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Jan 14, 2026

UNIT #3:

Number Representations for Arithmetic

Before doing operations, computers represent negative numbers in one of the following
ways:

a) Signed Magnitude

● MSB = sign bit (0 = +, 1 = −)

 ● Remaining bits = magnitude

● Two representations for zero (+0 and −0)

● Subtraction requires sign logic

b) 1’s Complement

● Negative number obtained by complementing each bit

● Also has two zeros

● Used in older systems

c) 2’s Complement

● Negative number = invert bits + 1

● Only one zero

● Simplifies hardware for addition/subtraction

Jan 14, 2026

UNIT #3: Addition and Subtraction

Binary Addition
Rules of Binary Addition

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Example – Unsigned Binary Addition
1011 (11 decimal)
+ 1101 (13 decimal)
--------
11000 (24 decimal)

Hardware Implementation

● Adders are basic building blocks in ALU

● Half Adder (HA): Adds 2 bits → produces Sum + Carry

● Full Adder (FA): Adds 3 bits (A, B, Carry-in) → efficient for multi-bit addition

Addition and Subtraction with Signed Magnitude Data

Addition Algorithm

The addition algorithm specifies that:

● If the signs of P and Q are the same, add both the magnitudes and put the sign of P to
the result, as shown in the table below.
● Compare both the magnitudes and subtract the small number from the greater number
when the signs of P and Q disagree.
● In cases where P > Q, the output signs must be equal to P, or the complement of P's sign
in cases where P < Q.
● Subtract Q from P and change the sign of the output to positive when the two
magnitudes are equal.

Subtraction Algorithm

The subtraction algorithm states that:

● When the signs of P and Q differ, the subtraction method says to add both the
magnitudes and put the sign of P to the result.
● Compare both the magnitudes and subtract the smaller number from the greater
number when the signs of P and Q are the same.
● In cases where P > Q, the output signs must be equal to P, or the complement of P's sign
in cases where P < Q.
● Subtract Q from P and change the sign of the output to positive when the two
magnitudes are equal.
Operations Addition of Magnitudes Subtraction of Magnitudes

P>Q P<Q P=Q

(+P) + (+Q) +(P+Q)

(+P) + (-Q) +(P-Q) -(Q-P) +(P-Q)

(-P) + (+Q) -(P-Q) +(Q-P) +(P-Q)

 (-P) + (-Q) -(P+Q)

(+P) - (+Q) +(P-Q) -(Q-P) +(P-Q)

(+P) - (-Q) +(P+Q)

(-P) - (+Q) -(P+Q)

(-P) - (-Q) -(P-Q) +(Q-P) +(P-Q)

Flowchart
 Flowchart for addition and subtraction

Hardware Implementation
 Hardware for signed-magnitude addition and subtraction

Example 1

Let's add two values, +3 and +2, using the signed magnitude representation.

Solution

We represent the given operands as shown below:

+3 = 0 0112

+2 = 0 0102

From the flowchart, we follow that A s xor Bs = 0. This implies that As = Bs

Also, according to the table,

Operations Addition of Magnitudes Subtraction of Magnitudes

(+P) + (+Q) +(P+Q)

So we do the addition of the magnitude of both operands.

Mag(+3) + Mag(+2) = 011 2 + 0102 = 1012 = Mag(5)

Now the sign of the result will be that of A s

Therefore, +3 + (+2) = 0 101 2 = +5

Example 2

Let's subtract two values, +3 and +2, using the signed magnitude representation.

Solution

We represent the given operands as shown below:

+3 = 0 0112

+2 = 0 0102

From the flowchart, we follow that A s xor Bs = 0. This implies that As = Bs

Also according to the table,

Operations Addition of Magnitudes Subtraction of Magnitudes

P>Q P<Q P=Q

(+P) - (+Q) +(P-Q) -(Q-P) +(P-Q)

Since the magnitude of P > Q,

We get results by +(P-Q).

Mag(Result) = 011 + (010)’ + 1 = 011 + 101 + 1 = (001)

SignBit(Result) = 0

Therefore, +3 - (+2) = +(+3-2) = +1

Addition and Subtraction with Signed 2’s Complement
Data
Here, the signed-2's complement form of integers is examined, as well as arithmetic techniques
for addition and subtraction. They've been summed up for your convenience. The sign bit is
represented by the leftmost bit of a binary number: 0 for positive and 1 for negative. The full
number is displayed in 2's complement form if the sign bit is 1. As a result, +33 is represented
as 00100001, and -33 is represented as 11011111. The 2's complement of 00100001 is 11011111,
and vice versa.

When two numbers are added in signed -2's complement form, the sign bits of the numbers are
regarded the same as the other bits of the number. The sign-bit position's carry-out is
disregarded.

The subtraction entails taking the subtrahend's 2's complement and then adding it to the
minuend.

Flowchart

Algorithm for addition and subtraction in signed-2’s complement representation

Hardware Implementation
 Hardware for signed-2’s complement addition and subtraction

Example 1

Let's use the 2's complement approach to add two decimal integers of +7 and +4.

Solution

The 2's complement representations of +4 and +7 with 5 bits each are shown below.

+710 = 001112

+410 = 001002

The addition of these two numbers is

(+710 ) + (+410 ) = 001112+ 001002

(+710 ) + (+410 ) = 010112

The resultant sum is 5 bits long. As a result, there is no carryover from the sign bit. The final
total is positive, as shown by the sign bit '0'. In the decimal number system, the magnitude of
the sum is 11. Therefore, the addition of two positive numbers will give another positive
number.

Example 2

Let's use the 2's complement approach to subtract two decimal integers of +7 and +4.

Solution

The subtraction of these two numbers is

(+410 ) − (+710 ) = (+410 ) + (−710)

The 2’s complement representations of +4 and -7 with 5 bits each are shown below.
+410 = 001002

−710 = 110012

(+410 ) + (−710 ) = 001002 + 110012 = 111012

Here, carry is not obtained from the sign bit. The final total is negative, as shown by the sign bit
'1'. As a result, we may determine the magnitude of the resultant sum as 3 in the decimal
number system by taking 2's complement of it. Therefore, the subtraction of two decimal
numbers, +4 and +7, is -3.

Jan 14, 2026

UNIT #3: Multiplication Algorithms

1. Binary Multiplication (Basic Concept)
● Binary multiplication is similar to decimal multiplication.

● Uses shift and add operations.

● Multiplicand is shifted left for each bit of the multiplier.

● If multiplier bit = 1 → add, if 0 → skip.

2. Shift-and-Add Multiplication Algorithm (Unsigned)

Algorithm Steps

1. Initialize Product = 0.

2. Examine LSB of multiplier.

3. If LSB = 1 → Product = Product + Multiplicand.

4. Shift multiplicand left by 1 bit.

5. Shift multiplier right by 1 bit.

6. Repeat until all multiplier bits are processed.

Example

Multiply: 101 (5) × 011 (3)

Multiplier bit = 1 → Add

Multiplier bit = 1 → Add
Multiplier bit = 0 → Skip

101 (5)
× 011 (3)
------
101
1010
------
1111 (15)

Block Diagram (Conceptual)

Advantages
 ● Simple hardware

● Easy to implement

Disadvantages

● Slow for large numbers

● Many shift and add operations

3. Signed Binary Multiplication

Signed numbers are represented using 2’s complement.
Normal shift-and-add becomes inefficient due to sign handling.

Solution: Booth’s Algorithm

4. Booth’s Multiplication Algorithm

Purpose

● Efficient multiplication of signed binary numbers

● Reduces number of additions and subtractions

Key Idea

Operation depends on:

● Current multiplier bit (Q₀)

● Previous bit (Q₋₁)

Rules

Q₀ Q₋₁ Operation

0 0 No operation

1 1 No operation
 0 1 Add multiplicand

1 0 Subtract
multiplicand

After each step → Arithmetic right shift

Algorithm Steps

1. Initialize:

○ A=0

○ Q = Multiplier

○ Q₋₁ = 0

2. Check (Q₀, Q₋₁)

3. Perform operation (Add/Subtract/None)

4. Arithmetic right shift (A, Q, Q₋₁)

5. Repeat for number of bits

Example

Multiply: +5 (0101) × −3 (1101)

● Booth’s algorithm automatically handles negative numbers.

● Final result obtained in 2’s complement form.

Booth’s Algorithm Diagram

Advantages

● Handles signed numbers

● Fewer additions/subtractions

● Faster than shift-and-add

Disadvantages

● Slightly complex control logic

5. Comparison of Multiplication Algorithms

Feature Shift-and-Add Booth’s Algorithm

Number Unsigned Signed

type
 Speed Slower Faster

Hardware Simple Moderate

Efficiency Low High

Used for Small numbers Large & signed

numbers

Jan 14, 2026

UNIT #3: Division Algorithms

1. Binary Division – Basic Idea
● Division is performed as a sequence of shift, subtract, and restore operations.

● Similar to long division in decimal arithmetic.

● Hardware produces Quotient and Remainder.

2. Restoring Division Algorithm

Concept

● After subtraction, if the partial remainder becomes negative, the original value is
restored.

● Hence the name restoring division.

Algorithm Steps

1. Initialize:

○ Remainder (A) = 0

○ Dividend (Q)
 ○ Divisor (M)

2. Shift left (A, Q) together.

3. Perform: A = A − M

4. If A ≥ 0:

○ Set Q₀ = 1

5. If A < 0:

○ Set Q₀ = 0

○ Restore A: A = A + M

6. Repeat for n bits of the dividend.

Example (Unsigned)

Divide: 13 ÷ 3

Dividend = 1101
Divisor = 0011

Step-by-step subtraction and restoration gives:

Quotient = 0100 (4)
Remainder = 0001 (1)

Restoring Division Diagram

Advantages

● Simple logic

● Easy to understand

Disadvantages

● Extra restoration step → slower

3. Non-Restoring Division Algorithm

Concept

● Avoids restoring step.

● Uses add or subtract based on sign of remainder.

● Faster than restoring division.

Algorithm Steps

1. Initialize:

○ A=0

○ Q = Dividend

○ M = Divisor

2. Shift left (A, Q).

3. If previous A ≥ 0 → A = A − M

4. If previous A < 0 → A = A + M

5. If A ≥ 0 → Q₀ = 1
Else → Q₀ = 0

6. Repeat for n bits.

7. If final A < 0 → A = A + M

Example

Divide: 13 ÷ 3

Uses alternate add∕subtract instead of restore.

Final Output:
Quotient = 0100
Remainder = 0001

Non-Restoring Division Diagram

Advantages

● Faster

● Fewer arithmetic operations

Disadvantages

● Slightly complex control logic

4. Signed Division (2’s Complement)

● Convert dividend and divisor to positive values.

● Perform unsigned division.

● Adjust sign of quotient:

○ Same sign → positive quotient

○ Different signs → negative quotient

● The remainder has the same sign as dividend.

5. Comparison of Division Algorithms

Feature Restoring Non-Restoring
Division Division

Restoration step Required Not required

Speed Slower Faster

Complexity Simple Moderate

Hardware Low High

efficiency
Jan 14, 2026

UNIT #3: Floating-point Arithmetic

Operations
1. Floating-Point Number Representation
A floating-point number is represented as:

Number=(−1)Sign×Mantissa×BaseExponent\text{Number} = (-1)^{Sign} \times Mantissa

\times Base^{Exponent}Number=(−1)Sign×Mantissa×BaseExponent

IEEE 754 Format (Most Common Standard)

● Sign bit (S) – indicates positive or negative

● Exponent (E) – represents power of base

● Mantissa / Fraction (M) – significant digits

| Sign | Exponent | Mantissa |

Used for representing very large or very small real numbers accurately.

2. Floating-Point Addition
Steps Involved

1. Compare Exponents

○ Shift the mantissa of the smaller exponent right

2. Align Mantissas

○ Make both exponents equal

 3. Add Mantissas

○ Perform binary addition

4. Normalize Result

○ Ensure mantissa is in standard form

5. Round Result

○ Adjust precision if required

Example (Conceptual)
X = 0.1101 × 2³
Y = 0.1011 × 2²

Step 1: Align exponents

Y → 0.01011 × 2³

Step 2: Add mantissas

0.1101
+0.01011
---------
1.00101 × 2³

Step 3: Normalize
0.100101 × 2⁴

Floating-Point Addition Diagram

3. Floating-Point Subtraction
Method

● Convert subtraction into addition:

A−B=A+(−B)A - B = A + (-B)A−B=A+(−B)

● Change sign of second operand

● Follow same steps as floating-point addition

Steps
 1. Compare exponents

2. Align mantissas

3. Subtract mantissas

4. Normalize

5. Round

Hardware treats addition and subtraction using the same circuitry.

4. Floating-Point Multiplication
Steps Involved

1. Multiply Mantissas

2. Add Exponents

3. Determine Sign

○ Same sign → positive

○ Different signs → negative

4. Normalize Result

5. Round if necessary

Example (Conceptual)
X = 0.101 × 2²
Y = 0.011 × 2³

Mantissa = 0.101 × 0.011

Exponent = 2 + 3 = 5
Floating-Point Multiplication Diagram

5. Floating-Point Division
Steps Involved
 1. Divide Mantissas

2. Subtract Exponents

3. Determine Sign

4. Normalize Result

5. Round Result

Example (Conceptual)
X = 0.110 × 2⁴
Y = 0.010 × 2²

Mantissa = 0.110 ÷ 0.010

Exponent = 4 − 2 = 2

Floating-Point Division Diagram

6. Normalization
● Ensures mantissa has only one non-zero digit before binary point

● Improves precision

● Required after addition, subtraction, multiplication, division

Example
1.0101 × 2³ → 0.10101 × 2⁴

7. Rounding Techniques
Used when mantissa exceeds allowed bits:

● Truncation

● Round to nearest

● Round toward zero

● Round toward infinity

Rounding errors are unavoidable in floating-point arithmetic.

8. Exceptions in Floating-Point Arithmetic

● Overflow – number too large

● Underflow – number too small

● Divide by zero

● Inexact result
9. Advantages of Floating-Point Arithmetic
✔ Can represent very large and very small numbers
✔ High precision
✔ Used in scientific and engineering applications

10. Disadvantages
Complex hardware
Rounding errors
Slower than fixed-point arithmetic

Jan 14, 2026

UNIT #3: Decimal Arithmetic Unit

1. Introduction
● A Decimal Arithmetic Unit (DAU) is a part of the Arithmetic Logic Unit (ALU)
designed to perform arithmetic operations on decimal numbers.

● Decimal numbers are usually represented in BCD (Binary Coded Decimal) format.

● DAU is mainly used where exact decimal precision is required, such as:

○ Banking systems

○ Financial calculations

○ Commercial applications

Binary arithmetic can cause rounding errors in decimal values, so DAU is preferred.

2. Binary Coded Decimal (BCD) Representation

 ● Each decimal digit (0–9) is represented using 4 bits.

Decimal BCD

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

BCD combinations from 1010 to 1111 are invalid.

3. Need for Decimal Arithmetic Unit

● Binary arithmetic may produce inexact decimal results.

● Decimal arithmetic ensures:

○ Accuracy

○ Correct rounding

○ No conversion errors

Hence, DAU directly operates on decimal digits instead of binary values.

4. Components of Decimal Arithmetic Unit
A typical DAU consists of:

1. BCD Adder

2. BCD Subtractor

3. Correction Logic

4. Registers

5. Control Unit

Block Diagram of Decimal Arithmetic Unit

5. Working of Decimal Arithmetic Unit
General Working

1. Decimal numbers are stored in BCD format.

2. Arithmetic operation (add/subtract) is performed.

3. If the result is invalid BCD, correction is applied.

4. Final valid BCD output is produced.

6. BCD Addition in DAU
Steps

1. Add two BCD digits using a binary adder.

2. Check for invalid BCD result:

○ If result > 9 or

○ Carry is generated

3. Add 0110 (decimal 6) to correct the result.

Example
0101 (5)
+ 0111 (7)
--------
1100 (12 → invalid BCD)

Correction:
1100 + 0110 = 1 0010

✔ Result = 12 in BCD

7. BCD Subtraction in DAU

Method Used

● 10’s complement method

Steps

1. Find 9’s complement of subtrahend.

 2. Add 1 → get 10’s complement.

3. Add to minuend.

4. Discard carry if present.

This method avoids complex borrow logic.

8. Decimal Arithmetic Unit Operations

Operation Method Used

Addition BCD addition + correction

Subtraction 10’s complement

Multiplication Repeated BCD addition

Division Repeated BCD subtraction

9. Advantages of Decimal Arithmetic Unit

✔ High accuracy
✔ No rounding errors
✔ Ideal for financial data
✔ Direct decimal processing

10. Disadvantages
More hardware required
Slower than binary arithmetic
Higher cost
Jan 14, 2026

UNIT #3: Decimal Arithmetic Operations

1. Introduction
● Decimal arithmetic operations are performed on decimal numbers represented in
BCD (Binary Coded Decimal) format.

● These operations are handled by the Decimal Arithmetic Unit (DAU).

● Decimal arithmetic ensures exact precision, especially important in financial and

commercial applications.

2. Decimal (BCD) Addition

Rule

● If the binary sum of two BCD digits is:

○ ≤ 9 → valid BCD

○ > 9 or carry generated → add 0110 (decimal 6) for correction

Steps for BCD Addition

1. Add two BCD digits using binary addition.

2. Check:

○ Sum > 1001 (9) OR

○ Carry = 1

3. If yes, add 0110.

 4. Result is valid BCD.

Example

Add: 27 + 15

0010 0111 (27)

+ 0001 0101 (15)
------------
0011 1100 (invalid BCD)

Add correction (0110) to lower digit:

0011 1100
+ 0000 0110
------------
0100 0010 (42)

✔ Result = 42

BCD Addition Diagram

3. Decimal (BCD) Subtraction
Method Used

● 10’s Complement Method

Steps

1. Find 9’s complement of each BCD digit of subtrahend.

2. Add 1 → get 10’s complement.

 3. Add this to the minuend.

4. If carry occurs, discard it → result is positive.

5. If no carry, take 10’s complement of result → result is negative.

Example

Subtract: 52 − 38

52 → 0101 0010
38 → 0011 1000

9’s complement of 38 → 0110 0001

Add 1 → 0110 0010

Add to 52:
0101 0010
+ 0110 0010
------------
1011 0100 (carry discarded)

Result = 14

4. Decimal Multiplication
Method

● Performed using repeated BCD addition and shifting.

Steps

1. Multiply each digit of multiplier with multiplicand.

 2. Use BCD addition for partial products.

3. Shift partial products appropriately.

4. Add all partial products.

Example

Multiply: 13 × 4

13 × 4 = 13 + 13 + 13 + 13
= 52

Used only for small numbers due to complexity.

5. Decimal Division
Method

● Performed using repeated BCD subtraction.

Steps

1. Subtract divisor from dividend repeatedly.

2. Count number of successful subtractions.

3. Count = Quotient

4. Remaining value = Remainder

Example
Divide: 25 ÷ 5

25 − 5 − 5 − 5 − 5 − 5 = 0
Quotient = 5
Remainder = 0

6. Comparison of Decimal Arithmetic Operations

Operation Technique Used

Addition BCD + correction

Subtraction 10’s complement

Multiplication Repeated addition

Division Repeated subtraction

7. Advantages of Decimal Arithmetic Operations

✔ Exact results
✔ No conversion errors
✔ Suitable for financial systems

8. Disadvantages
Slower than binary arithmetic
Complex hardware
High cost