Rashtreeya Sikshana Samithi Trust

RV Institute of Technology and Management®

(Affiliated to VTU, Belagavi)

JP Nagar, Bengaluru – 560076

Department of Computer Science and Engineering

Department of Information Science and Engineering

Course Name:Digital Design and Computer

Organization
Course Code: BCS302

III Semester

2022 Scheme
Prepared By:

Prof Padmasree N.
Prepared by
Padmasree N
Department of Computer Science and Engineering RVITM,
Bengaluru - 560076
Email: [Link]@[Link]

Pavithra M N
Department of Computer Science and Engineering RVITM,
Bengaluru - 560076
Email: [Link]@[Link]

Madhuri H D
Department of Computer Science and Engineering RVITM,
Bengaluru - 560076
Email: [Link]@[Link]
Module 2
Combinational Logic and Sequential logic

syllabus
Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary Adder- Subtractor,
Decoders, Encoders, Multiplexers. HDL Models of Combinational Circuits – Adder, Multiplexer, Encoder.
Sequential Logic: Introduction, Sequential Circuits, Storage Elements: Latches, Flip-Flops.
Text book 1: 4.1, 4.2, 4.4, 4.5, 4.9, 4.10, 4.11, 4.12, 5.1, 5.2, 5.3, 5.4.

Review of Combinational Circuit Design

Steps involved in the design of a combinational switching circuit:
1. Set up a truth table which specifies the output(s) as a function of the input variables. If a given combination
of values for the input variables can never occur at the circuit inputs, the corresponding output values are
don’t-cares.
2. Derive simplified algebraic expressions for the output functions using Karnaugh Maps, or Quine-
McCluskey method, or any other similar procedure. The resulting algebraic expressions are then manipulated
into the proper form, depending on the type of gates to be used in realizing the circuit.
3. When a circuit has two or more outputs, common terms in the output functions can often be used to
reduce the total number of gates or gate inputs.
4. Minimum two-level AND-OR, or NAND-NAND circuits can be realized using the minimum sum-of-
products. Minimum two-level OR-AND, or NOR-NOR circuits can be realized using the minimum product-
of-sums.

Multiplexers
It is a digital circuit with many inputs but only 1 output. By applying control-signals, we can steer any input
to output. Thus, it is also called a data-selector and control inputs are termed select inputs (Fig 3.1). The
circuit has n input signals, m control signals and 1 output signal. m control signals can select at the most 2m
input signals thus n ≤ 2m .
4:1 Multiplexer
• Depending on control inputs A and B, one of the 4 inputs D0 to D3 is steered to output Y as specified in Fig
3.14.
• The logic equation of the circuit (Fig: 3.1c) gives a SOP representation.
• Here, each AND gate generates a minterm which are finally summed by OR gate.

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In other words, for AB=00, the first AND gate to which D0 is connected remains active and equal to D0 and
all other AND gate are inactive with output held at logic 0. If D0=0, Y=0 and if D0=1, Y=1.
Similarly, for AB=01, second AND gate will be active and all other AND gates remain inactive. Thus,
output Y=D1.

Fig 3.14 a) Multiplexer Block Diagram, (b) 4-to-1 multiplexer truth table, (c) Its logic circuit

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Commercial multiplexer ICs come in integer power of 2, e.g. 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexers.
16-to-1 multiplexer
Fig 3.15 shows a 16-to-1 multiplexer. The input bits are labeled D0 to D15. Only one of these is transmitted
to the output. It depends on the value of ABCD, the control input. For instance, when ABCD= 0000

the upper AND gate is enabled while all other AND gates are disabled. Therefore, data bit D0 is transmitted
to the output, giving Y=D0. If D0 is low, Y is low; if D0 is high, Y is high. The output can be written as

Y= A'B'C'D'.D0 + A'B'C'D.D1 + A'B'CD'.D2 + ……… + ABCD'.D14 + ABCD.D15

74150
• The 74150 is a 16-to-1 TTL multiplexer. Pins 1 to 8 and 16 to 23 are for the input data bits D0 to D15. Pins
11, 13, 14, 15 are for control bits ABCD. Pin 10 is the output pin and it equals to the complement ofthe
selected data bit.
• Pin 9 is for the STROBE (an input signal) that disables or enables the multiplexer.
• A low strobe enables the multiplexer, so that output Y equals the complement of the input data bit:
Y=D'n where n is the decimal equivalent of ABCD. Fig 3.3 shows the pinout diagram of IC
• On the other hand, a high strobe disables the multiplexer and forces the output into the high state. With a
high strobe, the value of ABCD doesn't matter.

Fig 3.15 16-to-1 multiplexer

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Multiplexer logic
• Two standard methods for implementing a truth table are SOP and POS solutions. The third method is the
multiplexer solution. For example to use a 74150 to implement Table 3.1, complement each Y output to get
the corresponding data input.
D0=1'=0
D1=0'=1
….
….
D15=1'=0
• D0 is grounded, D1 is connected to +5V, D2 is grounded and so forth (Fig 3.16).
When ABCD=0000, D0 is the selected input. Since D0 is low, Y is high.
When ABCD=0001, D1 is the selected input. Since D1 is high, Y is low.
• The multiplexer is active (enabled) when the STROBE is low and inactive (disabled) when it is high. Because
of this, the STROBE is called an active low signal; it causes something to happen when it is low rather than
when it is high.

Fig 3.16 74150 IC and Truth Table

Multiplexer as Universal Logic Circuit
Multiplexer is called as universal logic circuit because a 2n-to-1 multiplexer can be used as a design
solution for any 'n' variable truth table.
We can implement the Truth Fig 3.17 using 8-to-1 multiplexer in following way:
Let's consider A, B and C variables to be fed as select inputs. The fourth variable D then has to be present as
data input. Here, EVM method can be used to convert 4-variable truth table into 3- variable truth table.

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 Fig 3.17 Multiplexer as Universal Logic Circuit and Truth Table
Nibble Multiplexers
Sometimes, we want to select 1 of two input nibbles. In this case, we can use a nibble multiplexer.
The control signal labeled SELECT determines which input nibble is transmitted to output (Fig: 3.18).
When SELECT=low, the four NAND gates on the left are activated. Therefore
Y3Y2Y1Y0=A3A2A1A0
When SELECT=high, the four NAND gates on the right are activated.
Therefore Y3Y2Y1Y0=B3B2B1B0

Fig 3.18 Nibble Multiplexer

Demultiplexers
It is a digital circuit with 1 input and many outputs (Fig: 3.19). By applying control signals, we can steer the
input signal to one of the output lines. The circuit has 1 input signal, m control or select signals and n output
signals where n ≤ 2m.

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1:16 Demultiplexer
The input data bit (D) is transmitted to the data bit of output lines depending on the value of ABCD, the control
input. When ABCD=0000, the upper AND gate is enabled while other AND gates are disabled. Therefore,
data bit D is transmitted only to the Y0 output, giving Y0=D. If D=low, Y0=low. If D=high, Y0=high. If the
control nibble is changed to ABCD=1111, all gates are disabled except the bottom AND [Link], D is
transmitted only to the Y15 output and Y15=D.

Fig 3.19 Demultiplexer Circuit Diagram and Truth Table

The 74154
74154 is a 1-to-16 demultiplexer. Pin 18 is for the input DATA D. Pins 20 to 23 are control bits ABCD. Pins1
to 11 and 13 to 17 are for output bits Y0 to Y15. Pin 19 for STROBE, it is an active low input. Pin 24 for VCC
and pin 12 for ground. STROBE must be low to activate the 74154. When the STROBE is low the control
input ABCD determines which output lines are low when the DATA input is low. When the DATA input is
high, all output lines are high. When STROBE is high, all output lines are high (Fig 3.20).

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 Fig 3.20 74154 is a 1-to-16 demultiplexer
Decoders
• It is a multiple-input, multiple-output logic circuit which converts coded inputs into coded outputs, where
the input and output codes are different (Figure: 3.10). It is similar to a demultiplexer with one exception that
there is no data input. The only inputs are the control bits.
1-of-16 Decoder
• 1-of-16 decoder is called so because only 1 of the 16 output lines is high.
• For instance, when ABCD=0001, only the Y1 AND gate has all inputs high, therefore only the Y1 output
is high. If ABCD=0100, only the Y4 AND gate has all inputs high, as a result Y4=high. For all combinations,
the subscript of the high output always equals the decimal equivalent of ABCD. Hence this circuit is called as
binary-to-decimal decoder.
IC 74154 is called a decoder-demultiplexer, because it can be used either as a decoder or as a demultiplexer.
To use this IC as decoder, we have to ground the DATA and STROBE inputs as shown in fig 3.11. Then, the
selected output line is in the low state. This is why bubbles are shown on the output lines. It means the output
line is low when it is active or selected. For instance, if the binary input is

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ABCD= 0111
Then the Y7 output is low, while all other- outputs are high.

Fig. 3.21 1-of-16 Decoder

BCD to Decimal Decoders
BCD- Binary Coded Decimal. The BCD code expresses each digit in a decimal number by its nibble
equivalent. Example decimal 429 in BCD is represented as 0100 0010 1001. Some early computers
processed BCD numbers. The decimal numbers were changed into BCD numbers, which the computer then
added, subtracted, etc. The final answer was converted from BCD back to decimal numbers. BCD digits are
from 0000 to 1001. All combinations above this (1010 to 1111) cannot exist in BCD. BCD- to Decimal
Decoder
The circuit of Fig 3.12 is called a 1-to-10 decoder because only 1 of the 10 output lines is high. For instance
when ABCD=0011, only the Y3 AND gate has all high inputs; therefore, only the Y3 output is high. If
ABCD= 1000, then only Y8 output is high and similar for rest of the ABCD combinations. The subscript of
the high output always equals the decimal equivalent of the input BCD digit. Hence the circuit is also called
as BCD-to-decimal converter

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 Fig. 3.22 BCD to Decimal Decoders
The 7445
TTL IC 7445 is available to convert BCD to decimal as shown in fig 3.33. Pin 16 connects to supply voltage
VCC and pin 8 is grounded. Pins 12 to 15 are for the BCD input (ABCD), while pins 1 to 7 and 9 to 11 are
for the outputs. Here the active output line is in the low state. All the other output lines are in the high
state as shown in table 3.3. Invalid BCD input(1010 to 1111) forces all output lines into the high state.

Fig. 3.23 TTL IC 7445

Seven Segment Decoders

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LED emits radiation when forward biased. This is because when free electrons recombine with holes near the
junction. As the free electrons fall from a higher energy level to a lower one, they give up energy in the form
of heat and light. The elements like gallium, arsenic, and phosphorus can emit red, green, yellow, blue, orange
and infrared (invisible) light.
Seven Segment Indicator
Fig 3.14 shows a seven segment indicator, i.e seven LEDs labeled a through g. By forward-biasing different
LEDs we can display digits from 0 to 9.
For example, to display 0, we need to light up segments a, b, c, d, e, and f.
To display 5, we need to light up segments a, c, d, f, and g.
Seven segment indicators may be the common-anode type where all anodes are connected together as in fig
3.15a or the common-cathode type where all cathodes are connected together as in fig 3.15b. With common
anode type, a current limiting resistor has to be connected between each LED and ground. The size of the
resistor determines how many current flows through the LED.
The typical LED current is between 1 and 50 mA. The common cathode type uses a current limiting resistor
between each LED and +VCC.

Fig. 3.24 Seven Segment Decoders

The 7446
A seven-segment decoder-driver is an IC decoder that can be used to drive a seven-segment indicator. There
are two types of decoder drivers. Both has 4 input pins(the BCD input) and 7 output pins(the a through g
segments)
7446- common- anode indicator
Fig 3.16a shows a 7446 driving a common anode indicator. Logic circuits inside 7446 convert the BCD input
to the required output. For instance, if the BCD input is 0111, the internal logic of 7446 will force LEDs a, b
and c to conduct. As a result digit 7 appears on seven segment indicator. External current limitingresistor are
used.
7448-Common- cathode indicator

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Fig 3.16b shows 7448 driving a common cathode indicator. The internal logic converts the BCD input to the
required output. When the BCD input is 0100, the internal logic forces the LEDs b, c, f, and g to conduct. The
seven segment indicator then displays a 4. 7448 has its own current limiting resistor on the chip.

Fig. 3.25 7448-Common- cathode indicator

Encoders
• It converts an active input signal into a coded signal.
• There are ‘n’ input lines, only one of which is active. Internal logic within the encoder converts this active
input to a coded binary output with ‘m’ bits. (fig 3.17)
Decimal to BCD Encoders
• The switches are push-button switches like those of a pocket calculator (Figure: 3.18).
• When button 3 is pressed, the C and D OR gates have high inputs, therefore the output is
ABCD=0011
If button 5 is pressed, output ABCD=0101
If button 9 is pressed, output ABCD=1001

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 Fig. 3.26 Decimal to BCD Encoders
The 74147
Fig 3.37a shows the pinout diagram for 74147, a decimal to BCD encoder. The decimal input X1 to
X9, connect to pins 1 to 5, and 10 to 13. The BCD output comes from pins 14, 6, 7, and 9. Pin 16 is for
the supply voltage, and pin 8 is grounded. The label NC on pin 15 means no connection.
Fig 3.19b shows how to draw a 74147. The bubbles indicate active-low inputs and outputs. Table 3.4 gives
the truth table. When all X inputs are high, all outputs are high. When X9 is low, the ABCD output is
LHHL(complement of 1001 (9)). When X8 is the only low input, ABCD is LHHH etc.

Fig. 3.27 pinout diagram for 74147

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The 74147 is called a priority encoder because it gives priority to the highest-order input. If all inputs X1
through X9 are low, highest of these, X9 has got highest priority and it is encoded. When X9 is high, X8 has
got next priority; it is encoded, if it is low.
Exclusive-OR Gates
This has a high output only when an odd number of inputs is high (Figure: 3.20).
• The upper AND gate forms the product A'B, while the lower one produces AB'. Therefore, the output of the
OR gate is Y=A'B+AB'
• This gate always produces an output 1 only when n-bit input has an odd number of 1s

Fig. 3.28 Exclusive-OR

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Arithmetic Building Blocks
Half-Adder
Half adder performs binary addition. It adds two bits. The following figure shows the circuit of half adder.
The output of EX-OR gate is called the SUM, while the output of AND gate is the CARRY.
The expression for SUM = B̅ + A ̅= A ⊕B

CARRY = AB

Fig. 3.40 Half-Adder

Full-Adder
Full adder can add three bits at a time (Fig 3.41). The third bit is a carry from a lower column.
Expressions:
Carry = AB+BC+AC
Sum = A ⊕B ⊕C

General representation of full-adder which adds i-th bit Ai and Bi of two numbers A and B and takes carry
from (i-1)th bit could be represented as below:
Ci = AiBi + BiCi-1 + AiCi-1
Ci = AiBi + (Ai + Bi)Ci-1
Si= Ai⊕Bi⊕Ci-1

Fig. 3.41 Full-Adder

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 HDL Models of Combinational Circuits – Adder, Multiplexer, Encoder.

A combinational circuit that performs the addition of two bits is called a half-adder. This circuit needs two binary
inputs and produces two binary outputs. One of the input variables designates the augend and other designates
the addend. The output variables produce the sum and the [Link] simplified Boolean functions of the two
outputs can be obtained as below:
Sum S = x’y + xy’
Carry C = xy
Procedure:
1. The half-adder circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in xilinx and simulated.
4. Signals are provided and output Waveforms are viewed.

Program:
Behavioral Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity habeh1 is
Port ( a,b: in STD_LOGIC;
s,c: out STD_LOGIC;
architecture behavioral of habeh1 is

begin

ha: process (a, b)

begin
if a = '1' then
s<= not b;
c <= b;
else
s<= b;
c<= '0';
end if;
end process ha;
end behavioral;
Dataflow Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity haf1 is
port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);

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 end haf1;
architecture dataflow of haf1 is

begin

s<= a xor b;

c<= a and b;
end dataflow;

Structural Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity has1 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end has1;

architecture structure of has1 is

component xor_gate
port (i1, i2: in std_logic;

o1: out std_logic);

end component;
component and_gate

port (i1, i2: in std_logic;

o1: out std_logic);

end component;

begin

u1: xor_gate port map (i1 => a, i2 => b, o1 => s);

u2: and_gate port map (i1 => a, i2 => b, o1 => c);

end structure

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Logic Diagram:

MULTIPLEXER

A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. Multiplexing means transmitting a large number of information units over a
smaller number of channels or lines. The selection of a particular input line is controlled by a set of selection
lines. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
selected. In general, a 2n – to – 1 line multiplexer is constructed from an n – to 2ndecoder by adding to it 2n input
lines, one to each AND gate. The outputs of the AND gates are applied to a single OR gate to provide the 1 – line
output.
Procedure:
1. The multiplexer circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in xilinx and simulated.
4. Signals are provided and Output Waveforms are viewed.
Program:
Behavioral Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
architecture behavioral of mux is

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begin
process (a,b,c,d,s0,s1) is
begin
if (s0 ='0' and s1 = '0') then
y <= a;
elsif (s0 ='1' and s1 = '0') then
y <= b;
elsif (s0 ='0' and s1 = '1') then
y <= c;
else
y <= d;
end if;
end process;
end behavioral;
Data Flow Model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity muxd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end muxd;
architecture Behavioral of muxd is
begin
y <= ((not s0) and (not s1) and a) or
((not s0) and s1 and b) or
(s0 and (not s1) and c) or
(s0 and s1 and d);
end behavioral;
Structural model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity muxs is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
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c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end muxs;
architecture behavioral of muxs is
component mux21 is
port(a: in std_logic;
b: in std_logic;
s: in std_logic;
y: out std_logic);
end component;
signal p,q: std_logic;
begin
u1:mux21 port map (a,b,s1,p);
u2: mux21 port map (c,d,s1,q);
u3:mux21 port map (p,q,s0,y);
end behavioral;
Logic Diagram:

Truth Table:

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 ENCODER

An Encoder is a combinational circuit that performs the reverse operation of [Link] has maximum of 2^n
input lines and 'n' output lines, hence it encodes the information from 2^n inputs into an n-bit code. It will
produce a binary code equivalent to the input, which is active high.
Procedure:
1. The encoder circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in xilinx and simulated.
4. Signals are provided and Output Waveforms are viewed.
Program:
Data Flow Model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC);
end encoder;
architecture behavioral of encoder is
begin
y0<=((not a)and (not b))and (c xor d);
y1<=((not a)and (not c))and (b xor d);
end behavioral;
Behavioral Model:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ec is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (1 downto 0));
end ec;
architecture behavioral of ec is
begin
process(a) is
begin
if (a="0000") then

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 y<= "00";
elsif (a="0001") then
y<="01";
elsif (a="0010") then
y<="10";
else
y<="11";
end if;
end process;
end behavioral;
Logic Diagram:

Truth Table:

Page 35 of 33
 SEQUENTAIL CIRCUITS:
A sequential circuit refers to a special type of circuit. It consists of a series of various inputs and outputs. Here,
the outputs depend on a combination of both the present inputs as well as the previous outputs. This previous
output gets treated in the form of the present state. Thus, the sequential circuit consists of the combinational
circuit along with its memory storage elements. It doesn’t need to consist of a combinational circuit all the
time. A sequential circuit can basically contain only the memory element.

Types of Sequential Circuits

There are basically two types of sequential circuits:

1. Asynchronous sequential circuits

2. Synchronous sequential circuits

1. Asynchronous Sequential Circuits

The asynchronous sequential circuits don’t make use of the clock signals. This type of circuit is operated
through various pulses. Thus, the changes in our input can easily make a change in the state of our circuit.
Clock pulses are not used in the case of asynchronous circuits. Here, the internal state gets altered whenever
there is a change in the input variable. The time-delayed or the unclocked flip-flops form the memory elements
of the asynchronous sequential circuits. This type of circuit is very similar to that of the combinational circuits
along with the feedback.

2. Synchronous Sequential Circuits

The clock signal performs the synchronization of the state of memory elements in the case of synchronous
sequential circuits. The output, in this case, is either stored in latches (memory devices) or flip-flops. The
output gets synchronized with the clock’s only positive edges or only the negative edges.

sequential circuit produces an output based on current input and previous output variables. That means
sequential circuits include memory elements that are capable of storing binary information. That binary
information defines the state of the sequential circuit at that time. A latch capable of storing one bit of
information.
Advantages of Sequential Circuits:

1. Memory: Sequential circuits have the ability to store binary values, which makes them ideal for
applications that require memory elements, such as timers and counters.
2. Timing: Sequential circuits are commonly used to implement timing and synchronization in
digital systems, making them essential for real-time control applications.

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 3. State machine implementation: Sequential circuits can be used to implement state machines,
which are useful for controlling complex digital systems and ensuring that they operate as
intended.
4. Error detection: Sequential circuits can be designed to detect errors in digital systems and
respond accordingly, improving the reliability of digital systems.

Disadvantages of Sequential Circuits:

1. Complexity: Sequential circuits are typically more complex than combinational circuits and
require more components to implement.
2. Timing constraints: The design of sequential circuits can be challenging due to the need to ensure
that the timing of the inputs and outputs is correct.
3. Testing and debugging: Testing and debugging sequential circuits can be more difficult compared
to combinational circuits due to their complex structure and state-dependant outputs.
In conclusion, sequential circuits have their advantages and disadvantages, but they play an important role in
digital systems design due to their ability to store and use binary values, implement timing and
synchronization, and implement state machines.

LATCHES & FLIP-FLOPS

Sequential switching circuits have the property that the output depends not only on the present input but also on
the past sequence of inputs. In effect, these circuits must be able to “remember” something about the past history
of the inputs in order to produce the present output. Latches and flip-flops are commonly used memory devices
in sequential circuits. Basically, latches and flip-flops are memory devices which can assume one of two stable
output states and which have one or more inputs that can cause the output state to change.
SET RESET LATCH:

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A simple latch can be constructed by introducing feedback into a NOR-gate circuit, as given in the following
Figure (a). As indicated, if the inputs are S = R = 0, the circuit can assume a stable state with Q =0 and P =
1.

Fig 4.12 Conditions S=1, R=0 and S=1 R=1

(a) S = 0 & R = 0: A stable condition of the circuit because P = 1 feeds into the second gate forcing the
output to be Q = 0, and Q = 0 feeds into the first gate allowing its output to be 1.
(b) S = 1 & R = 0: An unstable condition or state of the circuit because both the inputs and output of the

second gate are 0; therefore Q will change to 1, leading to the stable state.

Fig 4.13 Conditions S=0, R=0 and S=0 R=1

(a) S = 0 & R = 0: The circuit will not change state because Q = 1 feeds back into the first gate, causing P to
remain 0 as in Fig 4.13.
Note that the inputs are again S = 0 & R = 0, but the outputs are different than those with which we started.
Thus, the circuit has two different stable states for a given set of inputs.
(b) S = 0 & R = 1: Q will become 0 and P will then change back to 1. An input S = 1 sets the output to Q = 1,
and an input R = 1 resets the output to Q = [Link] circuit is commonly referred to as a set-reset (S-R) latch
(restriction that R and S cannot be 1 simultaneously).
This circuit is said to have memory because its output depends not only on the present inputs, but also on the past
sequence of inputs. If we restrict the inputs so that R = S = 1 is not allowed, the stable states of the outputs P and
Q are always complements, that is, P = Q’. To emphasize the symmetry between the operation of the two gates,
the circuit is often drawn in cross-coupled form, as shown in the following Figure (a).

If S = R = 1, the latch will not operate properly, as shown in above Fig 4.14 (c). Note that, when S and R are
both l, P and Q are both 0. Therefore, P is not equal to Q’, and this violates a basic rule of latch operation.
The following Figure shows a timing diagram for the S-R latch. Note that when S changes to 1 at time tl, Q
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changes to 1 a short time (ɛ - response time or delay time of latch) later. At time t2, when S changes back to
0, Q does not change. At time t3, R changes to 1, and Q changes back to 0 a short time (ɛ) later.
The duration of the S (or R) input pulse must normally be at least as great as ɛ in order for a change in the
state of Q to occur as in Fig 4.15.

Fig 4.15 SR Latch Timing Diagram

When discussing latches and flip-flops, we use the term present state to denote the state of the Q output of the
latch or flip-flop at the time any input signal changes, and the term next state to denote the state of the Q
output after the latch or flip-flop has reacted to the input change and stabilized. If we let Q(t) represent the
present state and Q(t + ɛ) represent the next state, an equation for Q(t + ɛ) can be obtained from the circuit by
conceptually breaking the feedback loop at Q and considering Q(t) as an input and Q(t + ɛ) as the [Link]
for the S-R latch;

The equation for output P is;

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These equations are mapped in the next-state and output tables as given in the following Table. The stable
states of the latch are circled. Note that for all stable states, P = Q except when S = R = 1. Making S = R =
1, a don‟t-care combination allows simplifying the next-state equation.

Fig 4.16
An equation that expresses the next state of a latch in terms of its present state and inputs will be referred to
as a next-state equation, or characteristic equation.
An alternative form of the S-R latch uses NAND gates, as shown in the following Fig 4.17.

Fig 4.17 SR Latch

Applications of S-R Latch: S-R latch is often used as a component in more complex latches and flip-flops
and in asynchronous systems. Another useful application of the S-R latch is for debouncing switches.
When a mechanical switch is opened or closed, the switch contacts tend to vibrate or bounce open and closed
several times before settling down to their final position. This produces a noisy transition, and this noise can
interfere with the proper operation of a logic circuit. The input to the switch in the following Figure is connected
to a logic 1 (+ V). The pull-down resistors connected to contacts a and b assure that when the switch is between
a and b the latch inputs S and R will always be at a logic 0, and the latch output will not

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change state. The timing diagram shows what happens when the switch is flipped from a to b. As the switch
leaves a, bounces occur at the R input; when the switch reaches b, bounces occur at the S input. After the
switch reaches b, the first time S becomes 1, after a short delay the latch switches to the Q = 1 state and
remains there. Thus Q is free of all bounces even though the switch contacts bounce.
GATED D LATCH:
A gated D latch (given in Fig 4.18 below) has two inputs—a data input (D) and a gate input (G). The D latch
can be constructed from an S-R latch and gates. When G = 0, S = R = 0, so Q does not change. WhenG = 1
and D = 1, S = 1 and R = 0, so Q is set to 1. When G = 1 and D = 0, S = 0 and R = 1, so Q is reset to
0. In other words, when G = 1, the Q output follows the D input, and when G = 0, the Q output holds the last
value of D (no state change). This type of latch is also referred to as a transparent latch because when G = 1,
the Q output is the same as the D input. From the truth table, the characteristic equation for the latch is + = ′
+ GD

Fig 4.18 gated D latch

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 EDGE-TRIGGERED D FLIP-FLOP:
A D flip-flop has two inputs, D (data) and Ck (clock). The small arrowhead on the flip-flop symbol identifies
the clock input. Unlike the D latch, the flip-flop output changes only in response to the clock, not to a change
in D.
o If the output can change in response to a 0 to 1 transition on the clock input, we say that the flipflop is
triggered on the rising edge (or positive edge) of the clock.
o If the output can change in response to a 1 to 0 transition on the clock input, we say that the flipflop is
triggered on the falling edge (or negative edge) of the clock.
o An inversion bubble on the clock input indicates a falling-edge trigger (Fig 4.19 (b)), and no bubble
indicates a rising-edge trigger (Figure (a)).
The term active edge refers to the clock edge (rising or falling) that triggers the flip-flop state change.

Fig 4.19 D FF
Since, the Q output of the flip-flop is the same as the D input, except that the output changes are delayed until
after the active edge of the clock pulse, as illustrated in the following Fig 4.20.

Fig 4.20 D FF Timing Diagram

A rising-edge-triggered D flip-flop can be constructed from two gated D latches and an inverter, as shown in
Figure the following Fig 4.21 (a). The timing diagram is shown in Fig 4.21 (b).

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 Fig 4.21 D flip-flop
When CLK = 0, G1 = 1, and the first latch is transparent so that the P output follows the D input. Because G2
= 0, the second latch holds the current value of Q. When CLK changes to 1, G1 changes to 0, and the current
value of D is stored in the first latch. Because G2 = 1, the value of P flows through the second latch to the Q
output. When CLK changes back to 0, the second latch takes on the value of P and holds it and, then, the first
latch starts following the D input again. If the first latch starts following the D input before the second latch
takes on the value of P, the flip-flop will not function properly. Therefore, the circuit designers must pay
careful attention to timing issues when designing edge-triggered flip-flops. With this circuit, output state
changes occur only following the rising edge of the clock. The value of D at the time of the rising edge of the
clock determines the value of Q, and any extra changes in D that occur between rising clock edges have no
effect on Q.
A flip-flop changes state only on the active edge of the clock, the propagation delay of a flip-flop is the time
between the active edge of the clock and the resulting change in the output. However, there are also timing
issues associated with the D input.
To function properly, the D input to an edge-triggered flip-flop must be held at a constant value for a period
of time before and after the active edge of the clock. If D changes at the same time as the active edge, the
behavior is unpredictable.
The amount of time that the D input must be stable before the active edge is called the setup time (tsu), and
the amount of time that the D input must hold the same value after the active edge is the hold time (th). The
times at which D is allowed to change during the clock cycle are shaded in the timing diagram of the following
Fig 4.22.

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 Fig 4.22 Set Up Time and Hold Time
The propagation delay (tp) from the time the clock changes until the Q output changes is also indicated in the
above Figure. Using these timing parameters, we can determine the minimum clock period for a circuit which
will not violate the timing constraints. Consider the circuit of following Fig 4.23 (a). Suppose the inverter has
a propagation delay of 2 ns, and suppose the flip-flop has a propagation delay of 5 ns and a setup time of 3 ns.
(The hold time does not affect this calculation). Suppose, as in following Figure (b), that the clock periodis 9
ns, i.e., 9 ns is the time between successive active edges (rising edges for this figure). Then, 5 ns after a clock
edge, the flip-flop output will change, and 2 ns after that, the output of the inverter will change. Therefore, the
input to the flip-flop will change 7 ns after the rising edge, which is 2 ns before the next risingedge. But the
setup time of the flip-flop requires that the input be stable 3 ns before the rising edge; therefore,the flip-flop
may not take on the correct value. Suppose instead that the clock period were15 ns, as in following Figure (c).
Again, the input to the flipflop will change 7 ns after the rising edge. However, becausethe clock is slower,
this is 8 ns before the next rising edge. Therefore, the flip-flop will work properly. Note in Figure (c) that there
is 5 ns of extra time between the time the D input is correct and the time when it mustbe correct for the setup
time to be satisfied. Therefore, we can use a shorter clock period, and have less extratime, or no extra time.
Figure (d) shows that 10 ns is the minimum clock period which will work for this circuit.

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 Fig 4.23 propagation delay (tp) from the time the clock
S-R FLIP-FLOP:
An S-R flip-flop (following Fig 4.24) is similar to an S-R latch in that S = 1 sets the Q output to 1, and R =
1 resets the Q output to 0. The essential difference is that the flip-flop has a clock input, and the Q output can
change only after an active clock edge.

Fig 4.24 S-R flip-flop

The truth table and characteristic equation for the flip-flop are the same as for the latch, but the interpretation of
Q+ is different. For the latch, Q+ is the value of Q after the propagation delay through the latch, while for the flip-
flop, Q+ is the value that Q assumes after the active clock edge. The following Figure (a) shows an S-R flip- flop
constructed from two S-R latches and gates. This flipflop changes state after the rising edge of the clock. The
circuit is often referred to as a master-slave flipflop. When CLK = 0, the S and R inputs set the outputs ofthe master
latch to the appropriate value while the slave latch holds the previous value of Q. When

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the clock changes from 0 to 1, the value of P is held in the master latch and this value is transferred to the
slave latch. The master latch holds the value of P while CLK = 1, and, hence, Q does not change. When the
clock changes from 1 to 0, the Q value is latched in the slave, and the master can process new inputs. Figure
(b) shows the timing diagram. Initially, S = 1 and Q changes to 1 at t1. Then R = 1 and Q changes to 0 at t3.

Fig 4.25 Master Slave S-R flip-flop

For a rising-edge-triggered flip-flop, the value of the inputs is sensed at the rising edge of the clock, and the
inputs can change while the clock is low. For the master-slave flip-flop, if the inputs change while the clock
is low, the flip-flop output may be incorrect. For example, (in above Figure (b)), at t4, S = 1 and R = 0, so P
changes to 1. Then S changes to 0 at t5, but P does not change, so at t5, Q changes to 1 after the rising edge
of CLK. However, at t5, S = R = 0, so the state of Q should not change. We can solve this problem if we only
allow the S and R inputs to change while the clock is high.
J-K FLIP-FLOP:
The J-K flip-flop (shown in the following Fig 4.26) is an extended version of the S-R flip-flop. The J-K flip-flop
has three inputs—J, K, and the clock (CLK). The J input corresponds to S, and K corresponds to R. That is, if J =
1 and K = 0, the flip-flop output is set to Q = 1 after the active clock edge; and if K = 1 and J = 0, the flip-flop
output is reset to Q = 0 after the active edge. Unlike the S-R flip-flop, a 1 input may be applied

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simultaneously to J and K, in which case the flip-flop changes state after the active clock edge. When J = K
= 1, the active edge will cause Q to change from 0 to 1, or from 1 to 0. The next-state table and
characteristic equation for the J-K flip-flop are given in Figure (b).

Fig 4.26
Figure 4.26 (c) shows the timing for a J-K flip-flop. This flip-flop changes state a short time (tp) after the
rising edge of the clock pulse, provided that J and K have appropriate values. If J = 1 and K = 0 when Clock
= 0, Q will be set to 1 following the rising edge. If K = 1 and J = 0 when Clock = 0, Q will be set to 0 after
the rising edge. Similarly, if J = K = 1, Q will change state after the rising edge. Referring to Figure 11- 20(c),
because Q = 0, J = l, and K = 0 before the first rising clock edge, Q changes to 1 at t1. Because Q = 1,J = 0,
and K = 1 before the second rising clock edge, Q changes to 0 at t2. Because Q = 0, J = 1, and K = 1 before
the third rising clock edge, Q changes to 1 at t3. One way to realize the J-K flip-flop is with two S-R latches
connected in a master-slave arrangement, as shown in the following Figure.

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 Fig 4.27 Master Slave JK FF
This is the same circuit as for the S-R master-slave flip-flop; except S and R have been replaced with J and K,
and the Q and Q outputs are feeding back into the input gates. Because S = JQ’Clk’ and R = K’QClk’, onlyone
of S and R inputs to the first latch can be 1 at any given time. If Q = 0 and J = 1, then S = 1 and R
= 0, regardless of the value of K. If Q = 1 and K = 1, then S = 0 and R = 1, regardless of the value of J.
T FLIP-FLOP:
The T flip-flop, also called the toggle flip-flop, is frequently used in building counters. Most CPLDs and
FPGAs can be programmed to implement T flip-flops. The T flip-flop (shown in the following Fig 4.28) has
a T input and a clock input. When T = 1 the flipflop changes state after the active edge of the clock. When T
= 0, no state change occurs. The next-state table and characteristic equation for the T flip-flop are given in
Figure (b). The characteristic equation states that the next state of the flip-flop (Q+) will be 1 iff the present
state (Q) is 1 and T = 0 or the present state is 0 and T = 1.

Fig 4.28 T FF Truth Table

The following Fig 4.29 shows a timing diagram for the T flip-flop. At times t2 and t4 the T input is 1 and the
flip-flop state (Q) changes a short time (tp) after the falling edge of the clock pulse. At times tl and t3 theT
input is 0, and the clock edge does not cause a change of state.

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 Fig 4.29 T FF Timing Diagram
One way to implement a T flip-flop is to connect the J and K inputs of a J-K flip-flop together, as shown in
the following Figure (a). Substituting T for J and K in the J-K characteristic equation gives; + = ′ + ′
= ′ + ′ which is the characteristic equation for the T flip-flop. Another way to realize a T flip-flop is with a D flip-flop and an exclusive-
OR gate [Figure (b)]. The D input is Q ⊕ T, so Q+ = Q ⊕ TQ’ + T’Q, which is the characteristic equation for the T flip-flop.

FLIP-FLOPS WITH ADDITIONAL INPUTS:

Flip-flops often have additional inputs which can be used to set the flip-flops to an initial state independent of
the clock. The following Fig 4.30 shows a D flip-flop with clear and preset inputs. The small circles (inversion
symbols) on these inputs indicate that a logic 0 (rather than a 1) is required to clear or set the flip-flop. This
type of input is often referred to as active-low because a low voltage or logic 0 will activate the clear or preset
function. We will use the notation ClrN or PreN to indicate activelow clear and preset inputs. Thus, a logic 0
applied to ClrN will reset the flip-flop to Q = 0, and a 0 applied to PreN will set the flip-flop to Q = 1.
These inputs override the clock and D inputs. That is, a 0 applied to the ClrN will reset the flip-flop regardless
of the values of D and the clock. ClrN and PreN are often referred to as asynchronous clear and preset inputs
because their operation does not depend on the clock.

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 Fig 4.30 FLIP-FLOPS WITH ADDITIONAL INPUTS
The above table (Figure (b)) summarizes the flip-flop operation. In the table, c indicates a rising clock edge, and
X is a don‟t-care. The last row of the table indicates that if Clk is held at 0, held at 1, or has a falling edge, Q does
not change. The following Figure illustrates the operation of the clear and preset inputs. At t1, ClrN
= 0 holds the Q output at 0, so the rising edge of the clock is ignored. At t2 and t3, normal state changes occur
because ClrN and PreN are both 1. Then, Q is set to 1 by PreN = 0, but Q is cleared at t4 by the rising edge
of the clock because D = 0 at that time.

Fig 4.31 D FF Timing Diagram

In synchronous digital systems, the flip-flops are usually driven by a common clock so that all state changes
occur at the same time in response to the same clock edge. When designing such systems, we frequently
encounter situations where we want some flip-flops to hold existing data even though the data input to the
flip-flops may be changing. One way to do this is to gate the clock, as shown in the following Figure (a).

Fig 4.32 D FFSymbols

When En = 0, the clock input to the flip-flop is 0, and Q does not change. This method has two potential
problems. First, gate delays may cause the clock to arrive at some flip-flops at different times than at other
flip-flops, resulting in a loss of synchronization. Second, if En changes at the wrong time, the flipflop may
trigger due to the change in En instead of due to the change in the clock, again resulting in loss of

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 synchronization. Rather than gating the clock, a better way is to use a flip-flop with a clock enable (CE). Such
flip-flops are commonly used in CPLDs and FPGAs. Figure (b) shows a D flip-flop with a clock enable, which
we will call a D-CE flip-flop. When CE = 0, the clock is disabled and no state change occurs, so Q+ = Q.
When CE = 1, the flip-flop acts like a normal D flip-flop, so Q+ = D. Therefore, the characteristic equation is
Q+ = Q•CE’ + D•CE. The D-CE flip-flop is easily implemented using a D flip- flop and a multiplexer (Figure
(c)). For this circuit, the MUX output is Q+ = D + Q•CE + Din•CE. Since, there is no gate in the clock line;
this cannot cause a synchronization problem.
Characteristic Equations of Flip-Flop:
The characteristics equations of flip-flops are useful in analyzing circuits made of them. Here, next output,
Qn+1, is expressed as a function of present output Qn and the input to the flip-flops. Karnaugh map can be
used to get the optimized expression.
S R Flip Flop

Fig 4.34 SR FF K Map

D Flip-Flop:

Fig 4.35 F FF K Map

JK Flip-Flop:

Fig 4.36 JK FF K Map

T Flip-Flop:
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 Fig 4.37 T FF K Map
Characteristic Equations of SR, D, JK & T Flip-Flops
The characteristic equations for the latches and flip-flops discussed so far are:

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