CS
MM cCOLEGE OF
ENGINEERING
Smce 1982
MVJCOLLEGE OF ENGINEERING, BENGALURU
An Autonomous Institute affiliated to Visvesvaraya Technological University, Belagavi,
Approved by AICTE,
Recognized by UGC under 2() and 12(B). Accredited by NBA &NAAC
ODD Semester -2025-26
CIE-Question Paper
Department of Computer Science and Engineering
(Common to CSE Allied Branches)
Semester III CIE Test No II
Course Digital Design and Computer
Code MVJ22/AI/CD/CG/CS/IS33 Course Title Organization
Duration 1 hour 3O minutes Max. Marks 50 Marks
Note:
Answer all Questions in Part-A.
Answer any Two fullquestions in Part Band Part C
CO Code Course Outcomes
CO1 Apply the functionalities of binary logic system
CO2 Analyse the working of combinational and sequential logic system
CO3 Analyse the basic structure of computer system
CO4 Analyse the working of I/O operations and processing unit.
COS Apply the functionalities of basic processingunits
Revised Bloom's Taxonomy Levels: L1 - Remembering, L2 - Understanding. L3 -Applying.
L4 -Analyzing, L5- Evaluating, and L6 - Creating
PART-A (5*2=10 Marks)
Q. No. Question Marks
1 List the four common conditional flags.
2
Differentiate between Big endian and Little endian byte addressability.
Define Indirect mode of addressing. Give an example. 2
Give the hierarchy of cache memory.
2
5 Define Bus arbitration and mention its types.
PART-B (2*10=20 Marks)
CO RBT
Module-3 Marks
Code Level
Apply steps needed to execute the machine instruction CO3 L3 10
1
Add LOCA, RO
Examine the various generic addressing modes with CO3 L4 10
2
examples.
For the given expression (A+B) * (C+D) Construct the
assembly language instructions using
3 a 1. Three-Address Instructions CO3 L4 10
2. Two-Address Instructions
3. One-Address Instructions
PART-C (2*10=20 Marks)
CO RBT
Module- 4 Marks
Code Level
4 a
Illustrate the three different types of mapping functions CO4 L3 10
with neat diagram
COLEGE OF
ENGINEERING
Snce 192
MVJ COLLEGE OF ENGINEERING, BENGALURU CS
An Autonomous Institute affiliated to Visvesvaraya Technological University, Belagavi,
Approved by AICTE,
Recognized by UGC under 2() and 12(B), Accredited by NBA SNAAC
ODD Semester -2025-26
CIE-Question Paper
Department of Computer Science and Engineering
(Common to CSE Allied Branches)
Semester CIE Test No II
Course Digital Design and Computer
Code MVJ22/AI/CD/CG/CS/IS33 Course Title Organization
Duration 1 hour 30 minutes Max. Marks 50 Marks
Note:
Answer all Questions in Part-A.
Answer any Two full questions in Part Band Part C
COCode Course Outcomes
CO1 Apply the functionalities of binary logic system
CO2 Analyse the working of combinational and sequential logic system
CO3 Analyse the basic structure of computer system
CO4 Analyse the working of /O operations and processing unit.
COS Apply the functionalities of basic processing units
Revised Bloom's Taxonomy Levels: L1 - Remembering, L2 - Understanding, L3 - Applying.
L4 -Analyzing, L5 - Evaluating, and L6 - Creating
PART-A (5*2=10 Marks)
Q. No. Question Marks
1 List thefour common conditional flags. 2
2
Differentiate between Big endian and Little endian byte addressability. 2
Define Indirect mode of addressing. Give an example.
4 Give the hierarchy of cache memory. 2
5 Define Bus arbitration and mention its types. 2
PART-B (2*10-20 Marks)
Module-3 CO RBT
Marks
Code Level
1 Apply steps needed to execute the machine instruction
a CO3 L3 10
Add LOCA, RO
2 Examine the various generic addressing modes with CO3 L4 10
examples.
For the given expression (A+B) * (C+D) construct the
assembly language instructions using
3 1. Three-Address Instructions CO3 L4 10
2. Two-Address Instructions
3. One-Address Instructions
PART-C (2*10=20Marks)
Module- 4 CO RBT
Marks
Code Level
4 a
Illustrate the three different types of mapping functions
with neat diagram CO4 L3 10
COUEGE OF
ENGINEERING
Stnce 1982
MVJCOLLEGE OF ENGINEERING, BENGALURU
An Autonomous Institute affiliated to Visvesvaraya Technological University, Belagavi,
Approved by AICTE,
Recognized by UGC under 2(f) and 12(B), Accredited by NBA &NAAC
ODD Semester -2025-26
CIE-Question Paper
Summarize the sequence of events involved in handling
5 an interrupt request from a single device by assuming CO4 L2 10
interrupts are enabled
6 Demonstrate the approaches involved in handling CO4 L3 10
simultaneous interrupt request from multiple devices
Principal
MJ COLLEGE OF
ENGINEERING
AnAutonomouslnstitute
NEARITPB,CHANNASANDRA, BENGALURU-S60067
Affiliated to VTU,
Recognized by UGC underBelagaviApprovedbyAICTE,NewDelhi
2(0) &12(B)Accreditedby NBA&NAAC
DEPARTMENT OF CSE/ISE/CSD/AIML/CD
ODDSemester (2025 -2026)
Scheme& Solutions
Internal assessment: III
Subject Code: MVJ22 CS/IS/CGIAI/CD33
Subject Name: Digital Design and
Question Computer Organization Semester: V
Number Solution
Marks
Allocate
Part-A
1. List the four common conditional flags.
Zero (Z): Set if result = 0. 2M
Carry (C): Set if carry/borrow occurs.
Sign (S): Indicates sign of result.
Overflow (0): Set if arithmetic overflow occurs.
2 Differentiate between Big endian and Little endian byte
Big Endian: Stores the most significant byte (MSB) at theaddressability.
2M
lowest
Little Endian: Stores the least significant byte (LSB) at the lowestmemory address.
memory address.
Define Indirect mode of addressing. Give an example.
3 Address field contains a memory location that holds the effective address of the 2M
operand. Example: MØV R1, (A) A contains address of operand.
Give the hierarchy of cache memory.
4. CPURegisters (fastest, smallest) 2M
Level 1(LI) Cache -Closest to CPU, very fast, small size.
Level 2 (L2) Cache - Larger, slightly slower. Level 3(L3) Cache - Shared
among cores, bigger size.
Main Memory (RAM) Secondary Storage (Disk)
Hierarchy ensures trade-off between speed, cost, and size.
Define Bus arbitration and mention its types.
5. 2M
Bus Arbitration: Process of deciding which device gets control
of the system bus when multiple devices request it.
Types: Daisy Chaining (Serial Arbitration)
Centralized
Arbitration (Controller-based)
Distributed Arbitration (Devices coordinate among themselves)
Part-B
Module-3
6. Apply steps needed to execute the machine instruction - AddLOCA Ro 10M
Memory
MAR MDR
Control
PC R
R.
IR Processor
AU
R.
D general purpose
registers
Instruction: Add contents of memory location LOCA to register RO.
Steps: 5steps: 2
|1. Fetch: PCprovides address ’ MAR ’ Memory ’ MDR ’ IR.
2. Decode: CU interpretsopcode (ADD).
B. Fetch Operand: MAR -LOCA MDR ALU.
4. Execute: ALUadds MDR + RO’ result in R0.
5. Update PC: PC increments for next instruction.
Fetch: PC ’ MAR: The Program Counter provides the address of the instruction to be
fetched. 2
Memory ’ MDR: The instruction at that address is read from memory into MDR.
MDR ’ IR: The instruction is then moved into the Instruction Register.
PCIncrement: PCis incremented to point to the next instruction.
2. Decode the Instruction
The Control Unit (CU)interprets the opcode ADD and identifies:
Operation: Addition.
Operands: Memory location LOCA and register R0. 1
Fetch Operand
MAR - LOCA: The address LOCA is placed in MAR.
Memory ’ MDR: The contents of LOCA are fetched from memory into MDR.
Operand Ready: MDR now holds the value to be added to RO.
4. Execute
ALUOperation: ALUperforms R0+ MDR.
Result ’ R0: The sum is stored back into register R0.
5. Update PC
PC already incremented during fetch; ready for next instruction.
1
7 Examine the various generic addressing modes with examples. 10
Immediate Addressing
2
Def: The operand is specified directly in the instruction.
Example:
MOV R1, #5; Move the value 5 into register RI
Operand in instruction (e.g., MOV RI, #5).
Use: Fast because no memory access is needed.
Direct Addressing 1
Def:The instruction contains the memory address of the operand.
Example:
MOV RI. A:Move the contents of memory location A into RI
Use :Simple, but requires memory access Address given (e.g., MOV RI, A).
Indirect Addressing
address 01 the
Det: Ihe instruction specifies a memory location that contains the
operand.
Example:
intoKI
MOV Rl, (A); Move the contents of the memorv location pointed by A
Use: Useful for dynamic data structures like linked lists.
Address points to another address (e.g.. MOVR1, (A).
Register Addressing
Def:The operand is in a register.
Example:
ADD RI, R2: Add contents of R2 to RI
Use :Very fast because it avoids memory access.
Operand in register (e.g.. ADDRI, R2).
Indexed Addressing
Def:The effective address is calculated as Base Address + Index Register.
Example:
MOV R, A(R2); Move contents of memory at address (A+ R2) into RI
Use: Common in arrays and tables.
Indexed: Base + index (e.g., MOV R1, A(R2). 2
Relative Addressing
Def: The effective address is Program Counter (PC) + Offset.
Example: PC
BRANCH +10; Branch to the instruction 10 locations ahead of current
Use: Used in control flow instructions like loops and jumps.
Relative: PC + offset (e.g., BRANCH +10)
instructions 10M
For Thegiven expression (A+B)*(C+D)construct assembly
A)Three-address instruction
B)Two- address instruction
C) One- address instruction
Three-Address Instructions
operand.
Each instruction can have two source operands and one destination
D
Example:
ADD R1, A, B; R1 A+B
ADDR2, C. D: R2 -C+D
MUL R3, R1, R2: R3 - RI x R2
result.
RIstores (A+B), R2 stores (C+D), and R3 stores the final
3
Two-Address Instructions
Each instruction uses one destination operand that is also a source operand.
DExample:
MOV RI1, A: RI +A
ADD R1, B: RI RI + B
MOV R2,C: R2 +-C
ADD R2, D: R2 +- R2 + D
MUL R1, R2 :R1 RI x R2
RI accumulates (A+B), R2 accumulates (C+D), then multiply and store in R1.
One-Address Instructions 4
Uses an implicit acecumulator (AC) for operations.
Example:
LOAD A: AC +- A
ADD B: AC+ AC+B;
STORE TEMP: TEMP AC:
LOAD C: AC -C
ADD D; AC +- AC+D;
MUL TEMP: AC AC* TEMP
STORE RESULT: RESULT AC
Temporary storage is needed because the accumulator can hold only one
value at a time
Module-4
9. Illustrate the three different typesof mapping functions with neat 10M
(Any one example for each mapping technique)
diagram
The different ways by which blocks from the
main memory are mapped into cache
There are three main mapping techniques which memory.
1. Direct-mapping technique decide the cache organization:
2. Associative mapping technique
B. Set associative mapping technique
we use a specific small example: A cache
total of 2048 (2K) words, and assuming thatconsisting of 128 blocks of 16 words each, for a
address. the main memory is addressable by a 16-bit
Direct Mapping Technique:
D The main memory has 64K words,
and the consecutive addresses which will be viewed as 4K blocks of 16 3
refer to consecutive words. words each,
D The cache systems are divided
shown in the figure: into three categories to implement the
cache system. As
The lower-order 4 bits from 16
words in a
The second field is known as the block block constitute a word field.
lts length is 7 bits. When a new field, used todistinguish a block from other
block enters the cache, the 7-bit cache blocks.
determines the cache position in which this block block field
The third field is a Tag field, used to store must be stored.
block and to identify which of the 32 higher-order 5 bits of the memory address of the
blocks are mapped into the cache
Tag Block Word
4
Figure 8:Main Memory Address
It is the simplest mapping technique, in
which each block from the main memory has only
one possible location in the cache organization.
For example, the block iof the main memory
Therefore, whenever one of themain memory maps onto block i mod 128 of the cache.
blocks 0, 128, 256, ... is loaded in the cache,
it is stored in block 0.
Block 1. 129, 257, ... are stored in block l of the
cache and so on.
B c 127
BKA 57
Associative Mapping Technique 3
The figure shows the associative mapping, where a main
into any cache block position. In this case, 12 tag bits arememory block can be placed
required to identify a memory
block when it is resident in the cache.
rhe tag bits of an address received irom the processor are compared to the tag bits of
each
block of the cache to see if the desired
block is present.
This is called associative mapping technigue. It gives complete freedom in
cache location in which to place the memory choosing the
block.
Set-Associative Mapping:
OIt is a combination of the direct and associative-mapping techniques. Blocksof the cache
are grouped into sets, and the mapping allows a block of main memory to reside in any
block of the specific set.
In this case, memory blocks 0, 64, 128. ..., 4032 are mapped into cache set 0, and they can
occupy either of thetwo block positions within this set.
The cache might contain the desired block. The tag field of the address must then be
associatively compared to the tags of the two blocks of the set to check if the desired
block is present. This two-way associative search is simple to implement.
aireGry
BlockO
SIOKe 1
Set 0
|Tag
Slock3
Set 1 Block 65
Line 3
Block 4095
Tag Line126
Set 63
[Tag Line 127
Biock 16383
Main-memorv address
Set Word
Tag
Summarize the sequence of events involved in handling an interrupt request
from a single 10M
10.
device.
Interrupt Request Raised
indicating it needs attention.
The device sends an interrupt signal to the CPU
Interrupt Acknowledgement
CPUacknowledgesthe interrupt and suspends the current execution.
Saving Current State 2
critical states to
The CPU saves the contents of registers, program counter, and other
preserve the interrupted program.
Identify Interrupt Source
The interrupt controller or CPUdetermines which device generated the interrupt.
Transfer toInterrupt Service Routine (ISR) of the ISR.
CPUloads the address of the ISR from the interrupt vector table and begins execution
Execution of ISR
The ISR performs the required service for the device (e.g., data transfer, error handling).
Restoring Saved State
After ISR execution, the CPUrestores the previously saved registers and program counter
Resume Normal Execution 1
CPUresumes the interrupted program from the point it was paused.
lnterrupts Example
Program "rogTam2
COMPUTE Routine DISPLAY Ruutin
Fig: Transfer of control
through the use of interrupts
(OR)
INTX1
INTRp
Device
Dovice 2 Devico p
INTA
11 Priority
ircuit arbilration
Demonstrate the approaches involved in
multiple devices. (ANY 5 METHODS) handling simultaneous interrupt requests fromoM
[Link] After Interrupt:
f the processor uses a polling
mechanism to poll the status registers of I/O
determine which device is requesting 2
an interrupt. devices to
|In thiscase the priority is
The first device with statusdetermined by the order in which
bit set to lis the device whose the devices are polled.
2. Vectored Interrupts interrupt request is accepted.
Each device has a unique interrupt
vector (address of its ISR).
CPU directly jumps to the correct ISR 2
Advantage: Fast response, less overhead. without extra identification steps.
Disadvantage: Requires hardware support.
Example: Modern microcontrollers use vectored interrupts.
3. Priority Interrupts
Devices are assigned priorities.
If multiple interrupts occur, the highest
priority device is serviced first.
Advantage: Critical devices (e.g., emergency
Disadvantage: alarms) get immediate attention.
Low-priority devices may suffer delays.
Example: Disk I/O prioritized over keyboard input.
4. Simultaneous Requests: 2
Let us now consider the problem of
more devices. simultaneous arrivals of interrupt requests from two or
The processor must have some means of
priority scheme such as that of figure, deciding which requests to service first. Using a
the solution is straight forward.
0The processor simply accepts the
requests having the highest priority. Polling the status
registers of the I/O devices is the simplest
OIn this case, priority is determined by thesuch mechanism.
order in which the devices are polled. When
vectored interrupts are used, we mustensure that only one device is selected to send its
interrupt vector code.
O The interrupt-request line INTR is
common to all devices.
5. Daisy-Chaining (Hardware Priority)
Devices are connected in a chain; the
The first device in the chain with a CPUchecks them in order.
request gets serviced.
Advantage: Simple hardware
Disadvantage: Devices fartherimplementation.
down the
Example: Early microprocessor [Link] may face longer delays.
Hoad of the Dept.
ISE
SIGNATURE OF FACULTÝ
HOD:ngicre-¬7