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DigitalDesign Assignment

The document outlines a lab assignment for CSET 105 focusing on digital design, including the creation of truth tables, Boolean expressions, and Verilog code for fundamental gates such as NOT, OR, and AND. It explains the significance of keywords like input, output, reg, and wire in Verilog, along with example code and testbenches for each gate. The assignment emphasizes practical implementation and verification of digital logic through coding.

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22 views6 pages

DigitalDesign Assignment

The document outlines a lab assignment for CSET 105 focusing on digital design, including the creation of truth tables, Boolean expressions, and Verilog code for fundamental gates such as NOT, OR, and AND. It explains the significance of keywords like input, output, reg, and wire in Verilog, along with example code and testbenches for each gate. The assignment emphasizes practical implementation and verification of digital logic through coding.

Uploaded by

shoryas936
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Digital Design

CSET 105
Lab Assignment 01_Set -4

Q1. Draw the Symbol along with their truth tables and Boolean expressions of
fundamental building gates used for digital design.

Ans.

i) Not Gate A ~A
A ~A

0 1

1 0

A B A || B
i) Or Gate A
B A || B 0 0 0

1 0 1

0 1 1

1 1 1

A B A&B
i) And Gate A A&B 0 0 0
B
1 0 0

0 1 0

1 1 1

Q2. Write the importance of the keywords input, output, input, reg and wire used in
Verilog along with its syntax declaration.

Ans.

Input Keyword specifies which variable will store the input and output keyword works similarly .
reg keyword is mostly used in testbench codes and it declares which variable will pass the test
values to the logic code . wire keyword is used for the variable which passes the output and it has
no size or memory.

Example :

Method orgate(input a , input b , output y)

{In Test Bench code}:


reg a , b
wire y
Q3. Write a Verilog code to implement NOT gate. Write the corresponding Testbench code for the
verification of your Verilog code.

Ans.

3_Verilog

module notgate(input a, output b);


assign b=~a;
endmodule

3_Testbench

module hiinot;
reg n;
wire o;
notgate uut(.a(n), .b(o));

initial begin
n=1;
#2;
n=0;
#2;
end
initial begin
$dumpfile("[Link]");
$dumpvars(0,hiinot);
end
endmodule

3_Gtkwave
.
Q4. Write a Verilog code to implement the Boolean Expression Y = A B. Write the corresponding
Testbench code for the verification of your Verilog code. Identify the gate that matches to this
Operation.

Ans.

4_Verilog

module orgate(input a, input b , output c)


assign c=a||b;
endmodule

4_Testbench
module hiior;
reg n , m;
wire o;
orgate uut(.a(n), .b(m), .c(o))
initial begin
n=0
m=0
#2;
n=0
m=1
#2;
n=1
m=0
#2;
n=1
m=1
#2;
$finish();
end
initial begin
$dumpfile("[Link]");
$dumpvars(0,hiior);
end
endmodule
4_Gtkwave

Q5. AND GATE

Ans-

5_Verilog

module ANDGate(input a, input b, output out);


assign out = a & b;
endmodule

5_Testbench

module tb_AND_gate;
reg a,b;
wire=out;
ANDGate uut(.a(a), .b(b), .out(out));

initial begin
$dumpfile("[Link]");
$dumpvars(1);
end
initial begin
$monitor("At time %0t: a=%b b=%b, mul=%b", $time, a, b,
out);
end
initial begin
$monitor("a=%b, b=%b, out=%b", a, b, out);
a=0; b=0;
#2
a=0;b=1;
#2
a==1;b=0;
#2
a=1;b=1;
#2
$finish();
end
endmodule

5_GTKWave

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