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Lecture #06, Microprocessor

The document provides an overview of memory segmentation in the 8086 microprocessor, detailing the base and offset addresses, along with the advantages of segmentation. It also explains the logical and physical address concepts, memory organization, and various addressing modes used in 8086 instructions. Additionally, it covers byte and word transfer methods, highlighting how data is accessed and transferred within the memory architecture.

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4 views8 pages

Lecture #06, Microprocessor

The document provides an overview of memory segmentation in the 8086 microprocessor, detailing the base and offset addresses, along with the advantages of segmentation. It also explains the logical and physical address concepts, memory organization, and various addressing modes used in 8086 instructions. Additionally, it covers byte and word transfer methods, highlighting how data is accessed and transferred within the memory architecture.

Uploaded by

shafahid666
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© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CSE-3103: Microprocessor and Microcontroller

Dept. of Computer Science and Engineering


University of Dhaka

Prof. Sazzad M.S. Imran, PhD


Dept. of Electrical and Electronic Engineering
[Link]
Memory Segmentation of 8086
Base address of segment 
= segment address × 10H,
segment starting address.
00000H, 00010H or 00020H, etc.

Offset address range = 0000H to FFFFH [216 = 64 kB]

Advantages of memory segmentation 


address bus = 20 bits,
segmentation allows to work with 16-bit registers.

> 1 code, data, extra, stack segment can be used.


code, data, stack, extra segment > 64 kB long.

time-shared multitasking environment 


moves over from one user’s program to another =
CPU reload four segment registers.

user’s program (code) and data can be stored separately.


Logical Address, Base Segment
Address and Physical Address
Segment address 
16-bit, reside in segment registers (CS, DS, ES, SS).

Base address 
20-bit, Segment address × 10H

Offset address 
= Effective address,
16-bit, reside in IP, BP, SP, BX, SI, DI.

Logical address 
Segment : Offset = DS : 1234H

Physical address 
= Real address,
= Segment address × 10H + Offset address
Memory Organization
Memory Organization

BHE A0 Word/byte access


0 0 Both banks active
0 1 Only high bank active
1 0 Only low bank active
1 1 No bank active
Byte and Word Transfer by 8086
(a) even-addressed byte transfer, BHE A0 Word/byte access
(b) odd-addressed byte transfer, 0 0 Both banks active
(c) even-addressed word transfer,
0 1 Only high bank active
(d) odd-addressed word transfer.
1 0 Only low bank active
1 1 No bank active
Byte and Word Transfer by 8086
BHE A0 Word/byte access
0 0 Both banks active
0 1 Only high bank active
1 0 Only low bank active
1 1 No bank active
Addressing Modes
Instruction = opcode + operand.
Operand may reside in
(i) accumulator or
(ii) general purpose register or
(ii) memory location.

Addressing mode = manner in which operand is specified in instruction.


Different addressing modes of 8086 
(i) Immediate operand addressing.
(ii) Register operand addressing.
(iii) Memory operand addressing.

Different memory addressing modes 


(i) Direct Addressing,
(ii) Register Indirect Addressing,
(iii) Based Addressing,
(iv) Indexed Addressing,
(v) Based Indexed Addressing,
(vi) Relative Based Indexed Addressing.

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