EXPERIMENT NO 1
Aim: -To Design &Verify Operation of Half Adder &Full Adder.
APPARATUS REQUIRED: Power supply, IC’s, Digital Trainer, Connecting leads.
BRIEF THEORY: We are familiar with ALU, which performs all arithmetic and logic
operation but ALU doesn’t perform/ process decimal no’s. They process binary no’s.
Half Adder: It is a logic circuit that adds two bits. It produces the O/P, sum & carry. The
Boolean equation for sum & carry are:
SUM = A + B CARRY = A. B
Therefore, sum produces 1 when A&B are different and carry is 1when A&B are 1. Application
of Half adder is limited.
Full Adder: It is a logic circuit that can add three bits. It produces two O/P sum & carry. The
Boolean Equation for sum & carry are:
SUM = A + B + C CARRY = A.B + (A+B) C
Therefore, sum produces one when I/P is containing odd no’s of one & carry is one when there
are two or more one in I/P.
LOGIC DIAGRAM
PROCEDURE
(a) Connect the circuit. as shown in fig. For half adder.
(b) Apply diff. Combination of inputs to the I/ P terminal.
(c) Note O/P for Half adder.
(d) Repeat procedure for Full wave.
(e) The result should be in accordance with truth table.
OBSERVATION TABLE:
FULL ADDER
INPUTS OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
FULL ADDER
INPUTS OUTPUTS
A B C S CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RESULT: The Half Adder & Full Adder ckts are verified.
PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
The Vcc and ground should be applied carefully at the specified pin only
EXPERIMENT NO2
OBJECT Implementing Binary to Gray and Gray to Binary conversion
APPARATUS REQUIRED Bread board, Logic trainer kit IC7486 and connecting wire
THEORY
BINARY CODE
Binary code represents text, computer processor instructions, or any other data using a two-symbol
system. The two-symbol system used is often "0" and "1" from the binary number system. The binary
code assigns a pattern of binary digits, also known as bits, to each character, instruction, etc. For
example, a binary string of eight bits can represent any of 256 possible values and can, therefore,
represent a wide variety of different items.
GRAY CODE
The reflected binary code (RBC), also known just as reflected binary (RB) or Gray
code after Frank Gray, is an ordering of the binary numeral system such that two successive values
differ in only one bit (binary digit).
For example, the representation of the decimal value "1" in binary would normally be " 001" and "2"
would be "010". In Gray code, these values are represented as "001" and "011". That way,
incrementing a value from 1 to 2 requires only one bit to change, instead of two.
Gray codes are widely used to prevent spurious output from electromechanical switches and to
facilitate error correction in digital communications such as digital terrestrial television and
some cable TV systems.
LOGIC DIAGRAM
PROCEDURE
(1) Make the connection as per circuit diagram
(2) Ground and Vcc must be at proper pins
TRUTH TABLE
RESULT
Implemented and studied the binary to gray and gray to binary conversion
PRECAUTION
(1) Connection must be properly done
(2) Supply must be given after connection
(3) IC must be properly installed
EXPERIMENT NO 3
OBJECT Implementation of 3-8 line DECODER
APPARATUS REQUIRED
(1) Digital trainer kit
(2) Bread board
(3) IC 74139 OR 74138
(4) Connecting leads
THEORY
DECODER: A decoder is a device which does the reverse operation of an encoder, undoing
the encoding so that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode. It is a combinational circuit that converts binary
n
information from n input lines to a maximum of 2 unique output lines. In digital electronics, a
decoder can take the form of a multiple- input, multiple-output logic circuit that converts coded
n
inputs into coded outputs, where the input and output codes are different. e.g. n-to-2 , binary-
coded decimal decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs assume a single
"disabled" output code word. In case of decoding all combinations of three bits eight
3
(2 =8)decoding gates are required. This type of decoder is called 3-8decoders because 3 inputs
and 8 outputs. For any input combination decoder outputs are 1.
LOGIC DIAGRAM
TRUTH TABLE
PROCEDURE:
1) Connect the circuit as shown infigure.
2) Apply Vcc& ground signal to everyIC.
3) Observe the input & output according to the truthtable
RESULT: Encoder/ decoder and demultiplexer have been studied and verified .
PRECAUTIONS:
1) Make the connections according to the IC pindiagram.
2) The connections should betight.
3) The Vcc and ground should be applied carefully at the specified pinonly.
EXPERIMENT NO 4(A)
AIM:IMPLEMENTATION OF 4X1 MULTIPLEXER USING LOGIC GATES.
APPARATUS REQUIRED:Power Supply, Digital Trainer, Connecting Leads, IC’s 74153(4x1
multiplexer )
BRIEF THEORY:
MULTIPLEXER:
Multiplexer generally means many into one. A multiplexer is a circuit with
[Link]
The fig.(1) Shows the general idea . The ckt. has n-input signal, control signal & one output signal .
Where 2n = m . One of the popular multiplexer is the 16 to 1 multiplexer, which has 16 input bits, 4
control bits & 1 output bit.
CIRCUIT DIAGRAM:
LOGIC DIAGRAM
PROCEDURE
1. Fix the IC's on the bread board &give the input supply.
2. Make connection according to the circuit.
3. Give select signal and strobe signal at respective pins.
4. Connect +5 v Vcc supply at pin no 24 & GND at pin no12
Verify the truth table for various inputs.
RESULT: Verify the truth table of multiplexer for various inputs.
PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.
EXPERIMENT NO 4(B)
OBJECT: IMPLEMENTATION OF 8X1 MULTIPLEXER USING LOGIC GATES.
APPARATUS REQUIRED: Power Supply, Digital Trainer, Connecting Leads, IC 74151
THEORY
We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output.
Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs.
LOGIC DIAGRAM
TRUTH TABLE
BLOCK DIAGRAM
IC 74151 PIN DIAGRAM
PROCEDURE
(1)Fix the IC's on the bread board &give the input supply.
(2)Make connection according to the circuit.
(3)Give select signal and strobe signal at respective pins.
(4)Connect +5 v Vcc supply at pin no 24 & GND at pin no12
(5)Verify the truth table for various inputs
RESULT Implemented and studied 8x1 mux using IC 74151
PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.
EXPERIMENT NO 6
OBJECT To verify the excitation table of various FLIP FLOPS (RS, D, JK, T)
APPARATUS REQUIRED: IC’ S 7400, 7402 Digital Trainer & Connecting leads.
BRIEF THEORY:
● RS FLIP-FLOP:
There are two inputs to the flip-flop defined as R and S. When I/Ps R = 0 and S = 0 then O/P remains unchanged.
. I/Ps R = 0 and S = 1 the flip-flop is switches to the stable state where O/P is 1 i.e. SET.
The I/P condition is R = 1 and S = 0 the flip-flop is switched to the stable state where O/P is 0 i.e. RESET.
The I/P condition is R = 1 and S = 1 the flip-flop is switched to the stable state where O/P is forbidden.
● JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal element to use. The variable
and K are called control I/Ps because they determine what the flip- flop does when a positive edge
arrives. When J and K are both 0s, both AND gates are disabled and Q retains its last value.
● D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching the Q output until
a clock pulse occur. When the clock is low, both AND gates are disabled D canchange value without
affecting the value of Q. On the other hand, when the clock is high, both AND gates are enabled.
In this case, Q is forced to equal the value of D. When the clock again goes low, Q retains or stores
the last value of D. a D flip flop is a bistable circuit whose D input is transferred to the output
after a clock pulse isreceived.
● T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock edge, giving an output
which is half the frequency of the signal to the T input. It is useful for constructing binary counters,
frequency dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying
both of its inputshigh.
LOGIC DIAGRAM
RS FLIP FLOP
D FLIP FLOP
JK FLIP FLOP
T FLIP FLOP
PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.
OBSERVATION TABLE:
SR FLIP FLOP:
CLOC S R Q
K
n
+
1
1 0 0 N
O
C
H
A
N
G
E
1 0 1 0
1 1 0 1
1 1 1 ?
D FLIPFLOP:
INPUT OUTPUT
0 0
1 1
JK FLIPFLOP
CLO S R Q
CK n+1
1 0 0 NO
CHAN
GE
1 0 1 0
1 1 0 1
1 1 1 Qn’
T FLIPFLOP
CLO S R Q
CK n+
1
1 0 1 NO
CH
AN
GE
1 0 Qn’
RESULT: Truth table is verified on digital trainer.
PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.
EXPERIMENT NO 7
OBJECT To study an 8 bit ARITHMETIC LOGIC UNIT Using IC 74181
APPARATUS REQUIRED ALU Trainer kit ,connecting leads
THEORY
The 8-bit ALU was formed by combining three 4-bit ALU's with 5 multiplexers as shown in Figure 2.
The design of the 8-bit ALU is based on the use of a carry select line. The four lowest bits of the input are
fed into one of the 4 bit ALU's.
BLOCK DIAGRAM
The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S 1 and S0 the
circuit operates as follows:
for Control signal S1 = 0 , S0 = 0, the output is A And B,
for Control signal S1 = 0 , S0 = 1, the output is A Or B,
for Control signal S1 = 1 , S0 = 0, the output is A Xor B,
for Control signal S1 = 1 , S0 = 1, the output is A Add B.
TRUTH TABLE
MODE SELECT FN FOR ACTIVE HIGH OPERANDS
ARITHMETIC (NOTE
INPUTS LOGIC 2)
S3 S2 S1 S0 (M = H) (M = L) (Cn=L)
L L L L A' A
L L L H A'+B' A+B
L L H L A'B A+B'
L L H H Logic 0 minus 1
L H L L (AB)' A plus AB'
L H L H B' (A + B) plus AB'
L H H L A⊕B A minus B minus 1
L H H H AB' AB minus 1
H L L L A'+B A plus AB
H L L H (A ⊕ A plus B
B)'
H L H L B (A + B') plus AB
H L H H AB AB minus 1
H H L L Logic 1 A plus A (Note 1)
H H L H A+B' (A + B) plus A
H H H L A+B (A + B') plus A
H H H H A A minus 1
Required functionality of ALU (inputs and outputs are active high)
The L denotes the logic low and H denotes logic high.
RESULTStudied the ALU using ic 74181
PRECAUTION
(1) Connection must be proper
(2)Observation must be taken carefully