Original Paper

Measurement and Control

2019, Vol. 52(7-8) 995–1001
Low-power design-for-test Ó The Author(s) 2019
Article reuse guidelines:
implementation on phase-locked [Link]/journals-permissions
DOI: 10.1177/0020294019858089

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Avinash Yadlapati and Hari Kishore Kakarla

Abstract
Low-power design for test is the need of the hour for any system-on-chip designer. The low-power design techniques
have been a major challenge to both the designer as well as the testing engineer. With so many advancements in low-
power technology in the phase of register transfer logic design, functional verification, register transfer logic and physical
synthesis and physical design. Design for test is not an exception to this. The low-power design-for-test techniques can
be applied at various levels of the design-for-test flow as in the scan insertion stage, automatic test pattern generation
simulations stage, testing stage, and so on. Some of the reasons for the high-power utilization in the design-for-test phase
can be due to the external circuitry being inserted during the design phase and not used in the functional mode. The
complete circuit will be active in the test mode only. In this paper, the focus will be primarily on reducing the power dur-
ing the automatic test pattern generation scan synthesis phase. All the scan flops are connected by a common scan clock
with a fixed frequency. The intention of this study is to divide the clock frequency by half and make sure that the power
is reduced without affecting any timing violations. Since the scan clock frequency is low, it can be further divided to
ensure that power is reduced without affecting the testing process of the chip.

Keywords
Design for test, low power, unified power format, common power format, scan, clock gating circuitry, automatic test
pattern generation, synthesis, phase-locked loop, asynchronous first-in first-out

Date received: 28 July 2018; accepted: 2 May 2019

Introduction (d) Inadequate battery life for portable applications.

As the technology is shrinking, more and more power

Hence, it becomes important that the power is saved
challenges are on the rise. Handling the power issues in
in parts of the chip that are not used always.3,4 All the
the lower technology nodes has become more complex
SoCs integrate multiple intellectual properties (IPs).
and challenging for the application-specific integrated
Every IP has got its own power requirements and speci-
circuit (ASIC) designers. Complex systems on chip
fications. When multiple IPs are integrated in a single
(SoCs) require huge data to test them, thereby increas-
SoC, there is every chance that the total power of the
ing the time for testing and the tester memory. Low-
chip might shoot up. This will lead to overall failure of
power design techniques are needed both at the func-
the power management system of the chip. To over-
tional mode as well as at the test mode of the design.1,2
come such problems related to power saving, each of
As the complexity of the integrated circuits (ICs) and
the IPs can be moved among the power modes like
the feature size continues to reduce, the power con-
power-off, power-on, or sleep. Every IP on SoC can be
sumption becomes one of the key issues not only at the
divided as power domains and these domains can be
functional level but also at the manufacturing level.
turned on and off in accordance with the power
The functional operation with higher power consump-
mode.5–7
tion implies the following:

(a) High design cost and high manufacturing cost; Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur
(b) High system cost because of the requirements of
packaging and cooling; Corresponding author:
Avinash Yadlapati, Koneru Lakshmaiah Education Foundation,
(c) Short device life cycle in addition to less device Vaddeswaram 522502, Guntur, India.
reliability; Email: avinashyadlapati15@[Link]

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996 Measurement and Control 52(7-8)

Figure 1. DFT flow diagram.

Low-power design for test (DFT) has always been a timing violations is considered in this approach. In this
challenge to the DFT engineers. One reason is that a lot novel approach, the authors have implemented the low-
of additional circuitry is added during the test phase power DFT technique during the scan synthesis phase
and one has to ensure that the switching activities dur- using the clock reduction technique with minimum tim-
ing this phase are under control. This phase primarily ing violations. During the ATPG phase, there are tech-
has two aspects: (1) scan synthesis and (2) automatic niques to minimize the power using unified power
test pattern generation (ATPG) simulations phase. format/common power format (UPF/CPF) flows.
Most of the techniques that are applied to reduce power However, the idea to minimize power at the scan design
in the DFT phase are as follows: phase is a novelty in this paper.

(a) Clock gating the scan cell;

(b) Special clustering and ordering of the scan cells
DFT flow diagram
improves the effectiveness of power reduction tech- A typical ASIC design flow till the DFT phase is as
niques based on test planning and test generation; shown in Figure 1.
(c) Partitioning techniques are used to reduce the power. From the ASIC design flow in Figure 1, the DFT
phase starts after the completion of synthesis and gener-
This idea of dividing the scan clock is novel because ation of the synthesized netlist.8–10 As it is evident from
the scan clock is used only to test the test mode of the the flow diagram, the low-power DFT technique can be
chip and not the functional mode. Usually, the scan clock applied in two phases of the DFT flow:
has a much lower frequency than the functional clock.
However, the scan clock is not always on which enables 1. Scan synthesis phase;
the clock gating technique to effectively shut down the 2. ATPG simulations phase.
scan clock when it is not in use. In this approach,
the authors have used the method of clock reduction
(decreasing the scan clock frequency by half) within the
Scan synthesis phase
permissible range of the specifications for achieving the As shown in Figure 2, during the scan synthesis phase,
low power in the circuit. The main advantage of reducing the following steps take place:
the scan clock frequency compared to the other methods
of low power is that the power is reduced to half (power (a) Scan configuration;
is directly proportional to frequency) and also fixing the (b) Scan replacement;
Yadlapati and Kakarla 997

and Magma. There is very subtle difference between

the two flows. Most of the companies follow both the
flows. Either of these flows is used to reduce power
consumption at various levels of the ASIC design
flow.12

Low-power DFT techniques

Some of the commonly used low-power techniques in
DFT are as follows. All the below-mentioned tech-
niques are already implemented in the DFT domain.
The clock reduction method is novel as it is done at the
scan synthesis phase and the timing violations arising
due to this clock reduction are also considered to be
fixed. The power is reduced by nearly 50% and no func-
tionality or performance of the chip is affected.

Clock gating circuitry

It is a technique used for the reduction of power con-
sumption in the power-on domain by blocking the
clock dynamically before reaching a set of flip-flops or
latches. It is like switching off the clock when it is not
being used functionally. Since continuous switching
consumes a lot of dynamic power, this technique helps
save power when the clock is not being used.13

Figure 2. Scan synthesis flow chart.

Power domains
Separating the whole design into different power
(c) Scan reordering; domains will ensure that each of the blocks can be
(d) Scan stitching. powered down or powered up individually by control-
ling the power switches utilized for gating the power
During the ATPG simulations phase, the following supply connection to every power domain block.14
steps take place:

(a) Read synthesis netlist from design; Low-power cell

(b) Read ATPG library files, test procedure files, and While testing the design, the capacity of the state pre-
do files; servation registers to keep hold of their state needs to
(c) Build the ATPG model; be verified when the power domain is powered off.
(d) ATPG DRC checking; Isolation cells are located at the limit of two power
(e) Generate fault list; domains keeping in mind to isolate the power-on and
(f) Generate test vectors; power-off domains.
(g) Validate test patterns using simulations.
Multiple supply voltages
Low-power specification formats Based upon the operating conditions, different power
The two common formats used in the industry for domain blocks are subject to different supply voltages
power savings are as follows: and each power domain block is connected to other
power domain block with the help of level shifters.
1. UPF;
2. CPF.
Power-aware DFT
While UPF design flow is implemented with the help Once the scan synthesis starts, the functional flops are
of Synopsys electronic design automation tools and replaced by their scan equivalent flops. During the scan
tested on Synopsys generic 90 nm and 32/28 nm stitching process, the power-aware DFT is applied by
libraries, CPF design flow was designed by Cadence the respective power domain after the partitioning of
Design Systems and then contributed to Si2. UPF has scan chains under the condition that there are adequate
been driven mainly by Synopsys, Mentor Graphics, scan I/Os in every power domain and they can have
998 Measurement and Control 52(7-8)

scan clock in such a way that it meets the design specifi-

cation and also directly resulted in reducing the power
consumption in the circuit.
The input design is a phase-locked loop (PLL) with
multiple clocks. A simple PLL design looks as shown in
Figure 3.
PLL is a circuit that can be used for high-frequency
application and very short interlocking time. PLL is a
feedback system that detects the phase error and then
adjusts the phase of the output. The phase error detec-
tor detects phase error between the output and the
input through the feedback system. The digital con-
Figure 3. PLL block diagram. trolled oscillator (DCO) adjusts the phase difference.
One of the primary applications of PLL is in carrier
synchronization and bit synchronization systems to
their dedicated scan I/Os, control signals, and test improve their synchronization properties. Another
clocks. This guarantees that every power domain is important application of PLL is its use as a frequency
having dedicated scan chains which are active in the synthesizer. Digital phase-locked loop (DPLL) can be
power domain that is ON.15,16 classified into two major categories: (1) uniform sam-
pling DPLLs and (2) non-uniform sampling DPLLs.
The gate-level netlist is taken as the input for per-
Power switches forming the DFT process and implementing the low-
In order to minimize power dissipation, particularly power DFT technique of decreasing the scan clock fre-
leakage power dissipation caused by the shrinking quency and dividing it into multiple power domains.
power technologies, power switches are generally Here the emphasis is on reducing the dynamic power.
employed in modern low-power design circuits. One or The general representation of CMOS (complemen-
tary metal-oxide semiconductor) logic gate for switch-
ing power calculation is shown in Figure 4
2T 3
ð2   ðT  
16 dVout dVout 7
Pavg = 4 Vout Cout dt + ðVDD  Vout Þ Cload dt5 ð1Þ
T dt dt
0 T
2

The average power consumption can be expressed as

1
Pavg = Cload V2DD = Cload V2DD fCLK ð2Þ
more power switches are equipped at different parts of T
the design to facilitate the functionality of power The transition rate of the nodes can be slower than
gating. the clock rate. For better representation of this beha-
vior, a node transition factor (a#) must be introduced

Implementation of the low-power DFT Pavg = aT Cload V2DD fCLK ð3Þ

technique
The generalized expression for the average power
In the current implementation in this paper, for the dissipation can be rewritten as
low-power DFT, we have adjusted the frequency of the

Figure 4. CMOS logic circuit for power calculation.

Yadlapati and Kakarla 999

Table 1. Comparison table showing the power values before and after applying LPT for PLL..

Parameter Before applying the low-power technique After applying the low-power technique

Global operating voltage 0.95 0.95

Power-specific unit information
Voltage units 1V 1V
Capacitance units 1.000000 ff 1.000000 ff
Time units 1 ns 1 ns
Dynamic power units 1 uW (derived from V, C, T units) 1 uW (derived from V, C, T units)
Leakage power units 1 pW 1 pW
Cell internal power 1.0212 mW (87%) 510.5775 uW (87%)
Net switching power 154.7289 uW (13%) 77.3645 uW (13%)
Total dynamic power 1.1759 mW (100%) 587.9420 uW (100%)

Table 2. Comparison table showing the power values before and after applying the low-power technique for asynchronous FIFO.

Parameter Before applying the low-power technique After applying the low-power technique

Global operating voltage 0.95 0.95

Power-specific unit information
Voltage units 1V 1V
Capacitance units 1.000000 ff 1.000000 ff
Time units 1 ns 1 ns
Dynamic power units 1 uW (derived from V, C, T units) 1 uW (derived from V, C, T units)
Leakage power units 1 pW 1 pW
Cell internal power 13.1903 uW (96%) 6.5952 uW (96%)
Net switching power 559.9319 nW (4%) 279.9659 nW (4%)
Total dynamic power 13.7503 uW (100%) 6.8751 uW (100%)

!
X
#ofnodes Cell internal power is the power dissipated within
Pavg = aTi Cl V VDD FCLK ð4Þ the boundary of a cell. During switching, a circuit dissi-
i=0
pates the internal power by charging or discharging of
As we can see from equation (4), power is directly any existing capacitances internal to the cell.
proportional to the clock frequency. Hence, reducing Net switching power occurs when signals which go
the clock frequency such that it falls between the specifi- through the CMOS circuits change their logic state. At
cation ranges, the power can be reduced without affect- this moment, energy is drawn from the power supply to
ing the timing violations. charge up the output node capacitance.
Total dynamic power can be obtained from the fol-
lowing equation
Results of the low-power DFT technique
Ptotal = Pdynamic + Pstatic
on PLL netlist
Dynamic power : Pdynamic = Pswitching + Pshortcircuit
The results of this experiment at the scan synthesis
level after varying the clock frequency are tabulated All the above parameters have been reported by the
in Table 1. Synopsys Design Compiler using the command
As can be seen from Table 1, it is evident that the report_power.
power has reduced by approximately 50%. These Synopsys DC is a synthesis tool that takes the design
results have been obtained for the PLL design netlist. netlist as the input and reports the area, power, and so
Table 1 explains the results of the application of the on consumed by the chip. There are no simulations car-
low-power DFT technique on PLL netlist using the ried out by the authors as they are not considering the
Synopsys Design Compiler tool from Synopsys. The functionality of the PLL netlist or the asynchronous
above results have been generated with the help of the first-in first-out (FIFO) netlist used. They are only tak-
Synopsys DC tool. It is observed from Table 1 that the ing the netlist as the input and carrying out the low-
parameters like cell internal power, net switching power DFT technique research on the inputs provided
power, and total dynamic power have nearly 50% by the designer. Hence, there are no simulation reports
reduction after applying this technique. shown in the results.
1000 Measurement and Control 52(7-8)

Figure 5. PLL graphical representation of power comparison.

Figure 6. Asynchronous FIFO graphical representation of power comparison.

Results of the low-power DFT technique Conclusion

on the asynchronous FIFO design netlist As we can see from the above results on two different
The results of this experiment at the scan synthesis level design netlists, when the clock frequency is reduced
after varying the clock frequency are tabulated in Table 2. from 50 to 25 MHz, the power is also reduced by nearly
As can be seen from Table 2, it is evident that the 50%. All these results have been calibrated by ensuring
power has reduced by approximately 50% by applying that there are no setup or hold violations in the circuit
the low-power DFT technique used in this paper. These after varying the clock frequency. It is clearly proved
results have been obtained for the asynchronous FIFO from equation (3) that power is directly proportional to
design netlist. frequency. One of the techniques which will be applied
By reducing the clock frequency by half, the power in the further version of the paper will be dividing the
has also reduced by 50% which is compliant to equa- scan clock for even and odd chains and thereby reduc-
tion (2). This is the reduction technique for dynamic ing the power consumption in the scan chain.
power which is also the switching power in any SoC. Reducing the scan clock frequency does not affect
From Figures 5 and 6, we can observe the decrease either the functionality or the performance of the IC.
in power after applying the low-power technique in DFT The scan clock frequency is used only for the purpose
methodology as discussed in section ‘‘Implementation of of DFT and it is not going to be used as the functional
the low-power DFT technique.’’ clock. When the DFT mode is enabled, the scan enable
Yadlapati and Kakarla 1001

is set to logic ‘‘1’’ and no functional paths are affected. 7. Nebhrajani A. Asynchronous FIFO architectures, http://
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The author(s) declared no potential conflicts of interest with Chennai, India, 4–7 January 1998, pp. 456–463. New
respect to the research, authorship, and/or publication of this York: IEEE.
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