Worcester Polytechnic Institute
Department of Electrical and Computer Engineering
ECE 523 --- Power Electronics, DESIGN PROBLEM #1
Handed out: 09/18/2025
Due: 10/02/2025
Note:
(1) In your report, answer each TASK in sequence.
(2) First page should contain one page summary of results, placed in sequence.
(3) Collaboration is not allowed.
(4) Late work is not accepted.
INTRODUCTION
Design a wide-input range down (buck) converter, operating in continuous conduction, with the
following specifications:
Input voltage, Vg 5.5 to 40 VDC
Output voltage, Vo 5.0 V
Output load resistor, R 25
Switching frequency, fsw 500 kHz
Switch ON resistance, RON 0.2
Inductor current ripple, iL,pp < 0.4 A, p-p
Output voltage ripple, vo,pp < 40mV, p-p
Ambient temperature, TA 25C
You use the following components:
• Schottky diode 10BQ60 from International Rectifier. The diode ON voltage and diode ON
resistance are to be extrapolated from the datasheet.
• The output filter capacitor will be chosen from the Panasonic SP-Cap family. In order to ensure
safety margin, use capacitors rated at 16V. Assume that the series inductance (ESL) of the output
filter capacitor is 10 nanoHenries. Use the 100 kHz equivalent series resistance (ESR) value in
your simulation.
• Inductor LPO2506-series from Coilcraft. Select one of these surface-mount power inductors for
your design. The inductor ESR and series resonant frequency are found on the datasheet.
TASK 0: INTRODUCTION AND SUMMARY SHEET OF RESULTS
Write a brief introduction to the problem, and include a summary list of important results from Tasks 1
– 4, i.e. inductor value, capacitor value, efficiencies, duty cycles, etc.
TASK 1: SELECTION OF INDUCTOR AND CAPACITOR, IDEAL DUTY CYCLE
At first, assume ideal components (i.e., don’t consider component losses). Design a buck converter
with the constraints given above. Find the ideal D over the entire operating range and select L and C
to meet the design specifications. Use the Coilcraft inductor and Panasonic capacitor datasheets to find
1
an appropriate inductor and capacitor for this design. When you select L and C, keep in mind
component tolerances. Draw your schematic.
Also, assume that there is a “soft-start” circuit which limits inductor current during converter startup.
(You don’t need to worry about the design details of the soft-start circuit).
TASK 2: ACTUAL DUTY CYCLE WITH REAL-WORLD COMPONENTS
Next, calculate the actual duty cycle D over the entire input voltage range of 5.5V to 40V, assuming a
nonideal switch (with RDS,ON loss), inductor series resistance, and diode loss. Include in your model
the switch ON resistance, the ESR of the inductor, and the diode ON voltage and diode ON resistance1.
Apply volt-second balance to find the duty cycle D including losses. Compare the ideal duty cycle
with the real-work duty cycle. Calculate D at: Vg = 5.5, 10, 20, 30, and 40V DC and output Vo = 5.0
VDC @ 200 mA
In this task, we’ll ignore the ESR and ESL of the capacitor, since (1) it very much complicates the
analysis, and (2) the capacitor ESR has little or no effect on duty cycle anyway, since the average
capacitor current is zero.
Hint: an Excel spreadsheet works very nicely for Task 2.
TASK 3: EFFICIENCY CALCULATIONS
Calculate and plot power delivery efficiency over the input voltage range of 5.5V to 40V. Model the
attached diode appropriately as an ideal diode in series with a voltage source and resistance. Calculate
switching loss as shown in class. Assume that when the diode turns ON or OFF, the diode voltage
risetime and falltime is 25 nanoseconds; similarly, for the MOSFET, assume that the drain current
risetime and falltime is 25 nanoseconds. To get total switch losses, you need to add switch conduction
loss to the switch switching loss; the switch total power loss is given by:
Psw,total = Psw + Pcond = E sw f sw + I sw
2
, RMS RON
Make sure you model and estimate all the losses in the converter. Calculate and plot efficiency at
input voltage Vg = 5.5, 10, 20, 30, and 40V DC and output Vo = 5.0 VDC @ 200 mA.
Hint: Again an Excel spreadsheet works very nicely for Task 3. Note that ripple current, RMS values,
etc. all vary with the Vg operating point.
TASK 4: SIMULATIONS AT 500 KHZ AT VG = 5.5V, 20V AND 40V
Simulate your original design at fsw = 500 kHz using PSIM and find inductor ripple current and
capacitor ripple voltage at Vg = 5.5V, 20V and 40V focusing at first on steady-state operation after all
startup transients have died out. In your simulations, use your non-ideal duty cycle D calculated in
Task 2. Explain any discrepancies between calculated values and simulated values. In your PSIM
model, include the following parasitics:
• Switch ON resistance
• Inductor ESR (read from the datasheet)
1
Ballpark estimate an ON resistance based on the slope of the diode VI curve near your operating point.
2
• Inductor parallel capacitance (which can be estimated from the series resonant frequency)
• Capacitor ESR and 10 nH ESL
• Diode ON voltage
• Diode ON resistance
Also examine the startup transient. What’s the maximum instantaneous value of the inductor current
during startup?
PSIM HINTS
In my simulation control, I use a total time of 300 microseconds and a time step of 50 nanoseconds.
When you’re plotting output voltage ripple, set the x-axis time scale to 290s < t < 300 s, so you can
see the details of the output voltage ripple.
Here’s the front end of my buck converter.
Use a MOSFET Q1 for the switch. Double click on the MOSFET and set the ON resistance to 0.2
Ohms. Make sure the body diode of the MOSFET is in the correct direction.
3
The MOSFET is turned ON and OFF by a gating block G1. Double click on it to set the switching
frequency (500k) and the duty cycle. We set the number of switching points per cycle as 2. Duty
cycle is set by changing the second switching point. In this case, I have it set to 45 degrees, which
means D = 45/360 = 0.125. For D = 0.25, set the gating block second switching point to 90 degrees.
Comments on grading criteria for design problems
The bulk of your grade will depend on the quality of your written report. Here are some guidelines
which will help result in a quality report:
1. Format: A formal lab report is not required, but a detailed legible account of your design effort
is needed. A readable, concise presentation is required.
2. Calculations: All calculated quantities must be justified in the report. It is not necessary to re-
derive any results that were developed in class, homework, or texts, but state your intermediate
results in terms of known quantities.
3. Graphics: Schematics should be neat and accurate. Label all components with their values and
designators. Graphs should be neatly drawn, labeled and dimensioned. Asymptotes, slopes, DC
values, etc. should be indicated where appropriate.
4. Simulations: Reams of computer output are not needed or appreciated. Turn in relevant data.
Label all simulation outputs and dimension all results.
5. Justifications: The purpose of your report is to convince the reader that you understand the
theory behind your calculations, design, and simulation results. Thus, it is imperative that you
explain any discrepancies between theory and practice. Please be quantitative, and use a few
quick calculations to support your arguments.
6. Organization. Make sure your report is organized and easy to read.