ECL 1503: Fundamentals of VLSI

Design

MODULE X
Autumn / ODD Session 2025

Dr. Sushanta Bordoloi

Dept. of Electronics and Communication Engineering
National Institute of Technology Mizoram
Contents
• Design Flow
 Partitioning
 Floor Planning
 Placement

ECL 1503: Autumn / ODD Session 2025

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Design Flows
• A design flow is a set of procedures that allows designers to
progress from a specification for a chip to the final chip
implementation in an error-free way.

• Design starts at the behavioral level and then proceeds to the

structural level (gates and registers). This step is called behavioral
or Register Transfer Level (RTL) synthesis because the designs are
captured at the RTL (memory elements and logic) level in an HDL.

ECL 1503: Autumn / ODD Session 2025

• The description is then transformed to a physical description
suitable for chip fabrication. This step is called physical synthesis
(or layout generation).

• In Fig. 1, the design has been partitioned into the front end stage
at the behavioral level and the back end at the structural and
physical levels. This is important because it illustrates a
partitioning that is used to build Application Specific Integrated
Figure 1. Generalized design flow
Circuits (ASICs).

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Design Flows (contd.)
• VLSI design cycle is broadly categorized into Front End
and Back End.
 Front end (FE) starts with system specification. FE defines the
logical behavior according the functional specifications. At the
end of FE we get technology mapped gate level netlist.
 Back End (BE) starts from there and main focus of BE is to
translate the circuit we have got in FE into Silicon wafer with
proper placement of blocks , essential power lines routing and

ECL 1503: Autumn / ODD Session 2025

etc. After all these the process lead to tape out.

• Partitioning is the initial step in the Physical Design (PD)

process which divides a chip into smaller blocks.
 Different functional blocks are separated and routing and
placement is simplified. The designer breaks the larger design
into various smaller functional modules/blocks and then
proceeds with implementation of these smaller modules during
RTL design phase.
 These smaller functional blocks are structurally instantiated
or linked in the main module. Main module is called TOP

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LEVEL module. This type of partitioning is called as Logical
Partitioning. Figure 2. Physical design specification
Design Flows (contd.)
Partitioning
• Partitioning
 To simplify complex integrated circuit designs, they are divided into smaller parts called modules.
These modules can be as simple as a few electrical components or as complex as fully functional
integrated circuits (ICs).
 A tool called a partitioner splits the circuit into smaller subcircuits/ partitions/blocks. It aims to
reduce the number of connections between these partitions while adhering to design rules like
maximum size and delay limits.
 If each block is designed without considering the others, it can lead to problems. More connections

ECL 1503: Autumn / ODD Session 2025

between partitions can increase circuit delay and decrease reliability. Too many connections can
create dependencies that slow down the design process.
 The main objective is to minimize connections between sub-circuits to improve performance and meet
design constraints. Constraints may include limits on the logic size in a partition or the number of
external connections (e.g., limited by the number of I/O pins on a chip). By following these points,
designers aim to create efficient, reliable, and easily manageable integrated circuits.

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Design Flows (contd.)
Partitioning (contd.)
• Partitioning

ECL 1503: Autumn / ODD Session 2025

Figure 3. A example of Partitioning Figure 4. Level of Partitioning

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Design Flows (contd.)
Partitioning (contd.)
• Level of Partitioning
 System Level Partitioning : A system is partitioned
into group of PCBs. Each sub system can be designed as
single PCB.
 Board level partitioning : A PCB is partitioned into
sub- circuits. Each subcircuit fabricated as VLSI Chips.
 Chip Level Partitioning : Circuit assigned to the chip
is divided into manageable sub circuits.

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Figure 5. Level of Partitioning
Design Flows (contd.)
Partitioning (contd.)
• Why Partitioning is Important?
 Physical packaging : Partitioning decomposes the system in order to satisfy the physical packaging
constraints. The partitioning conforms to a physical hierarchy ranging from cabinets, cases, boards, chips,
to modular blocks.
 Divide and conquer strategy : Partitioning helps manage complex designs by breaking them into
smaller parts. This approach allows team members to work on different sections, creates a logical order
for design, converts the netlist into a physical layout for planning, assigns cells to specific areas for
placement and RLC extraction, and coordinates between logic and layout for simulation.

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 System emulation & Rapid Prototyping : One way to emulate and prototype a system is by using
FPGAs to build the hardware. Since FPGAs usually have less capacity than modern VLSI designs, these
prototype systems use a hierarchical setup of multiple FPGAs. A partitioning tool is necessary to map the
netlist onto the hardware.
 Hardware & Software Codesign : For hardware and software codesign, partitioning is used to
decompose the designs into hardware and software.
 Management of Design Reuse : For huge designs especially system-on-a-chip, we have to manage
design reuse. Partitioning can identify clusters of the netlist and construct functional modules out of the
clusters.

Figure 6. Partitioning of a System

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Design Flows (contd.)
Partitioning (contd.)
• Rules of Partitioning :
 Interconnections between Partitioning: Reducing interconnections decreases delay and interaction
between partitions, simplifying independent design and fabrication.
 Delay Due to Partitioning: Partitioning a circuit may result in the critical path crossing between
partitions multiple times.
 Number of Terminals: The number of nets needed to connect a sub-circuit to other sub-circuits does not
exceed the sub-circuit's terminal count.
 Number of Partitions : A large number of partitions can simplify the design of individual sections, but

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it may also increase fabrication costs and the number of interconnections between partitions.
 Area of each Partition

Figure 7. Partitioning of a System 9

Design Flows (contd.)
Partitioning (contd.)
• Graph Theory & Partitioning : Graphs are used in physical design algorithms to describe and
represent layout topologies.

• A graph G(V,E) is made up of two sets :

 Elements : Set of nodes or vertices denoted as V
 Edges : relations between the elements, denoted as E.

• A hypergraph consists of nodes and hyperedges. In a hypergraph, edges are sets of any number

ECL 1503: Autumn / ODD Session 2025

of vertices. Hyperedges are commonly used to represent multi-pin nets or multi-point
connections within circuit. Hypergraph can be directed or non-directed.
 Order of Hypergraph = Size of vertex set,
 Size of Hypergraph = Size of the edges set

Figure 8. Representation of Graph

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Design Flows (contd.)
Partitioning (contd.)
• Partitioning Algorithm:
 A partition or block is a grouped collection of components and cells (A cell is any logical or functional unit built
from component).
 The k-way partitioning problem seeks to divide a circuit into k partitions. The most common partitioning
objective is to minimize the number or total weight of cut edges while balancing the sizes of the partitions.
Often, partition area is limited due to packing considerations and other boundary conditions implied by system
hierarchy, chip size, or floorplan restrictions. Circuit partitioning, is very hard to solve. As the problem gets
bigger, the time needed to find the best solution grows very quickly. There is no known fast and perfect method
to solve balance- constrained partitioning.

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• There are two types of partitioning methods:
 Constructive or Iterative Method : A constructive algorithm creates a partitioning from the graph that represents
the circuit or system. Iterative methods work to improve the quality of an already existing partitioning solution.
 Deterministic or Probabilistic Method : Deterministic programs always produce the same solution each time they
run. Probabilistic methods give different solutions each time because they use random numbers.

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Design Flows (contd.)
Partitioning (contd.)
• Partitioning Algorithm:
 Methods, like the Kernighan-Lin (KL) algorithm and the Fiduccia-Mattheyses (FM) algorithm, can find
good solutions and run relatively quickly. Optimization using simulated annealing can address
particularly challenging partitioning problems. KL algorithm is sensitive to the number of nodes and
edges. The KL algorithm performs partitioning through iterative improvement steps. The KL algorithm is
based on exchanging (swapping) pairs of nodes, each node from a different partition.
 FM algorithm is sensitive to the number of nodes and nets (hyperedges). The FM algorithm is typically
applied to large circuit netlists. This algorithm is more naturally applicable to partitions of unequal size
or the presence of initially fixed cells. FM algorithm offers best tradeoff between solution quality and

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runtime.
 Partition area is limited by packing considerations and other boundary conditions such as chip size, or
floorplan restrictions.

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Design Flows (contd.)
Partitioning (contd.)
• Partitioning Algorithm:

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Figure 9. Cutline Partitioning

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Design Flows (contd.)
Floor Planning
• Floor planning is the art of any physical design. A well and perfect floorplan leads to an ASIC
design with higher performance and optimum area.
• Floor planning can be challenging in that, it deals with the placement of I/O pads and macros as
well as power and ground structure.
• Inputs for floor plan:
1. Netlist (.v)
2. Technology file (techlef)
3. Timing Library files (.lib)

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4. Physical library (.lef)
5. Synopsys design constraints (.sdc)

• After physical design database creation using imported netlist and corresponding library and
technology file, steps are
1. Decide core width and height for die size estimation.
2. IO pad sites are created for placement of IO pad placement.
3. Placement of macros.
4. The standard cell rows created for standard cell placement.
5. Power planning (pre routing)
6. Adding physical only cells

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Design Flows (contd.)
Floor Planning (contd.)
• Apart from this aspect ratio of the core, utilization of core area, cell orientation, and core to
IO clearance are also taken care of during the floorplan stages.

• Floorplan control parameter:

 Aspect ratio: Aspect ratio will decide the size and shape of the chip. It is the ratio between horizontal
routing resources to vertical routing resources (or) ratio of height and width.
Aspect ratio = width/height
 Core utilization:- Utilization will define the area occupied by the standard cells, macros, and other

ECL 1503: Autumn / ODD Session 2025

cells. If core utilization is 0.8 (80%) that means 80% of the core area is used for placing the standard
cells, macros, and other cells, and the remaining 20% is used for routing purposes.
core utilization = (macros area + std cell area + pads area) / total core area

• Pad placement:
 In ASIC design three types of IO Pads. Generally pad placement and pin placement is done by Top-
Level. It is critical to the functional operation of an ASIC design to ensure that the pads have
adequate power and ground connections and are placed properly in order to eliminate electro-
migration and current-switching related problems.
 Power
 Ground
 Signal
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Design Flows (contd.)
Floor Planning (contd.)
• Electro-migration is the movement or molecular transfer of electrons in the metal from one
area to another area that is caused by a high density electric current inflows in the metal.
High density current can create voids or hillocks, resulting in increased metal resistance or
shorts between wires and it can degrade the ASIC performance.

• One can determine the minimum number of ground pads required to satisfy the current
limit, and the required number of power pads equal to the number of ground pads.
Given by Ngnd = Itotal/Imax

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Ngnd = number of ground pads, Itotal = total current in design (sum of static and dynamic currents), Imax=
max EM current.

• Macro placement:
 Macros may be memories, analog blocks. Proper placement of macros has a great impact on the
quality and performance of the ASIC design. Macro placement can be manual or automatic.
 Manual macro placement is more efficient when there are few macros to be placed. Manual macro
placement is done based on the connectivity information of macros to IO pin/pads and macro to macro.
Automatic macro placement is more appropriate if the number of macros is large.

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Design Flows (contd.)
Floor Planning (contd.)
• Types of macros:
 Hard macros: The circuit is fixed. We can’t see the functionality information about macros. Only we
know the timing information.
 Soft macros: The circuit is not fixed and we can see the functionality and which type of gates are using
inside it, and know about its timing information.

• Guidelines to place macros:

 Placement of macros are the based on the fly-lines (its shows the connectivity b/w macro to macro and

ECL 1503: Autumn / ODD Session 2025

macro to pins) so we can minimize the interconnect length between IO pins and other cells.
• Place the macros around to the boundary of the core, leaving some space between macro to core edge
so that during optimization this space will be used for buffer/inverter insertion and keeping large
areas for placement of standard cells during the placement stage.
• Macros that are communicating with pins/ports of core place them near to core boundary.
• Place the macros of same hierarchy together.
• Keep the sufficient channel between macros

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Design Flows (contd.)
Floor Planning (contd.)
• Types of floorplan techniques:
[Link]:- When the chip is divided into blocks in the abutted design there is no gap between the
blocks.
[Link] abutted:- In this design there is a gap between blocks. The connection between the blocks is done
through the routing nets.
[Link] mix of both: This design is a combination of abutted and non- abutted.

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Figure 10. Floor Planning 18
Design Flows (contd.)
Placement
• Placement is the process of finding a suitable physical location for each cell in the block.
Placement does not just place the standard cell available in the synthesized netlist, it also
optimized the design.

• Placement is driven based on different criteria like timing driven, congestion driven, power
optimization.

• Placement is performed in two stages: coarse placement and legalization.

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• Goal of placement:
 Timing, power, area optimization
 Routable design
 Minimum cell density and pin density (reduce the congestion due to cells and pins)
 Minimum timing DRC’s

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Design Flows (contd.)
Placement (contd.)
• Coarse placement:
 During the coarse placement, the tool determines an approximate location for each cell according to
the timing, congestion and multi-voltage constraints. The placed cells don’t fall on the placement grid
and might overlap each other. Large cells like RAM and IP blocks act as placement blockages for
standard cells. Coarse placement is fast and sufficiently accurate for initial timing and congestion
analysis.

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Figure 11. Coarse Placement
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Design Flows (contd.)
Placement (contd.)
• Legalization:
 During legalization, the tool moves the cells to legal locations on the placement grid and eliminate any
overlap between cells. These small changes to cell location cause the lengths of the wire connections to
change, possibly causing new timing violations. Such violations can often be fixed by incremental
optimization, for example: by resizing the driving cells.

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Figure 12. Legalize Partitioning
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Design Flows (contd.)
Placement (contd.)
• Placement constraints provide guidance during placement and placement optimization and
legalization so that congestion and timing violations will be reduced.
 Placement blockages
 Placement bounds
 Density constraint
 Cell spacing constraint

Keep-out margin: it is a region around the boundary of fixed cells in a block in which no

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•
other cells are placed. The width of the keep-out margin on each side of the fixed cell can be
the same or different. Keeping the placement of cells out of such regions avoids congestion
and net detouring and produces better QOR (quality of results).

Figure 13. Illustration of keep-out margin 22

Design Flows (contd.)
Placement (contd.)
• Placement bounds: It is a constraint that controls the placement of groups of leaf cells and
hierarchical cells. It allows you to group cells to minimize wire length and place the cells at
most appropriate locations. When our timing is critical during placement then we create
bounds in that area where two communicating cells are sitting far from another. It is a fixed
region in which we placed a set of cells. It comprises of one or more rectangular or rectilinear
shapes which can be abutted or disjoint. In general we specify the cells and ports to be
included in the bound. If a hierarchical cell is included, all cells in the sub-design belong to
the bound.

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• Types of bounds:
 Soft move bound
 Hard move bound
 Exclusive move bound

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Design Flows (contd.)
Placement (contd.)
• Optimization techniques: Netlist constructing only changes existing gates, does not change
functionality.
 Cloning
 Duplicates gates
 Gate sizing
 Swapping of pins that can change the final delay
 Fan-out splitting

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• Congestion occurs when the number of available routing resources is less than the required
routing resources. This condition we can see in global routing. A congestion map can help us
to visualize the quality of placement. The congestion map shows the borders between global
routing cells highlighted with different colors that represent the different levels of overflow.
The overflow and underflow of the all selected layers. For example, if a highlighted light
blue on the edge global routing cells shows 10/9 that means there are 9 available wire tracks
and the required tracks are 10.

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