STM32 PWM Mode Preface
As we’ve discussed in an earlier tutorial, the timer modules can operate a variety of modes
one of which is the PWM mode. Where the timer gets clocked from an internal source and
counts up to the auto-reload register value, then the output channel pin is driven HIGH. And
it remains until the timer counts reach the CCRx register value, the match event causes the
output channel pin to be driven LOW. And it remains until the timer counts up to the auto-
reload register value, and so on.
The resulting waveform is called PWM (pulse-width modulated) signal. Whose frequency
is determined by the internal clock, the Prescaler, and the ARRx register. And its duty cycle
is defined by the channel CCRx register value. The PWM doesn’t always have to be
following this exact same procedure for PWM generation, however, it’s the very basic one
and the easier to understand the concept. It’s called the up-counting PWM mode. We’ll
discuss further advanced PWM generation techniques as we go on in this series of tutorials.
The following diagram shows you how the ARR value affects the period (frequency) of the
PWM signal. And how the CCRx value affects the corresponding PWM signal’s duty cycle.
And illustrates the whole process of PWM signal generation in the up-counting normal
mode.
STM32 Timers – PWM Output Channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), an input stage for capture (with a digital filter, multiplexing, and Prescaler)
and an output stage (with comparator and output control). The output stage generates an
intermediate waveform which is then used for reference: OCxRef (active high). The polarity
acts at the end of the chain.
And here is a diagram for the capture/compare channel 1 Full Circuitry
And here is a diagram for the output stage that driver the OCx pins
A single STM32 timer usually has multiple channels (4, 6, or whatever found in the
datasheet). Therefore, using a single timer you can independently generate multiple PWM
signals with different duty cycles of course, but they’ll share the same timing (same
frequency), and all of them will be in sync. We’ll do this in the 2nd LAB in this tutorial after
we set up a single PWM channel and get everything up and running.
Here is a snapshot of the general-purpose Timer2 diagram, which highlights the presence
of multiple output compare channels and output drivers.
STM32 Timers In PWM Mode
Pulse width modulation mode allows generating a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register. The PWM mode can be selected independently on each channel (one
PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM
bits in the TIMx_CCMRx register. The user must enable the corresponding preload register
by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload
preload register by setting the ARPE bit in the TIMx_CR1 register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. For applications where you need to
generate complementary PWM signals, this option will be suitable for you.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx≤TIMx_CNT or TIMx_CNT≤TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
NOTE: PWM signals have a lot of properties that we need to control in various applications.
First of which is the frequency of the signal. And secondly, and probably the most important
one, is the duty cycle. Third, is the PWM resolution. And much more to be discussed in
later tutorials, we’ll get into those 3 properties in the next sections down below.
STM32 PWM Frequency
In various applications, you’ll be in need to generate a PWM signal with a specific
frequency. In servo motor control, LED drivers, motor drivers, and many more situations
where you’ll be in need to set your desired frequency for the output PWM signal.
The PWM period (1/FPWM) is defined by the following parameters: ARR value, the Prescaler
value, and the internal clock itself which drives the timer module F CLK. The formula down
below is to be used for calculating the FPWM for the output. You can set the clock you’re
using, the Prescaler, and solve for the ARR value in order to control the FPWM and get
what you want.
STM32 PWM Duty Cycle
In normal settings, assuming you’re using the timer module in PWM mode and generating
PWM signal in edge-aligned mode up-counting configuration. The duty cycle percentage is
controlled by changing the value of the CCRx register. And the duty cycle equals
(CCRx/ARR) [%].
STM32 PWM Resolution
One of the most important properties for a PWM signal is the resolution. It’s the number of
discrete duty cycle levels that you can set it to. This number determines how many steps
the duty cycle can take until it reaches the maximum value. So, the step size or the number
of duty cycle steps can tell how fine can you change the duty cycle in order to achieve a
certain percentage. This can be extremely important in some audio applications, motor
control, or even light control systems.
This is the STM32 PWM resolution formula that can be used to calculate the resolution of
the PWM signal at a specific frequency or even the opposite. If you’re willing to get a 10-Bit
resolution PWM signal, what should the frequency be in order to achieve this? And so on..
In other situations, you’ll need to adjust the ARR value. Therefore, you’ll need to know the
relationship between it and the PWM resolution. This is not a new formula, it’s derived from
the first one and the FPWM equation that you’ve seen earlier in this tutorial. We’ll need it in
later tutorials for designing our Motor driver library and some other applications.
Check this table which shows you some example frequencies and the PWM resolution at
each FPWM frequency.
STM32 PWM Different Modes
The PWM signal generation can be done in different modes, I’ll be discussing two of them
in this section. The edge-aligned and the center-aligned modes.
1- Edge-Aligned Mode
In the edge-aligned PWM mode there exist a couple of possible configurations:
Up-Counting Configuration
Down-Counting Configuration
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF
is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
‘1. If the compare value is 0 then OCxREF is held at ‘0.
2- Center-Aligned Mode
The compare flag is set when the counter counts up when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software.
The diagram below shows some center-aligned PWM waveforms in an example where:
TIMx_ARR=8, PWM mode is the PWM mode 1.