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Data Integrity IP Components Overview

The Data Integrity Building Block IP by Synopsys includes three components: Error Checking and Correction (ECC), a 32-bit Cyclic Redundancy Check (CRC) generator/checker, and a parity checker, aimed at high reliability applications. The ECC provides single-error correction and double-error detection, while the CRC ensures data integrity for varying data stream lengths in network applications. The document also contains proprietary information and legal disclaimers regarding usage and export control compliance.

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0% found this document useful (0 votes)
6 views2 pages

Data Integrity IP Components Overview

The Data Integrity Building Block IP by Synopsys includes three components: Error Checking and Correction (ECC), a 32-bit Cyclic Redundancy Check (CRC) generator/checker, and a parity checker, aimed at high reliability applications. The ECC provides single-error correction and double-error detection, while the CRC ensures data integrity for varying data stream lengths in network applications. The document also contains proprietary information and legal disclaimers regarding usage and export control compliance.

Uploaded by

azfmj22
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

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DWBB Application Specific – Data Integrity
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DesignWare
Foundation
Building Blocks

The Data Integrity Building Block IP consist of three components targeted for high reliability applications.
These components include Error Checking and Correction (ECC), a 32-bit Cyclic Redundancy Check (CRC)
generator/checker, and a parity checker.
The 32-bit CRC polynomial generator/checker provides data integrity on data streams of varying length in
network applications. The ECC component implements single-error correction, double-error detection
(SECDED) error correcting code over a parameterized range of word widths. The parity checker can be used
with peripherals such as disk drives, and with external DRAM or SRAM buffers.

Related Topics
For a listing of the Building Block components and associated datasheets, see:
■ DesignWare Building Block IP User Guide

Version DWBB_202212.0 Synopsys, Inc. SolvNetPlus 1


December 2022 [Link]
DesignWare Building Block IP Datasheet

Copyright Notice and Proprietary Information


© 2022 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
[Link]
All other product or company names may be trademarks of their respective owners.
Free and Open-Source Software Licensing Notices
If applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not
responsible for such websites and their practices, including privacy practices, availability, and content.

Synopsys, Inc.
[Link]

2 SolvNetPlus Synopsys, Inc. Version DWBB_202212.0


[Link] December 2022

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