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VLSI Inverter & OR Gate Simulation Guide

The document details an experiment conducted at Chittagong University of Engineering & Technology focusing on the DC analysis of an inverter and the design of a 2-input OR gate using Cadence Virtuoso. It outlines objectives, theory, parameter setup, simulation results, and conclusions regarding the impact of NMOS width on inverter performance and logical correctness of the OR gate. The experiment enhances understanding of CMOS logic design through practical application and simulation techniques.

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AmitBarua
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5 views6 pages

VLSI Inverter & OR Gate Simulation Guide

The document details an experiment conducted at Chittagong University of Engineering & Technology focusing on the DC analysis of an inverter and the design of a 2-input OR gate using Cadence Virtuoso. It outlines objectives, theory, parameter setup, simulation results, and conclusions regarding the impact of NMOS width on inverter performance and logical correctness of the OR gate. The experiment enhances understanding of CMOS logic design through practical application and simulation techniques.

Uploaded by

AmitBarua
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Chittagong University of Engineering & Technology

Department of Electrical and Electronic Engineering

VLSI Technology Sessional


Course No. : EEE-476
Experiment No. : 03

Experiment Title
DC analysis of an inverter, Drawing the Schematic of a 2 input OR Gate
Using Cadence Virtuoso,
Perform Simulation and Plot the Output Wave Forms

Name : Amit Barua


ID No. : 2002019
Section : A
Date of Experiment : 20.07.2025
Date of Submission : 27.07.2025

Remarks:
TABLE OF CONTENTS
• Objectives

• Introduction

• Theory

• Schematic of Inverter

• Parameter Setup for parametric analysis

• Simulation Results

• Schematic of OR gate

• Symbol of OR gate

• Simulation Results

• Conclusion

• References

ABSTRACT

This experiment exhibits the effect of changing NMOS width on the inverter’s Transfer
Characteristics Curve (TCC) and the design, simulation, schematic and symbol creation of
a 2-input OR gate using Cadence Virtuoso. Both DC and transient simulations were performed
to evaluate inverter behavior and OR gate logical correctness.

KEYWORDS

OR gate, Inverter, Parametric Analysis, Cadence Virtuoso, Symbol creation, NMOS Width
Variation

OBJECTIVES
1. To design and simulate a 2-input OR gate and create its symbol.

2. To verify logical operation using transient response.

3. To analyze the effect of NMOS width on inverter transfer characteristics.

4. To perform parametric simulation in Cadence Virtuoso

1
INTRODUCTION

This experiment includes DC transfer characterization by sweeping the NMOS width,


and step-by-step schematic, symbol, and simulation of a 2-input OR [Link] helps us to
understand how transistor sizing affects inverter performance is fundamental in CMOS logic
design

THEORY

The inverter’s transfer characteristic is influenced by the width of its transistors, affecting
switching threshold and output swing. OR gates in CMOS require specific arrangements
of PMOS and NMOS transistors. Symbol creation allows reuse in hierarchical schematics.

Schematic of Inverter

Figure 1: Schematic Of Inverter

2
PARAMETER SETUP For Parametric Analysis

Cadence NMOS Parameter Setup and Parametric Sweep:

Figure 02: NMOS Parameter Window in Cadence

Figure 3: Parametric Sweep Setup for NMOS Width in Cadence

3
Simulation Results

DC Transfer Characteristics for Different NMOS Widths:

Figure 4: DC Response—Transfer Characteristic Curve for NMOS Width Variation

Schematic of OR gate

Figure 5: Schematic Diagram of 2-input OR gate

4
Symbol o f O R g a t e :

Figure 6: Custom Symbol Created for OR Gate

OR Gate Simulation (Symbol Level):

Figure 7: Transient Output from OR Gate (Symbol instance)

CONCLUSION

This experiment improved proficiency with Cadence Virtuoso for DC and transient simu-
lations, inverter characterization, and OR gate design with symbol creation. Results are
consistent with CMOS logic theory and expected sizing impact.

REFERENCES
1. Lab Manual: DC Analysis, Symbol Creation, and OR Gate Design
2. Cadence Virtuoso Tutorials
5

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