Counters and Register’s

1. Asynchronous (Ripple) Counters:

• What’s an Asynchronous (Ripple) Counter?
An asynchronous counter is made up of flip-flops (FFs) connected in
sequence such that the clock signal is applied only to the first flip-flop (FF
A). Each next flip-flop gets its clock from the previous FF's output. That
means FF A toggles first, then FF B responds after A toggles, and so on. This
introduces a ripple effect—hence the name ripple counter. This counter is
called asynchronous because not all flip-flops are triggered simultaneously.

• How the 4-Bit Counter Works?

Clock Input: Only Flip-Flop A is directly connected to the clock.
J = K = 1 for all FFs: That makes each flip-flop toggle its output whenever it
gets a falling edge (HIGH to LOW) on its clock input.
Chaining:
➢ A toggles on each falling edge of the clock.
➢ B toggles on the falling edge of A’s output.
➢ C toggles on B’s falling edge, and D on C’s.
➢ So, each flip-flop changes state when the one before it goes from 1 to
0.
• Step-by-Step Operation (Using Figure 7-1)
The four flip-flops are labeled A (LSB), B, C, and D (MSB). All flip-flops are
J-K types with J = K = 1, so they toggle their output on each triggering clock
edge. Let’s say all FFs are cleared to 0 (i.e., DCBA = 0000) at the start. It
count’s number as follows:
Clock pulse 1:
o FF A toggles: Q_A = 1 → DCBA = 0001
Clock pulse 2:
o FF A toggles: Q_A = 0
o FF B sees a falling edge from Q_A and toggles: Q_B = 1 → DCBA =
0010
Clock pulse 3:
o FF A = 1
o FF B remains at 1 → DCBA = 0011
Continue this up to 15th pulse: DCBA = 1111
16th pulse: FF A toggles → Q_A = 0 → triggers B, then C, then D to all toggle
back to 0 → DCBA = 0000 again
This completes one full cycle of 16 states.

• Binary Counting:
The outputs (D, C, B, A) represent a 4-bit binary number, starting from 0000
and counting up to 1111 (0 to 15 in decimal), then rolling over to 0000 again.
That’s a MOD-16 counter—it goes through 16 distinct states before
repeating.

• MOD Number Explanation

MOD refers to the number of distinct states before the counter wraps around.
For an asynchronous binary counter:
MOD= 2^N, where N = number of flip-flops
For Figure 7-1:
4 FFs → MOD = 2⁴ = 16
➡ You can make a MOD-8 counter with 3 FFs, MOD-1024 with 10 FFs, and
so on.
• Frequency Division:
Each flip-flop divides the frequency of the signal it receives:
Flip-Flop A toggles every clock pulse → half the clock frequency.
Flip-Flop B toggles every 2 clock pulses → ¼ the clock frequency.
So on…
Meaning: the output of the last flip-flop (D) gives a signal 1/16th the
frequency of the clock. That’s why these are also used as frequency dividers.

• Duty Cycle:

Each output waveform in a binary ripple counter has a 50% duty cycle,
assuming the clock does too. That is: Time high = time low.
But this balance can shift if the counter's MOD number is less than 2ⁿ (more
on that in Section 7-4).

Every output wave toggles with a 50% duty cycle in a MOD-2ⁿ counter.
Time HIGH = Time LOW
This is because each FF toggles on every second negative edge it sees.
For waveform A:
Period = Clock period × 2
HIGH time = Clock period
So duty cycle = (1/2) × 100% = 50%
• ⚠ Signal Flow in Diagram

Traditionally, circuit diagrams go left to right, with inputs on the left and
outputs on the right. But in Figure 7-1, they deliberately did it right to left:
➢ Clock enters from the right
➢ FF A (LSB) is on the rightmost, and FF D (MSB) is on the leftmost
Why?
➡ Because it lines up with bit order (DCBA) of the binary output—it’s easier
to follow the logic of the count visually.

• Example 7-1 — How Many Pulses?

Ques: The counter in Figure 7-1 starts off in the 0000 state, and then
clock pulses are applied. Some time later the clock pulses are
removed, and the counter FFs read 0011. How many clock pulses
have occurred?

The apparent answer seems to be 3 because 0011 is the binary equivalent of

3. With the information given, however there is no way to tell whether or not
the counter has recycled. This means that there could have been 19 clock
pulses; the first 16 pulses bring the counter back to 0000, and the last 3 bring
it to 0011. There could have been 35 pulses (two complete cycles and then
three more), or 51 pulses, and so on.
(Suppose you look at the counter and see 0011 (decimal 3). You might think
3 pulses occurred. But… what if the counter completed a full 16-count cycle
and then reached 3 again? Then, total pulses = 16 + 3 = 19 Or maybe 2 cycles
+ 3 = 35 pulses. You can’t determine how many pulses happened just by
looking at the current state.)

• Example 7-2 — How Many Flip-Flops?

A counter is needed that will count the number of items passing on a

conveyor belt. A photocell and light source combination is used to
 generate a single pulse each time an item crosses its path. The
counter must be able to count as many as one thousand items. How
many FFs are required?

It is a simple matter to determine what value of N is needed so that 2 N >=

1000. Since 29 = 512, 9 FFs will not be enough. 210 = 1024, so 10 FFs would
produce a counter that could count as high as 11111111112 = 102310.
Therefore, we should use 10 FFs. We could use more than 10, but it would be
a waste of FFs because any FF past the tenth one will not be needed.
You need to count up to 1,000 events on a conveyor belt.

(We calculate:
2⁹ = 512 ❌ Not enough
2¹⁰ = 1024 ✅ Works
✅ So, 10 flip-flops are needed to count up to 1000.)

• Example 7-3 — Frequency Divider

There is no integer power of 2 that will equal 60. The closest is 26 = 64. Thus,
a counter using six FFs would act as a MOD-64 counter. Obviously, this will
not satisfy the requirement. It seems that there is no solution using a counter
of the type shown in Figure 7-1. This is partly true; in Section 7-4, we will see
how to modify basic binary counters so that almost any MOD number can be
obtained and we will not be limited to values of 2N
(Start with: Input signal = 60 Hz, Goal: reduce to 1 Hz
You’d need a MOD-60 counter. But 2⁶ = 64 is closest. So we need a special
counter that rolls over after 60 instead of 64. (Section 7-4 explains how to do
that!)
[Link] Delay in Ripple Counters:
Ripple counters are the simplest type of binary counters, as they use the fewest
components to perform counting operations. Each flip-flop (FF) in the counter is
triggered by the output of the preceding one rather than a common clock, creating a
cascading or "rippling" effect. However, this simplicity introduces a major
drawback: the accumulation of propagation delays.
For example, if each FF has a propagation delay time (TPD), the second FF will
respond only after TPD, the third after 2 × TPD, and so forth. This means the Nth FF
won’t react until N × TPD after the initial clock signal. As a result, the overall
response time increases with the number of FFs, making ripple counters unsuitable
for high-speed applications where precise and synchronized timing is critical.
This limitation is visually demonstrated in timing diagrams such as Figure 7-4,
which shows how delays affect a three-bit ripple counter.
In a ripple counter, each flip-flop (FF) takes time to respond because it waits for the
one before it. If each FF responds 50 ns later, the delays add up: the third FF (C)
won’t respond until 150 ns after the initial clock pulse. This usually works fine at
slower input speeds.
But when input pulses come too quickly—like every 100 ns—there isn’t enough
time for all the FFs to catch up. So, a certain state in the counting sequence (like 100,
meaning C=1, B=A=0) never actually happens. If your circuit depends on detecting
that state to trigger another action, it could fail. That’s a serious problem.
To make sure the counter works correctly, the clock period (Tₛ) must be greater than
or equal to the total delay, which depends on the number of FFs (N) and each flip-
flop’s delay (tpd). This gives us the rule:

or
For example, with 4 FFs and TPD= 24 ns, the max frequency is:

If you use 6 FFs instead, the max frequency drops to 6.9 MHZ. So, the more FFs you
add, the slower your counter must run to avoid errors.

Also, ripple counters can briefly show the wrong count—glitches—because FFs
change one after another, not all at once. These glitches may not matter to humans,
but digital circuits will notice and potentially misfire.

Example-01: Why does a ripple counter’s maximum frequency

decrease as more FFs are added?
In a ripple counter, each flip-flop (FF) is triggered by the output of the one before it.
This creates a chain reaction of delays—called propagation delay—as each FF
waits its turn to respond. The total delay grows with each added FF. So, if one FF
takes a short time (say, 12 ns) to react, then two FFs cause 24 ns of delay, three cause
36 ns, and so on.
Because of this growing delay, the clock needs to wait longer before sending the
next pulse—otherwise, the last FF might not respond correctly. That’s why the more
FFs you add, the lower the maximum operating frequency (fₘₐₓ) becomes. The rule
is:

Where:
• N is the number of flip-flops
• TPD is the propagation delay of each flip-flop

Example-02: Calculating the largest MOD counter using tpd = 12 ns

and a clock frequency of 10 MHz.

So, you can build a MOD-256 ripple counter using flip-flops with a 12 ns
delay that operates up to 10 MHz without timing issues.
[Link] (Parallel) Counters
In synchronous or parallel counters, all FFs are triggered simultaneously (in
parallel) by the clock. Because the input pulses are applied to all the FFs, some
means must be used to control when an FF is to toggle and when it is to remain
unaffected by a clock pulse. This is accomplished by using the J and K inputs
and is illustrated in Figure 7-5 for a four-bit, MOD-16 synchronous counter.

Circuit Operation:
To ensure proper counting in a synchronous counter, only the flip-flops (FFs)
that need to toggle on a particular negative-going transition (NGT) of the
clock should have their J and K inputs set to HIGH. Flip-flop A toggles on
every clock NGT, so its J and K are always HIGH. Flip-flop B toggles only
when A is HIGH, so its J and K are tied to A. Flip-flop C toggles when both
A and B are HIGH, with its J and K connected to the logic signal AB.
Similarly, flip-flop D toggles when A, B, and C are all HIGH, using logic
signal ABC at its inputs. This arrangement ensures each FF toggles at the
correct time, enabling accurate binary counting. The basic principle for
constructing a synchronous counter can therefore be stated as follows:
Each FF should have its J and K inputs connected so that they are HIGH only
when the outputs of all lower-order FFs are in the HIGH state.

Truth table:
Advantages of synchronous counter over asynchronous counter:
A synchronous counter changes the state of all flip-flops (FFs) simultaneously,
aligning with the negative-going transitions (NGTs) of the clock pulses. This
design avoids the accumulation of propagation delays seen in asynchronous
counters. Instead, the total response time depends only on the delay of one FF
plus that of a single AND gate. This consistent and minimal delay enables
synchronous counters to operate at higher input frequencies. However, this
improved performance comes at the cost of increased circuit complexity
compared to asynchronous (ripple) counters.

Example-01:
(a) Determine fmax for the synchronous counter of Figure 7-5(a) if tpd for
each FF is 50 ns and tpd for each AND gate is 20 ns. Compare this value with
fmax for a MOD-16 ripple counter.
(b) What must be done to convert this counter to MOD-32?
(c) Determine fmax for the MOD-32 parallel counter.
[Link] with MOD Number <2N
A basic synchronous counter using N flip-flops can count up to a MOD number of
2ⁿ. To obtain MOD numbers less than 2ⁿ, a truncated count sequence is
implemented by intentionally skipping certain states in the count cycle. This is
commonly achieved through logic gating.
In the example shown in Figure 7-6, a MOD-8 counter is modified to operate as a
MOD-6 counter by using a NAND gate connected to the outputs of flip-flops B and
C. When both outputs go HIGH (B = C = 1), the NAND output goes LOW and
triggers an asynchronous clear on all flip-flops, forcing the counter back to the 000
state. This occurs momentarily after the counter reaches the 110 (6) state, creating a
transient state.
This technique ensures that the counter cycles through six stable states (000 to 101),
thus forming a MOD-6 counter. This approach is elegant and efficient:
• It minimizes hardware changes.
• It ensures the counter doesn’t waste time cycling through unwanted states.
• It’s flexible—you can set the reset point wherever you want to define different
MOD values.
However, this method introduces glitches or narrow spikes in output waveforms due
to the brief appearance of the decoded state before clearing. Additionally, the output
waveforms typically lose their 50% duty cycle symmetry.

Figure 7-6: MOD-6 counter produced by clearing a MOD-8 counter when a count
of six (110) occurs
Instead of going through all 8 states (000 to 111), the counter:
➢ The counter progresses from 000 up to 101, which is decimal 5. When the counter
reaches 110 (decimal 6), a transient state, the NAND gate activates the asynchronous
clear, bringing it immediately back to [Link] state 111 is never reached (unless
possibly due to random power-up conditions), making this a MOD-6 sequence. The
transition from 101 → 110 → 000 happens within one clock cycle due to the
asynchronous clear.
The spike seen in the NAND output at pulse 6 is a transient glitch, a momentary dip caused
by the counter briefly entering state 110 before resetting. Notice that the waveform at the B
output contains a spike or glitch caused by the momentary occurrence of the 110 state before
clearing.

General Procedure:
To construct a counter that starts counting from all 0s and has a MOD num ber of X:
➢ Find the smallest number of FFs such that 2N<=X, and connect them as a counter. If
2N = X, do not do steps 2 and 3.
➢ Connect a NAND gate to the asynchronous CLEAR inputs of all the FFs.
➢ Determine which FFs will be in the HIGH state at a count = X; then connect the normal
outputs of these FFs to the NAND gate inputs.

Construct a MOD-10 counter that will count from 0000 (zero) through 1001
(decimal 9).
23 = 8 and 24 = 16; thus, four FFs are required. Because the counter is to have
stable operation up to the count of 1001, it must be reset to zero when the count of
1010 is reached. Therefore, FF outputs D and B must be connected as the NAND
gate inputs. Figure 7-8(b) shows the arrangement.
 Any MOD-10 counter is a decade counter

Decade Counter/Mod-10 Counter:

A MOD-10 counter, also known as a decade counter, is a digital counter with ten unique states,
regardless of the specific sequence. When it counts in binary from 0000 to 1001 (decimal 0 to 9),
it’s specifically called a BCD (Binary-Coded Decimal) counter because it uses only valid BCD
codes. These counters are widely used in applications that require event or pulse counting with
output shown on decimal numeric displays. A key advantage of the BCD decade counter is that
it can divide input pulse frequency by 10, with the output taken from the most significant flip-
flop (FF D), producing an output frequency that’s one-tenth the input.

Mod-16 Counter:
To build a MOD-60 counter as required in Example 7-3, the surrounding content suggests
cascading a **MOD-6 counter** with a **MOD-10 (decade) counter** to achieve the desired
total of 60 states. The MOD-6 counter cycles through six clock pulses and then sends a pulse to
the MOD-10 stage, which advances once every six counts. This arrangement effectively produces
60 unique combinations before resetting, dividing an incoming 60 Hz signal down to 1 Hz—ideal
for timekeeping applications like digital clocks. Each stage is built from standard flip-flops and
uses logic gating to reset at the appropriate count, ensuring the counter operates reliably within the
specified range.
[Link] Down and Up/Down Counters
A synchronous down counter works similarly to an up counter, but instead of using the normal
outputs of lower-order flip-flops to control toggling, it uses their inverted outputs. For example,
FF B toggles when A = 0, FF C when A = B = 0, and so on—producing a downward sequence
from 15 to 0 and recycling back to 15.
To build a parallel up/down counter, a control input labeled Up>Down determines the count
direction. When this input is HIGH, the counter operates in up mode, using the normal outputs of
flip-flops; when it is LOW, the counter switches to down mode, relying on the inverted outputs.
This control is implemented through a set of AND gates, selectively enabling either the normal or
inverted outputs to reach the J and K inputs of the next flip-flops.

The counter’s behavior is shown in its timing diagram, where the counting direction changes
depending on the Up>Down signal. Its state transition diagram also reflects this dual behavior,
with each state branching conditionally based on the control input. The use of dual arrows from
each state illustrates that the next state is determined by whether the counter is set to count up or
down.

Up/Down Counters
In a parallel up/down counter, the control input controls the values fed to the J and K inputs of
the successive FFs.

[Link]-settable Counter(Parallel Loading Counter)

A pre-settable synchronous counter, like the one in Figure 7-12, allows loading any desired
starting value through a process called parallel loading. This is done asynchronously by
applying the desired binary count to data inputs (P2, P1, P0) and pulsing the PARALLEL
LOAD (PL) line LOW. While PL is LOW, the counter ignores clock signals and uses the
PRESET and CLEAR inputs to immediately set each flip-flop to match the data inputs. Once
PL returns HIGH, the counter resumes normal synchronous counting from the newly loaded
value. This feature is commonly used in counters like the 74ALS190–193 and 74HC190–193,
making them highly useful in applications where custom reset points or mid-count starts are
required.

Synchronous counter with asynchronous parallel load

[Link] a Counter
Initially, a simple approach involves connecting flip-flop outputs directly to indicator LEDs,
where ON represents logic 1 and OFF represents logic 0. This allows users to mentally decode
binary values, which works fine for small counters (e.g., a 4-bit BCD counter showing 0110
as decimal 6). However, as counters grow in size, mental decoding becomes impractical. More
importantly, many digital systems require automatic detection of specific counter states to
trigger operations—like initiating a task when the counter hits 101100 (decimal 44). In such
cases, electronic decoding circuitry is essential for real-time automation, especially when
human intervention is too slow or impractical.

Active High Decoding:

A MOD-X counter has X unique binary states stored in its flip-flops, and a decoding network
is used to detect each of these states electronically. This network typically consists of logic
gates—often AND gates—that output a HIGH signal when a specific combination of flip-flop
outputs (a particular counter state) is present. For example, in a MOD-8 counter, eight three-
input AND gates are used, with each gate configured to decode one of the eight binary states
from 000 to 111. When a specific state occurs, only its corresponding gate outputs HIGH,
which can be used to activate an LED or trigger a system operation. This method not only
simplifies visual display of the current count but also enables automatic control functions in
digital systems, eliminating the need for manual interpretation or intervention.
Active Low Decoding:
If NAND gates are used in place of AND gates, the decoder outputs produce a normally
HIGH signal, which goes LOW only when the number being decoded occurs. Both types of
decoders are used, depending on the type of circuits being driven by the decoder outputs.

BCD Counter Decoding:

A BCD (Binary-Coded Decimal) counter produces 10 unique binary states representing
decimal digits 0 through 9, and these can be decoded using a BCD decoder. The decoder
generates 10 outputs—each associated with one of the 10 decimal values—which can directly
control indicator LEDs or, more commonly, a single seven-segment display. These displays
use seven light-emitting segments to form decimal digits, and the decoder activates the
appropriate segments to visually represent each number. Because such counters and displays
are so widely used, especially in digital clocks and counters.

[Link] Synchronous Counter

Synchronous counters use only synchronous flip-flop inputs to generate a desired count
sequence, avoiding glitches caused by asynchronous control signals. To analyze such counters,
we use a Present state/Next state table by applying each state to the control input logic
expressions (J-K or D) and observing how the counter transitions. For JK flip-flops, toggling
is controlled by logic conditions based on current states, while D flip-flop counters are driven
by logic expressions for each D input. These can be simplified using Boolean algebra—often
involving XOR functions. A properly designed synchronous counter can be self-correcting,
meaning any unused state eventually leads back into the valid counting sequence. Using this
method, we can design MOD-N counters with custom sequences and verify their stability using
state tables and transition diagrams.

Analyze counter designs of this type by predicting FF control inputs for each state of
the counter. A PRESENT state/NEXT state table is very useful for this purpose.

Synchronous up counter state transition diagram and waveform.

10. Synchronous Counter Design