1. What is System Bus? Explain the different types of bus.
A System Bus is a communication pathway used to connect major components of a computer system
such as CPU, memory, and I/O devices. It allows data and control signals to be transferred between
them.
Types of System Buses
Type Purpose
Data Bus Transfers actual data between CPU and other components. Bidirectional.
Address Bus Carries memory addresses or I/O addresses to identify data location. Unidirectional.
Control Bus Transfers control and timing signals (Read/Write, Interrupt, Clock, etc).
2. Explain the concept of Three State Gate with diagram.
A Three-state (Tri-state) Gate has three output conditions:
• Logic 1
• Logic 0
• High Impedance (Hi-Z) – effectively disconnects output from circuit, like an open switch.
Diagram (ASCII form):
EN
Input --->[ Three State Gate ]----> Output
Hi-Z
Used in bus systems to prevent multiple devices from driving the bus at the same time.
3. What is Bus Arbitration? Why do we need it? Types of arbitration.
Bus Arbitration is the process of deciding which device gets control of the system bus when multiple
devices request it.
Need
• To avoid conflict and data corruption.
• To ensure fair and efficient usage of the bus.
Types
1. Daisy Chain Arbitration (Serial)
2. Centralized Parallel Arbitration
3. Distributed Arbitration
4. Draw the functional unit diagram of computer system and explain.
Components
• Input Unit
• Output Unit
• Memory Unit
• Arithmetic Logic Unit (ALU)
• Control Unit (CU)
• System Bus
┌─────────────┐
│ Input │
└──────┬──────┘
┌──────▼──────┐
│ CU & ALU │ <----> Registers
└──────┬──────┘
┌──────▼──────┐
│ Memory │
└──────┬──────┘
┌──────▼──────┐
│ Output │
└──────────────┘
5. IEEE 754 Floating Point Standards + conversion
IEEE Single Precision (32-bit) format:
| Sign | Exponent (8 bit) | Mantissa/Fraction (23 bit) |
Convert: 1.01101 × 2⁻¹¹
• Sign = 0 (positive)
• Exponent = -11 + 127 = 116 → 01110100
• Mantissa = 01101000000000000000000
IEEE 754 Representation
0 01110100 01101000000000000000000
6. Booth’s Algorithm for (20) × (-10)
Binary:
• 20 = 00010100
• -10 = 11110110 (2’s complement 8-bit)
Flowchart available if needed. Final product = -200 (binary: 1111011001101000) after Booth’s steps.
7. Practice Problems
Examples:
1. Multiply 15 × –6 using Booth
2. Divide 35 ÷ 5 using restoring / non-restoring division
8. Addressing Modes
Methods to specify operand location in instructions.
Mode Example Meaning
Immediate MOV R1, #5 Operand is constant
Direct MOV R1, 4000 Memory address directly
Indirect MOV R1, @R3 Address stored in register
Register MOV R1, R2 Operand in register
Indexed MOV R1, 4000(R3) Index added to base
Relative JMP 50 PC + offset
9. Instruction, format & cycle
Instruction: A binary command telling CPU what operation to perform.
Instruction Format
| Opcode | Address / Operand |
Example: ADD R1, R2
Instruction Cycle
1. Fetch
2. Decode
3. Execute
4. Write Back
10. Why Carry Look Ahead Adder?
To speed up binary addition by eliminating ripple delays. Computes carry signals in parallel.
11. RAM vs ROM
RAM ROM
Volatile Non-volatile
Temporary storage Permanent
Read/write Read only
Used for main memory Used for firmware
12. RISC vs CISC
RISC CISC
Simple & fewer instructions Complex instructions
Single cycle execution Multi-cycle
Hardwired Microprogrammed
More registers Less registers
13. Asynchronous vs Synchronous communication
Synchronous Asynchronous
Uses clock No clock
Faster Slower
Synchronous Asynchronous
Expensive Cheaper
14. Hardwired vs Microprogrammed CU
Hardwired Microprogrammed
Fixed logic circuits Control stored in ROM
Faster Slower
Difficult to modify Easy to modify
15. SRAM vs DRAM
SRAM DRAM
Flip-flops Capacitors
Faster Slower
Expensive Cheaper
Cache Main memory
16. Array Multiplier
Hardware circuit producing product by shifting and adding partial products.
17. Input-Output Interface
Connects CPU with I/O devices using:
• Status register
• Control signals
• Data register
18. Cache Mapping
Type Description
Direct One memory block ↔ One cache line
Type Description
Associative Any block ↔ Any line
Set Associative Combination of both
19. DMA
Direct Memory Access transfers data between memory & I/O without CPU involvement.
20. Interrupts
Signals that temporarily pause CPU to handle urgent tasks.
21. Pipelining
Breaks instruction into stages to allow parallel execution, improving throughput.
22. Common Bus using Multiplexers
MUX selects which register outputs onto bus at one time using selection lines.
23. ALU and CU
ALU CU
Performs arithmetic/logic operations Manages control of system
Works with registers Generates control signals