Course Code: 22CST402

Prepared By,
Jaseela Beevi S
Assistant Professor
Dept. of CSE, TKMCE Dept. of CSE, TKMCE 1
Course Outcomes
CO1: Recognize and express the relevance of basic components, I/O organization and
pipelining schemes in a digital computer (Understand)
CO2: Explain the types of memory systems and mapping functions used in memory
systems (Understand)
CO3: Demonstrate the control signals required for the execution of a given instruction.
(Apply)
CO4: Illustrate the design of Arithmetic Logic Unit and explain the usage of registers in
it (Apply)
CO5:Explain the implementation aspects of arithmetic algorithms in a digital
computer (Apply)
CO6:Develop the control logic for a given arithmetic problem (Apply)

Dept. of CSE, TKMCE 2

Module - I
Basic Structure of computers – functional units - basic operational concepts
- bus structures. Memory locations and addresses - memory operations,
Instructions and instruction sequencing, addressing modes.

Basic processing unit – fundamental concepts – instruction cycle –

execution of a complete instruction - single bus and multiple bus
organization.

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Computer Organization & Architecture
Computer Architecture:
- Deals with functional behaviour of computer system.
- Design Implementation for the various parts of a computer.

Computer Organization:
- Deals with structural relationship.
- Operational attributes are linked together and contribute to realize the
architectural specification.
Architecture describes what the computer does and organization describes
how it does.
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Computer Types
Computers are classified based on the parameters like
• Speed of operation
• Cost ü Desktop Computers
• Computational power ü Notebook Computers
• Type of application ü Workstations
ü Enterprise Systems (Mainframes)
ü Servers
ü Super Computers

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 Functional Units

1) Input Unit
2) Memory Unit
3) Arithmetic and Logic Unit
4) Control Unit
5) Output Unit

ref: Page No: 4,5 and 6 of your text book for

more... Dept. of CSE, TKMCE 6
Basic Operational Concepts
To perform a given task, an appropriate program consisting of a list of
instructions is stored in the memory. Individual instructions are brought
from the memory into the processor, which executes the specified
operations.
Data to be used as instruction operands are also stored in the memory.

A typical instruction may be,

Add LOCA, R0
This instruction adds the operand at memory location LOCA, to operand in
register R0 & places the sum into register R0.

Dept. of CSE, TKMCE 7

Basic Operational Concepts
Add LOCA, R0
This instruction requires the performance of several steps,
1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R0
3. Finally the resulting sum is stored in the register R0

The effect of the above instruction can be realized by the two instruction
sequence.
Load LOCA, R1 #transfers the content of memory location LOCA into processor register R1
Add R1, R0 #adds the contents of registers R1 nd R0 and places the sum to R0

Dept. of CSE, TKMCE 8

Basic Operational Concepts
The transfers between memory and the processor are started by
sending the address of the memory location to be accessed to the
memory unit and issuing the appropriate control signals.

The data are then transferred to or from the memory.

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Connection between the processor and memory

• The processor contains a number of

registers used for several different
purposes.
• The Instruction Register (IR) holds the
instruction that is currently being executed.
• The Program Counter (PC) contains the
memory address of the next instruction to
be fetched and executed.

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Connection between the processor and memory
• R0 to Rn-1 (n general purpose registers) - They serves a variety of functions.
• Memory Address Register (MAR) - holds the address of the location to be
accessed.
• Memory Data Register (MDR) - holds the data to be written into or read
out of the address location.

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Operating Steps for Program Execution
1. Execution of the program (stored in memory) starts when the PC is set to
point to the first instruction of the program.

2. The contents of the PC are transferred to the MAR and a Read control
signal is sent to the memory.

3. The addressed word is read out of the memory and loaded into the MDR.
Next, the contents of the MDR are transferred to the IR.

4. If the instruction involves an operation to be performed by the ALU, it is

necessary to obtain the required operands.
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Connection between the processor and memory
5. If an operand resides in memory (it could also be in a general purpose
register in the processor), it has to be fetched by sending its address to the
MAR and initiating a Read cycle.

6. When the operand has been read from the memory into the MDR, it is
transferred from the MDR to ALU.

7. After one or more operands are fetched in this way, the ALU can perform
the desired operation.

8. If the result of the operation is to be stored in the memory, then the

result is sent to the MDR.

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Connection between the processor and memory
9. The address of the location where the result is to be stored is sent to the
MAR, and a write cycle is initiated.

10. At some point during the execution of the current instruction, the
contents of the PC are incremented so that the PC points to the next
instruction to be executed.

Thus, as soon as the execution of the current instruction is completed, a

new instruction fetch may be started.

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Interrupt Handling
Normal execution of a program may be preempted if some device requires
urgent service.
For example, a monitoring device in a computer-controlled industrial
process may detect a dangerous condition. In order to respond immediately,
execution of the current program must be suspended.

To cause this, the device raises an interrupt signal, which is a request for
service by the processor.
The processor provides the requested service by executing a program called
an Interrupt Service Routine (ISR)

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Interrupt Handling - ISR
Because such diversions may alter the internal state of the processor, its
state must be saved in the memory before servicing the interrupt request.

The information that is saved includes,

üThe contents of the PC
üThe contents of the general-purpose registers
üSome control information.

When the ISR is completed, the state of the processor is restored from the
memory so that the interrupted program may continue.
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Bus Structure

BUS: A group of lines(wires) that serves as a connecting path for several

devices of a computer is called a bus.

The following are different types of buses:

1. Data Bus 2. Address Bus 3. Control Bus

Data Bus:
üIt carries data from one component to other component connected to it.
üIt is bidirectional in nature.
üIt consist of 8, 16, 32 or more parallel signal lines.

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Bus Structure
Address Bus:
ü It carries address information about where in memory the data is to be
transferred to or from.
ü It is unidirectional in nature.
ü It consist of 16, 20, 24 or more parallel lines.

Control Bus:
ü It carries the control and timing information.
ü It is bidirectional in nature.
ü Control information is used for directing the activities of all units.

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Bus Structure
Single Bus Structure: The simplest way to interconnect the functional units
is to use a single bus.

ü All units are connected to this bus.

ü The bus can be used for only one transfer at a time (only two units
can actively use the bus at any given time).
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Bus Structure

Advantages of using single bus

structure:
ülow cost
üflexibility for attaching
peripheral devices.

Multiple Bus Structure: One bus is

used to fetch instructions while ü More concurrency in operations
other is used to fetch data, ü Better performance
ü Increased cost
required for execution.
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Bus Structure
Buffer Registers:
Slow speed devices include a buffer register to hold the information during
transfers.
eg., Consider the transfer of an encoded character from a processor to
printer. Processor sends the character to printer over the bus to the printer
buffer. Once the buffer is loaded the printer can start printing without for
the intervention by the processor.

The bus and the processor are no longer needed and can be used for other
activity. Thus buffer register smooth out the timing differences among
processors, memories and I/O devices.
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Memory Locations and Addresses

ü Memory consist of many millions of storage

cells, each of which can store 1 bit.

ü Data is usually accessed in n-bit groups. ‘n’ is

called word length.

ü The memory of a computer can be

schematically represented as a collection of
words.

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Memory Locations and Addresses
ü Main memory is the second major subsystem in a computer.
ü It consist of a collection of storage locations, each with a unique identifier,
called an address.

ü Data is transferred to and from memory in group of bits called words. A

word can be a group of 8 bits, 16 bits, 32 bits or 64 bits (and growing).
ü If the word is 8 bits, it is reffered to as a byte. a 16 bit word is reffered to
as a 2-byte word, or a 32 bit word is reffered to as a 4-byte word.

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Memory Locations and Addresses

If the word length of a computer is

32 bits, a single word can store a
32-bit signed number or four
ASCII-encoded characters, each
occupying 8 bits.

Machine instructions may require

one or more words for their
representation.

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Memory Locations and Addresses
• Accessing the memory to store or retrieve a single item of information,
either a word or a byte, requires distinct names or addresses for each
location.

• We can use numbers from 0 to 2k − 1, for some suitable value of k, as the

addresses of successive locations in the memory. Thus, the memory can
have up to 2k addressable locations.

• The 2k addresses constitute the address space of the computer. For

example, a 24-bit addres generates an address space of 224 (16,777,216)
locations.

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Memory Locations and Addresses
a 24-bit address -> an address space of 224 (16,777,216) locations - 16M (16
mega),

a 20-bit address -> an address space of 220 (1,048,576) - 1M .

a 32-bit address -> an address space of 232 or 4G (4 giga) locations,

where 1G is 230.

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Memory Locations and Addresses
1 Kilobyte (KB) = 1024 Bytes
1 Megabyte (MB) = 1024 Kilobytes (KB)
1 Gigabyte (GB) = 1024 Megabytes (MB)
1 Terabyte (TB) = 1024 Gigabytes (GB)
1 Petabyte (PB) = 1024 Terabytes (TB)
1 Exabyte (EB) = 1024 Petabytes (PB)
1 Zettabyte (ZB) = 1024 Exabytes (EB)
1 Yottabyte (YB) = 1024 Zettabytes (ZB)

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Byte Addressability
The word length - 16 to 64 bits.
It is impractical to assign distinct addresses to individual bit locations in the
memory. The most practical assignment is to have successive addresses refer
to successive byte locations in the memory. This is the assignment used in
most modern computers. This type of memory is known as byte addressable
memory.

Byte locations have addresses 0, 1, 2,.... Thus, if the word length of the
machine is 32 bits, successive words are located at addresses 0, 4, 8,..., with
each word consisting of four bytes.

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Big-Endian and Little-Endian Assignments
There are two ways that byte
addresses can be assigned across
words.
üThe name big-endian is used when
lower byte addresses are used for
the more significant bytes (the
leftmost bytes) of the word.
üThe name little-endian is used when
lower byte addresses are used for
the less significant bytes (the
rightmost bytes) of the word.

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Big-Endian and Little-Endian Assignments
Consider a computer memory as a large array of Bytes. Indices into this
array are called “addresses”.
Suppose a 32 bit integer is stored in memory location 100.

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Big-Endian and Little-Endian Assignments
What part of the 32 bit quantity is stored at each address?

12 34 56 78 (12345678)16

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Memory Operations
Two basic operations involving the memory are Read and Write.
üThe Read operation transfers a copy of the contents of a specific memory
location to the processor. The memory contents remain unchanged.
To start a Read operation, the processor sends the address of the desired
location to the memory and requests that its contents be read.

üThe Write operation transfers an item of information from the processor

to a specific memory location, overwriting the former contents of that
location.
To initiate a Write operation, the processor sends the address of the desired
location to the memory, together with the data to be written into that
location. The memory then uses the address and data to perform the write.
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Instructions and Instruction Sequencing
A computer must have instructions capable of performing four types of
operations:

• Data transfers between the memory and the processor registers

• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers

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Instructions and Instruction Sequencing

• Data transfers between the memory and the processor registers

(1) Register Transfer Notations

(2) Assembly Language Notations

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Register Transfer Notations
üIt is used for the transfer of information from one location in a computer
to another.
üPossible locations that may be involved in such transfers are memory
locations, processor registers, or registers in the I/O subsystem.
üMost of the time, we identify such locations symbolically with convenient
names.
Example,
Locations - LOC, PLACE, A
Processor Registers - R0, R1, R2, R3, R4, R5
I/O Registers - DATAIN or OUTSTATUS

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Register Transfer Notation (RTN)
Example 1:
To describe the transfer of information, the contents of any location are
denoted by placing square brackets around its name.
R2 ← [LOC]
Thus, the expression means that the contents of memory location LOC are
transferred into processor register R2.

Example 2:
consider the operation that adds the contents of registers R2 and
R3, and places their sum into register R4.
R4 ← [R2]+[R3]

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Assembly Language Notations
This is another type of notation to represent machine instructions and
programs.

Example 1:
a generic instruction that causes the transfer from memory location LOC to
processor register R2, is specified by the statement.
Load R2, LOC
The contents of LOC are unchanged by the execution of this instruction, but
the old contents of register R2 are overwritten.
The name Load is appropriate for this instruction, because the contents read
from a memory location are loaded into a processor register.

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Bus Structure
Example 2:
The second example of adding two numbers contained in processor registers
R2 and R3 and placing their sum in R4 can be specified by the assembly-
language statement
Add R4, R2, R3
In this case, registers R2 and R3 hold the source operands, while R4 is the
destination.

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Basic Instruction Types
The operation of adding two numbers is a fundamental capability in any
computer.
The statement “C = A + B” in a high-level language program
instructs the computer to add the current values of the two variables called
A and B, and to assign the sum to a third variable, C.

The contents of these locations represent the values of the three variables.
Hence, the above high-level language statement requires the action
C ← [A]+[B]

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Basic Instruction Types
Different instruction formats for performing the above mentioned operation

(1) Three Address Instruction Format

Operation Source1, Source2, Destination
Eg., Add A, B, C
(2) Two Address Instruction Format
Operation Source, Destination
Eg., Add A, B Move B, C
Add A,C

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Basic Instruction Types
(3) One Address Instruction Format
Operation Source Load A
Eg., Add A Add B
Store C
When a second operand is needed (eg., incase of Add instn), it is understood
implicitly to be in a unique location. A processor register, usually called the
Accumulator, may be used for this purpose.

(4) Zero Address Instruction Format

Locations of all operands are defined implicitly.

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Basic Instruction Types
Let us now consider a typical arithmetic operation. The statement
C = A + B which means C ← [A]+[B]
To carry out this action, the contents of memory locations A and B are fetched from the memory
and transferred into the processor where their sum is computed. This result is then sent back to
the memory and stored in location C.
The required action can be accomplished by a sequence of simple machine instructions.
We choose to use registers R2, R3, and R4 to perform the task with four instructions:

Load A, R2
Load B, R3
Add R2, R3, R4
Store R4, C
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Instruction in high level language:- C=A+B

Assumption: Arithmetic operations are allowed only on operands that are

in processor register.
Three Address Instruction Two Address Instruction
Load A, R2 Move A, R1
Load B, R3 Move B, R2
Add R2, R3, R4 Add R1, R2
Store R4, C Move R2, C

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Example: evaluate X = ( A + B ) * ( C + D )

Three Address Two Address One Address Zero Address

Instruction Instruction Instruction Instruction
Add A, B, R1 Move A, R1 Load A Push A
Add C, D, R2 Add B, R1 Add B Push B
Mul R1, R2, X Move C, R2 Store T1 Add
Add D, R2 Load C Push C
Mul R1, R2 Add D Push D
Move R2, X Mul T1 Add
Store X Mul
Pop X

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Instruction Execution and Straight-Line Sequencing
Assumption: word length is 32 bits
memory is byte-addressable.
The three instructions of the program are in successive word locations,
starting at location i.

Move A, R0
Add B, R0
Move R0, C

Since each instruction is 4 bytes long, the second and third instructions are
at addresses i + 4 and i + 8

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Instruction Execution

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Instruction Execution and Straight-Line Sequencing
üThe processor contains a register called the program counter (PC), which
holds the address of the next instruction to be executed.
üTo begin executing a program, the address of its first instruction (i in our
example) must be placed into the PC.
üThen, the processor control circuits use the information in the PC to fetch
and execute instructions, one at a time, in the order of increasing
addresses. This is called straight-line sequencing
üDuring the execution of each instruction, the PC is incremented by 4 to
point to the next instruction.
üThus, after the Move instruction at location i + 8 isexecuted, the PC
contains the value i + 12, which is the address of the first instruction of the
next program segment.

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Executing a given instruction is a two-phase procedure.
first phase - instruction fetch
The instruction is fetched from the memory location whose address is in the PC. This
instruction is placed in the instruction register (IR) in the processor.
second phase - instruction execution
The instruction in IR is examined to determine which operation is to be performed.
The specified operation is then performed by the processor. This involves,
ü fetching operands from the memory or from processor registers
ü performing an arithmetic or logic operation
ü storing the result in the destination location.
At some point during this two-phase procedure, the contents of the PC are advanced
to point to the next instruction.
When the execute phase of an instruction is completed, the PC contains the address
of the next instruction, and a new instruction fetch phase can begin.

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Branching Fig: Straight Line program of adding
n numbers

Consider the task of adding a list of n

numbers.
The addresses of the memory
locations containing the n numbers
are symbolically given as NUM1,
NUM2,..., NUMn, and
separate Add instructions are used to
add each number to the contents of
register R0. After all the numbers
have been added, the result is placed
in memory location SUM

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Branching
(Addition of ‘n’ numbers)

Instead of using a series of long Add

instructions, it is possible to use a single
Add instruction in a program loop.

Loop - It is a straight line sequence of

instructions executed as many times as
needed. It starts at location LOOP and
ends at the instruction Branch > 0

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Branching (Addition of ‘n’ numbers)
üHere the location N stores the value of n.
üProcessor register R1 is used as a counter to determine the number of
times the loop gets executed.
üThe contents of the location N are moved into R1 at the start of program
execution.
üAfter that, register R0 is cleared.
üThe address LOOP is reloaded again and again until R1 becomes 0 (this
means all numbers are added).Every time a number is added, then the R1
value is decremented.
üWhen R1 becomes 0, we come out of the loop and the result which is
stored at R1 is copied into memory location SUM

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Branch Instruction
• This type of instruction loads a new address into the program counter.
• As a result, the processor fetches and executes the instruction at this new
address, called the branch target, instead of the instruction at the location
that follows the branch instruction in sequential address order.
• A conditional branch instruction causes a branch only if a specified
condition is satisfied.
• If the condition is not satisfied, the PC is incremented in the normal way,
and the next instruction in sequential address order is fetched and
executed.

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Condition Codes
The processor keeps track of information about the results of various
operations for use by subsequent conditional branch instructions. This is
done by recording the information in individual bits, called condition code
flags.

These flags are grouped together in a special processor register called the
condition code register or status register. Individual condition code flags are
set to 1 or cleared to 0, depending on the outcome of the operation
performed.

Four commonly used flags are,

N (negative), Z(zero), V(overflow), C(carry)

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Condition Codes
N (negative) - set to 1 if the result is negative; otherwise cleared to 0
Z (zero) - set to 1 if the result is 0; otherwise, cleared to 0
V (overflow) - set to 1 if arithmetic overflow occurs; otherwise, cleared to 0
C (carry) - Set to 1 if a carry-out results from the operation;
otherwise, cleared to 0

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Addressing Modes
The different ways in which the location of an operand is specifid in an
instruction are called addressing modes.

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Dept. of CSE, TKMCE 56
Addressing Modes
1) Immediate Addressing mode

ü The operand is specified in the instruction explicitly.

ü Instead of address field, an operand field is present that contains the
operand.

Examples:

ADD 10 will increment the value stored in the accumulator by 10.

MOV R #20 initializes register R to a constant value 20.

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Addressing Modes
2) Direct Addressing Mode
üThe address field of the instruction contains
the effective address of the operand.
üOnly one reference to memory is required to
fetch the operand.
üIt is also called as absolute addressing mode.
Example-
ü ADD X will increment the value stored in the
accumulator by the value stored at memory
location X.
AC ← AC + [X]

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Addressing Modes
3) Indirect Addressing Mode
üThe address field of the instruction specifies
the address of memory location that contains
the effective address of the operand.
üTwo references to memory are required to
fetch the operand.
Example-
ADD X will increment the value stored in the
accumulator by the value stored at memory
location specified by X.
AC ← AC + [[X]]
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Basic Processing Units
In this chapter you will learn about:
• How a processor executes instructions
• The internal functional units of a processor and how they are
interconnected
• Hardware for generating internal control signals
• The microprogramming approach
• Microprogram Organization

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Basic Processing Units
Fundamental Concepts:
üA typical computing task consists of a series of operations specified by a
sequence of machine-language instructions that constitute a program.
üThe processor fetches one instruction at a time and performs the
operation specified. Instructions are fetched from successive memory
locations until a branch or a jump instruction is encountered.
üThe processor uses the program counter, PC, to keep track of the address
of the next instruction to be fetched and executed. After fetching an
instruction, the contents of the PC are updated to point to the next
instruction in sequence.
üA branch instruction may cause a different value to be loaded into the PC.
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Consider a 32-bit computer in which each instruction is contained in one word in the
memory. To execute an instruction, the processor has to perform the following steps:
1. Fetch the contents of the memory location pointed to by the PC. The contents of
this location are the instruction to be executed; hence they are loaded into the IR.
IR ← [[PC]]
2. Increment the PC to point to the next instruction.
PC ← [PC] + 4
3. Carry out the operation specified by the instruction in the IR.

Fetching an instruction and loading it into the IR is usually referred to as the

instruction fetch phase. Performing the operation specified in the instruction
constitutes the instruction execution phase.

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Internal Organization of the processor

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Internal Organization of the processor
ALU and all registers are interconneted via a single common bus (internal
bus).
The data and address lines of the external memory bus are connected to the
internal processor bus via the MDR and MAR.
Data may be loaded into MDR either from the memory bus or from the
internal processor bus.
The input of the MAR is connected to the internal bus and its output is
connected to external bus.
The control lines of the memory bus are connected to the instruction
decoder and control logic block.
This unit is responsible for issuing the signals that control the operations of
all the units inside the processor and for interacting with the memory bus.

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R0 to R(n-1) general purpose register.
Registers may be provided for general purpose use by the programmer.
Some of them are special purpose registers (index register & stack pointer)
(Three registers - X,Y, TEMP)
They are used by the processor for temporary storage during the execution
of some instructions.
The MUX selects either the output of register Y or a constant value 4 (to
increment the content of PC ) to be provided as input A of the ALU.

The registers, the ALU, and the interconnecting bus are colectively referred
to as the datapath

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Internal Organization of the processor

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Internal Organization of the processor

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