Registration No:
- 2 3
Total Number of Pages: 02
2 6- Course: IDD ([Link] and [Link])/[Link]
/ 2 0 Sub_Code: EOPC2004
/0 1
3rd Semester Regular/Back Examination: 2025-26
-2 0
SUBJECT: Digital Electronics
1
29
BRANCH(S): AI, CSE, CSEAI, CSEAIML, CSEDS, CSEIOT, CSIT, CST, IT
Time: 3 Hour
Max Marks: 100
[Link] : U613
- 2 3
-
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two
6
0 2from Part-III.
1 / 2
The figures in the right hand margin indicate marks.
0 /0 Part-I
Q1
-2
Answer the following questions: (2 x 10)
91 are minterms and maxterms?
2Find - 2 3
a) What
6 -to implement a 2-input
b) the minimum number of 2-input NAND gates required
0 2
c) How many OR gate and half adder are required to/2
XOR gate.
/ 0 1 implement a full adder Circuit?
e) Perform the following binary arithmetic:2(i)01011 + 0110, (ii) 11100 - 1011
d) What is essential prime implicant?
f) Define error-detecting code with an1 -
g) Define functional completeness 9 example.
2of logic gates.
3forfrequency.
h) A 4 bit modulo-16 ripple counter uses JK flipflops. If the propagation delay of each
-
Flip-flop is 50 ns. Then find the maximum clock
- 2
6
i) Find the minimum number of flip-flops required
2 Part-II
a Mod-9 (BCD) counter.
j) Define Algorithmic State Machine (ASM).
2 0
/ Type Questions- (Answer Any Eight out of
Q2 Only Focused-Short Answer
/ 0 1 (6 × 8)
Twelve)
- 2 0
9 1 2 3
a) Explain SR and
2 3
JK flip-flops with characteristic tables.
6 -
- a 4-to-
b) Implement the Boolean function F(A, B, C, D) = Σ(1, 3, 5, 7, 8, 12, 14)
2
-the- Quine–McCluskey minimization technique. /20
1 multiplexer 2 using
c) Describe 6
2 the working of a serial binary adder. 1
2 0 / 0
/ Simplify the Boolean expression F(A, B, C) =-A'20B' C + A'BC + ABC using a
d) Explain
0 1
e)
/ f) Design 1 gates and extend the concept to
2 0 Karnaugh map.
2 9
1- a 1-bit magnitude comparator using logic
29 g)
a 2-bit comparator.
Describe the synthesis of synchronous sequential circuits with an example.
h) Explain flip-flop and design a modulo-N ring counter.
i) Differentiate between decoder and demultiplexer. Under what circumstance a
decoder can be converted into demultiplexer?
j) If (1235)x = (3033)y, where x and y indicate the bases of the corresponding
numbers, then find the value of x and y.
- 2 3
6-
k) Explain the difference between static and dynamic hazards and describe design
techniques to eliminate them
0 2
l)
/ 2
A finite state machine is designed using d flip flops. Explain how state assignment
1
impacts power consumption and switching activity in the circuit.
0 /0
-2 Part-III
91
Only Long Answer Type Questions (Answer Any Two out of Four)
2
Q3 a) Design of 16×1 MUX using 4×1 MUX. (8+8)
23 for a 4-bit data word using logic gates.
b) Convert the SR Flipflop to JK Flipflop.
Q4 - -
6line decoder using AND and NOT gates. Draw the gate-
a) Design a parity bit generator (6+10)
0
b) Implement a 3-to-8 2
/2
level realization.
1
0 /0a 4-bit sequential adder using shift registers and flip-flops. Explain
-2the gate-level operation.
Q5 a) Design (8+8)
1 a modulo-6 synchronous counter using T23
29 b) Design - - flip-flops. Derive
excitation equations and draw the complete gate-level
2 6 circuit.
/ 2 0 design using ASM for
Q6
c) Weighing machine.
/ 0 1
Explain Algorithmic State Machines and discuss system (8+8)
d) Binary multiplier.
- 2 0
9 1
2
- 2 3
2 6-
/ 2 0
/ 0 1
- 2 0
9 1 2 3
23 6 - -
-- 2 0 2
2 6 1 / 2
/ 2 0 0 / 0
/ 0 1 1 - 2
2 0 2 9
1-
29