Shift Registers

Serial-in/Serial out Shift Register

Shift registers are available in IC form or can be constructed
from discrete flip-flops as is shown here with a five-bit
serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-flop.
For example, a 1 is shown as it moves across.

1 1 1 1 1

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Slide 4
 Shift Registers

Serial-in/Serial out
Shift Register

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Slide 5
 Shift Registers

Serial in/Parallel out Shift Register

An application of shift registers is conversion of
serial data to parallel form.

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Slide 6
 Shift Registers

Serial in/Parallel out Shift Register

Floyd Copyright ©2006 by Pearson Education, Inc.

Digital Fundamentals, 9/e Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 7
 Shift Registers

Parallel in/Serial out Shift Register

An application of shift registers is conversion of
parallel data to serial form.

Floyd Copyright ©2006 by Pearson Education, Inc.

Digital Fundamentals, 9/e Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 8
 Shift Registers

Parallel in/Serial out Shift Register

Floyd Copyright ©2006 by Pearson Education, Inc.

Digital Fundamentals, 9/e Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 9
 Shift Registers

Parallel in/Parallel out Shift Register

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Digital Fundamentals, 9/e Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 10
 Shift Registers

Bidirectional Shift Register

Bidirectional shift registers can shift
the data in either direction using a
RIGHT/LEFT input.

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Slide 11
 Universal Shift Register
If the register has both shifts and parallel load
capabilities, it is referred to as a universal shift register.

• A clear control to clear the register to 0.

• A clock input to synchronize the operations.
• A shift-right control to enable the shift right operation and
the serial input and output lines associated with the shift
right.
• A shift-left control to enable the shift left operation and the
serial input and output lines associated with the shift left.
• A parallel-load control to enable a parallel transfer and the n
input lines associated with the parallel transfer.
• n parallel output lines
• A control state that leaves the information in the register
unchanged in the presence of the clock.
Universal Shift Register
Universal Shift Register (cont.)
Types of counter are

1. Asynchronous Also known as ripple counter

The first flip-flop is driven by external clock while the successive flip-flops by the output of
preceding flip-flop

2. Synchronous: All flip-flops are simultaneously driven by common clock

Asynchronous counter

 Also known as ripple counter. Ripple counters are the simplest type of binary counters
because they require the fewest components to produce a given counting operation.

 Each FF output drives the CLK input of the next FF.

 FFs do not change states in exact synchronism with the applied clock pulses.

 There is delay between the responses of successive FFs.

 It is also often referred to as a ripple counter due to the way the FFs respond one after another
in a kind of rippling effect.

Ripple Counter/Asynchronous Counter

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an
external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.
Asynchronous counters are also called ripple-counters because of the way the clock pulse
ripples it way through the flip-flops.

The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used. For a
4-bit counter, the range of the count is 0000 to 1111 (24-1). A counter may count up or count
down or count up and down depending on the input control.

Binary Ripple Counter

A binary ripple counter consists of a series connection of complementing flip-flops (T or JK

type), with the output of each flip-flop connected to the CP input of the next higher-order flip-
flop.

UCA15E51 DLF UNIT-4 Page 11

The diagram of a 4-bit binary ripple counter is shown in Fig. All J and K inputs are equal to l.

The small circle in the CP input indicates that the flip-flop complements during a negative-going
transition or when the output to which it is connected goes from 1 to 0.

To understand the operation of the binary counter, refer to its count sequence given in Table 7 -
4. It is obvious that the lowest-order bit A1 must be complemented with each count pulse.

Every time A1 goes from 1 to 0, it complements A2.

Every time A2 goes from 1 to 0, it complements A3, and so on.

For example, take the transition from count 0111 to 1000.

The arrows in the table emphasize the transitions in this case.

A1 is complemented with the count pulse. S

ince A1 goes from 1 to 0, it triggers A2, and complements it.

As a result, A3, goes from 1 to 0, which in turn complements A3.

A3 now goes from 1 to 0, which complements A4

TABLE

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UCA15E51 DLF UNIT-4 Page 13
 SYNCHRONOUS COUNTERS

Synchronous counters are distinguished from ripple counters in that clock pulses are
applied to the CP inputs of all flip-flops. The common pulse triggers all the flip-flops
simultaneously, rather than one at a time in succession as in a ripple counter

Binary Counter

The design of synchronous binary counters is so simple that there is no need to go through a
rigorous sequential-logic design process.

In a synchronous binary counter, the flip-flop in the lowest-order position is complemented with
every pulse. This means that its J and K inputs must be maintained at logic-1.

A flip-flop in any other position is complemented with a pulse provided all the bits in the lower-
order positions are equal to I, because the lower-order bits (when all 1's) will change to 0's on the
next count pulse. The binary count dictates that the next higher-order bit be complemented. For
example, if the present state of a 4-bit counter is A4A3A2A1 = 0011, the next count will be 0100.

UCA15E51 DLF UNIT-4 Page 14

A1 is always complemented. A2 is complemented because the present state of A1 = 1. A3 is
complemented because the present state of A2A1=11. But A4 is not complemented because the
present state of A3A2A1 = 011, which does not give an all 1's condition.

Synchronous binary counters have a regular pattern and can easily be constructed with
complementing flip-flops and gates. The regular pattern can be clearly seen from the 4-bit
counter depicted in Fig. 7-17. The CP terminals of all flip-flops are connected to a common
clock-pulse source. The first stage A1 has its J and K equal to 1 if the counter is enabled. The
other J and K inputs are equal to 1 if all previous low-order bits are equal to 1 and the count is
enabled. The chain of AND gates generates the required logic for the J and K inputs in each
stage. The counter can be extended to any number of stages, with each stage having an additional
flip-flop and an AND gate that gives an output of 1 if all previous flip-flop outputs are 1's.

UCA15E51 DLF UNIT-4 Page 15

Binary Up-Down Counter

BCD Counter

In a synchronous count-down binary counter, the flip-flop in the lowest-order position is

complemented with every pulse. A flip-flop in any other position is complemented with a pulse
provided all the lower-order bits are equal to 0. For example, if the present state of a 4-bit count-
down binary counter is A4A3A2A1 = 1100, the next count will be l0ll. A1 is always
complemented. A, is complemented because the present state of A1 = 0. A, is complemented
because the present state of A2A1 = 00. But A3 is not complemented because the present state of
A3A2A1 = 100, which is not an all-0's condition.

A count-down binary counter can be constructed as shown in Fig. 7-17, except that the inputs to
the AND gates must come from the complement outputs Q' and not from the normal outputs Q of
the previous flip-flops. The two operations can be combined in one circuit. A binary counter
capable of counting either up or down is shown in Fig. 7-18. The T flip-flops employed in this
circuit may be considered as JK flip-flops with the J and K terminals tied together. When the up
input control is 1, the circuit counts up, since the T inputs receive their signals from the values of
the previous normal outputs of the flip-flops. When the down input control is 1 and the up input
is 0, the circuit counts down, since the complemented outputs of the previous flip-flops are
applied to the T inputs. When the up and down inputs are both 0, the circuit does not change
state but remains in the same count. When the up and down inputs are both 1, the circuit counts
up. This ensures that only one operation is performed at any given time.

UCA15E51 DLF UNIT-4 Page 16

UCA15E51 DLF UNIT-4 Page 17
 BCD Counter

A BCD counter counts in binary-coded decimal from 0000 to 1001 and back to 0000. Because of
the return to 0 after a count of 9, a BCD counter does not have a regular pattern as in a straight
binary count. The excitation table of a BCD counter is given in Table 7-5. The excitation for the
T flip-flops is obtained from the present and next state conditions. An output y is also shown in
the table. This output is equal to I when the counter present state is 1001. In this way, y can
enable the count of the next-higher-order decade while the same pulse switches the present
decade from 1001 to 0000.

The flip-flop input functions from the excitation table can be simplified by means of maps. The
unused states for minterms 10 to 15 are taken as don't-care terms. The simplified functions are

UCA15E51 DLF UNIT-4 Page 18