Programmable Logic Devices
• General purpose chip for implementing circuits
• Can be customized using programmable switches
• Main types of PLDs
• PLA
• PAL
• CPLD
• FPGA
• Custom chips: Designed by standard cells & sea of
gates
Programmable Logic Devices
Programmable Logic Devices
• The purpose of a PLD device is to permit elaborate digital
logic designs to be implemented by the user in a single
device.
• Can be erased electrically and reprogrammed with a new
design, making them very well suited for academic and
prototyping
• Types of Programmable Logic Devices
• SPLDs (Simple Programmable Logic Devices)
• ROM (Read-Only Memory)
• PLA (Programmable Logic Array)
• PAL (Programmable Array Logic)
• GAL (Generic Array Logic)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field-Programmable Gate Array)
General structure of PLDs
General structure of PLDs
The differences between the first three categories are these:
• In a ROM, the input connection matrix is hardwired. The user can
modify the output connection matrix.
• In a PAL/GAL the output connection matrix is hardwired. The user
can modify the input connection matrix.
• In a PLA the user can modify both the input connection matrix and
the output connection matrix.
Programming by blowing fuses
Programming by blowing fuses
Gate Level Version of PLA
Function Implementation in PLA
f1 = x1x2 + x1x3‘ + x1'x2'x3 & f2 = x1x2 + x1'x2'x3 +x1x3
Limitations of PLAs
• PLAs come in various sizes
• Typical size is 16 inputs, 32 product terms, 8 outputs
• Each AND gate has large fan-in and this limits the
number of inputs that can be provided in a PLA
• 16 inputs and 2^16 possible input combinations; But
only 32 permitted (since 32 AND gates) in a typical PLA
• 32 AND terms permitted large fan-in for OR gates as well
• This makes PLAs slower and slightly more expensive than
some alternative devices
• 8 outputs could have shared min terms, but not
required
Design for PLA
Implement the following functions using PLA
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Design for PAL
Implement the following functions using PAL
Programmable Array Logic (PAL)
• Also used to implement circuits in SOP form
• The connections in the AND plane are programmable
• The connections in the OR plane are NOT programmable
Programmable Array Logic (PAL)
Implement the following functions in PAL
f1 = x1x2x3'+x1'x2x3
f2 = x1'x2'+x1x2x3
Programmable Array Logic (PAL)
Implement the following functions in PAL
Comparison of PALs and PLAs
• PALs have the same limitations as PLAs
(small number of allowed AND terms) plus
they have a fixed OR plane less flexibility
than PLAs
• PALs are simpler to manufacture, cheaper,
and faster (better performance)
• PALs also often have extra circuitry
connected to the output of each OR gate
FPGA AND CPLD
• FPGA - Field-Programmable Gate Array.
• CPLD - Complex Programmable Logic Device
• FPGA and CPLD is an advance PLD.
• Support thousands of gate where as PLD only
support hundreds of gates.
CPLD
• CPLDs contain multiple circuit blocks on a
single chip
• Each block is like a PAL: PAL-like block
• Connections are provided between PAL-like
blocks via an interconnection network that is
programmable
• Each block is connected to an I/O block as
well
Structure of a CPLD
Programming a CPLD
• CPLDs have many pins – large ones have > 200
• Removal of CPLD from a PCB is difficult without breaking the pins
• Use ISP (in system programming) to program the CPLD
• JTAG (Joint Test Action Group) port used to connect the CPLD to a
computer
FPGA
• SPLDs and CPLDs are relatively small and useful for
simple logic devices Up to about 20000 gates
• Field Programmable Gate Arrays (FPGA) can handle
larger circuits
• No AND/OR planes
• Provide logic blocks, I/O blocks, and interconnection
wires and switches
• Logic blocks provide functionality
• Interconnection switches allow logic blocks to be
connected to each other and to the I/O pins
Structure of an FPGA
Simplified Structure of FPGA
LUTs
• Logic blocks are implemented using a lookup table (LUT)
• Small number of inputs and one output
• Contains storage cells that can be loaded with the
desired values
• A 2 input LUT uses 3 MUXes to implement any desired
function of 2 variables
Programming an FPGA
• ISP(In System Programming) method is used
• LUTs contain volatile storage cells
• None of the other PLD technologies are volatile
• FPGA storage cells are loaded via a PROM when
power is first applied
• The UP2 Education Board by Altera contains a
JTAG port, a MAX 7000 CPLD, and a FLEX 10K FPGA
• The MAX 7000 CPLD chip is EPM7128SLC84-7
Programming an FPGA
FPGA Advantages
• Long time availability
• Can be updated and upgraded at your customer's site
• Extremely short time to market
• Fast and efficient systems
• Performance gain for software applications
• Real time applications
• Massively parallel data processing
Comparison of FPGA and CPLD