1.

Numerical: Basic Setup Slack Calculation

Question:
Clock period = 1.2 ns, Launch latency = 0.1 ns, Capture latency = 0.25 ns, Data delay = 0.7 ns, Setup = 0.1 ns.

Formula:

Required Time = Tclk + Capture Latency − Setup

Arrival Time = Launch Latency + Data Delay
Slack = Required Time − Arrival Time

Solution: Required Time = 1.2 + 0.25 − 0.1 = 1.35 ns

Arrival Time = 0.1 + 0.7 = 0.8 ns
Slack = 1.35 − 0.8 = +0.55 ns
Hence, setup timing is met.

2. Numerical: Basic Hold Slack Calculation

Question:
Hold = 0.05 ns, Launch latency = 0.15 ns, Capture latency = 0.05 ns, Min delay = 0.12 ns.

Formula:

Arrival Time = Launch Latency + Min Delay

Required Time = Capture Latency + Hold
Slack = Arrival − Required

Solution: Arrival Time = 0.15 + 0.12 = 0.27 ns

Required Time = 0.05 + 0.05 = 0.10 ns
Slack = 0.27 − 0.10 = +0.17 ns
Hence, hold timing is safe.

3. Numerical: Setup with Positive Skew

Question:
Clock period = 1 ns, Skew = +0.08 ns, Data delay = 0.7 ns, Setup = 0.1 ns.

Formula:

1
 Effective Period = Tclk + Skew
Required Time = Effective Period − Setup
Slack = Required − Data Delay

Solution: Effective Period = 1 + 0.08 = 1.08 ns

Required Time = 1.08 − 0.1 = 0.98 ns
Slack = 0.98 − 0.7 = +0.28 ns
Therefore, positive skew helps setup.

4. Numerical: Setup with Clock Uncertainty

Question:
Clock = 1 ns, Uncertainty = 0.12 ns, Data delay = 0.75 ns, Setup = 0.08 ns.

Formula:

Required Time = Tclk − Setup − Uncertainty

Slack = Required − Data Delay

Solution: Required Time = 1 − 0.08 − 0.12 = 0.80 ns

Slack = 0.80 − 0.75 = +0.05 ns
So the path is near critical.

5. Numerical: Multicycle Path Setup

Question:
Clock = 1 ns, Multicycle = 3, Setup = 0.1 ns, Data delay = 2.5 ns.

Formula:

Effective Period = Multicycle × Tclk

Required Time = Effective Period − Setup
Slack = Required − Data Delay

Solution: Effective Period = 3 × 1 = 3 ns

Required Time = 3 − 0.1 = 2.9 ns
Slack = 2.9 − 2.5 = +0.4 ns
Hence, multicycle relaxes setup timing.

2
6. Numerical: CPPR Slack Improvement
Question:
Common clock path = 0.2 ns, Slack before CPPR = −0.1 ns.

Formula:

New Slack = Old Slack + Common Path Delay

Solution: New Slack = −0.1 + 0.2 = +0.1 ns

Therefore, CPPR removes common pessimism.

7. Numerical: Frequency from Slack

Question:
Clock period = 1 ns, Slack = 0.15 ns.

Formula:

New Period = Old Period − Slack

Frequency = 1 / Period

Solution: New Period = 1 − 0.15 = 0.85 ns

Frequency = 1 / 0.85 = 1.176 GHz
So frequency headroom is available.

8. Numerical: Hold Fix using Buffer

Question:
Min delay = 0.08 ns, Required hold = 0.18 ns.

Formula:

Hold Slack = Arrival − Required

Extra Delay = Required − Arrival

Solution: Arrival = 0.08 ns

Required = 0.18 ns

3
Hold Slack = 0.08 − 0.18 = −0.10 ns
Extra Delay Needed = 0.10 ns
Thus, insert buffer of 0.10 ns.

9. Numerical: OCV Max Derate Impact

Question:
Path delay = 0.9 ns, OCV derate = 1.08.

Formula:

Adjusted Delay = Path Delay × Derate

Solution: Adjusted Delay = 0.9 × 1.08 = 0.972 ns

OCV increases pessimism for setup paths.

10. Numerical: Jitter Impact on Setup

Question:
Clock = 1 ns, Jitter = 0.06 ns, Setup = 0.1 ns, Data = 0.78 ns.

Formula:

Required Time = Tclk − Jitter − Setup

Slack = Required − Data Delay

Solution: Required Time = 1 − 0.06 − 0.1 = 0.84 ns

Slack = 0.84 − 0.78 = +0.06 ns
Hence, jitter reduces setup margin.

11. Numerical: Hold Violation Fix Using Buffer

Question: Min data delay = 0.08 ns, Required hold margin = 0.18 ns.

Formula:

4
 Hold Slack = Arrival Time − Required Time
Required Time = Hold Requirement
Arrival Time = Min Data Delay

Solution: Arrival Time = 0.08 ns

Required Time = 0.18 ns
Hold Slack = 0.08 − 0.18 = −0.10 ns
Extra delay needed = 0.10 ns
Therefore, insert a buffer of at least 0.10 ns to fix hold.

12. Numerical: Setup with Negative Skew

Question: Clock period = 1 ns, Skew = −0.12 ns, Data delay = 0.72 ns, Setup = 0.08 ns.

Formula:

Effective Period = Tclk + Skew

Required Time = Effective Period − Setup
Slack = Required Time − Data Delay

Solution: Effective Period = 1 − 0.12 = 0.88 ns

Required Time = 0.88 − 0.08 = 0.80 ns
Slack = 0.80 − 0.72 = +0.08 ns
Hence, timing is safe with small margin.

13. Numerical: AOCV Depth Effect

Question: Base delay = 1.0 ns, AOCV derate = 0.92.

Formula:

Adjusted Delay = Base Delay × Derate

Solution: Adjusted Delay = 1.0 × 0.92 = 0.92 ns

So, AOCV reduces pessimism and gives a realistic delay of 0.92 ns.

5
14. Numerical: Crosstalk Impact
Question: Victim delay = 0.60 ns, SI delta = +0.09 ns.

Formula:

Effective Delay = Victim Delay + SI Delta

Solution: Effective Delay = 0.60 + 0.09 = 0.69 ns

Therefore, crosstalk increases delay to 0.69 ns and hurts setup.

15. Numerical: Max Frequency from Setup Slack

Question: Clock = 1.5 ns, Setup slack = 0.3 ns.

Formula:

New Period = Old Period − Slack

Frequency = 1 / Period

Solution: New Period = 1.5 − 0.3 = 1.2 ns

Frequency = 1 / 1.2 = 0.833 GHz
So maximum achievable frequency is 833 MHz.

16. Numerical: Recovery Check

Question: Recovery = 0.12 ns, Capture latency = 0.2 ns, Async deassert arrives at 0.25 ns.

Formula:

Required Time = Capture Latency + Recovery

Slack = Required Time − Arrival Time

Solution: Required Time = 0.2 + 0.12 = 0.32 ns

Arrival Time = 0.25 ns
Slack = 0.32 − 0.25 = +0.07 ns
Hence, recovery timing is met.

6
17. Numerical: Removal Check
Question: Removal = 0.1 ns, Capture latency = 0.3 ns, Async assert arrives at 0.38 ns.

Formula:

Required Time = Capture Latency + Removal

Slack = Required Time − Arrival Time

Solution: Required Time = 0.3 + 0.1 = 0.4 ns

Arrival Time = 0.38 ns
Slack = 0.4 − 0.38 = +0.02 ns
Therefore, removal check passes marginally.

18. Numerical: Path Margin After Uncertainty

Question: Clock = 1 ns, Uncertainty = 0.15 ns, Setup = 0.1 ns, Data = 0.7 ns.

Formula:

Required Time = Tclk − Uncertainty − Setup

Slack = Required Time − Data Delay

Solution: Required Time = 1 − 0.15 − 0.1 = 0.75 ns

Slack = 0.75 − 0.7 = +0.05 ns
So the path is near‑critical.

19. Numerical: Hold with Skew

Question: Launch latency = 0.25 ns, Capture latency = 0.1 ns, Min delay = 0.12 ns, Hold = 0.05 ns.

Formula:

Arrival Time = Launch Latency + Min Delay

Required Time = Capture Latency + Hold
Slack = Arrival − Required

Solution: Arrival Time = 0.25 + 0.12 = 0.37 ns

Required Time = 0.1 + 0.05 = 0.15 ns

7
Slack = 0.37 − 0.15 = +0.22 ns
Hence, hold timing is safe.

20. Numerical: CPPR Improvement

Question: Common path = 0.18 ns, Old slack = −0.05 ns.

Formula:

New Slack = Old Slack + Common Path Delay

Solution: New Slack = −0.05 + 0.18 = +0.13 ns

So CPPR converts violation into positive slack.

21. Numerical: Setup with OCV + Uncertainty

Question:
Clock = 1 ns, Setup = 0.08 ns, Uncertainty = 0.1 ns, Data delay = 0.75 ns, OCV derate = 1.06.

Formula:

Derated Delay = Data Delay × OCV

Required Time = Tclk − Setup − Uncertainty
Slack = Required − Derated Delay

Solution: Derated Delay = 0.75 × 1.06 = 0.795 ns

Required Time = 1 − 0.08 − 0.1 = 0.82 ns
Slack = 0.82 − 0.795 = +0.025 ns
Hence, path is barely safe.

22. Numerical: Hold with Min OCV

Question:
Min delay = 0.22 ns, Hold = 0.06 ns, Launch latency = 0.12 ns, Capture latency = 0.08 ns, Min derate = 0.92.

Formula:

8
 Derated Delay = Min Delay × Derate
Arrival = Launch + Derated Delay
Required = Capture + Hold
Slack = Arrival − Required

Solution: Derated Delay = 0.22 × 0.92 = 0.2024 ns

Arrival = 0.12 + 0.2024 = 0.3224 ns
Required = 0.08 + 0.06 = 0.14 ns
Slack = 0.3224 − 0.14 = +0.1824 ns
Thus, hold timing is safe.

23. Numerical: Negative Skew Impact on Hold

Question:
Launch latency = 0.1 ns, Capture latency = 0.25 ns, Skew = −0.15 ns, Min delay = 0.12 ns, Hold = 0.05 ns.

Formula:

Effective Capture = Capture + Skew

Arrival = Launch + Min Delay
Required = Effective Capture + Hold
Slack = Arrival − Required

Solution: Effective Capture = 0.25 − 0.15 = 0.10 ns

Arrival = 0.1 + 0.12 = 0.22 ns
Required = 0.10 + 0.05 = 0.15 ns
Slack = 0.22 − 0.15 = +0.07 ns
Hence, negative skew helps hold.

24. Numerical: Crosstalk Aware Setup

Question:
Victim delay = 0.68 ns, SI delta = +0.1 ns, Clock = 1 ns, Setup = 0.1 ns.

Formula:

Effective Delay = Victim + SI

Required Time = Tclk − Setup
Slack = Required − Effective Delay

9
Solution: Effective Delay = 0.68 + 0.1 = 0.78 ns
Required Time = 1 − 0.1 = 0.9 ns
Slack = 0.9 − 0.78 = +0.12 ns
So SI still keeps path safe.

25. Numerical: Multicycle Hold Adjustment

Question:
Clock = 1 ns, Multicycle setup = 3, Multicycle hold = 2, Hold = 0.05 ns, Launch latency = 0.12 ns, Capture
latency = 0.1 ns, Min delay = 0.15 ns.

Formula:

Arrival = Launch + Min Delay

Required = Capture + Hold + (Multicycle Hold − 1) × Tclk
Slack = Arrival − Required

Solution: Arrival = 0.12 + 0.15 = 0.27 ns

Required = 0.1 + 0.05 + (2 − 1) × 1 = 1.15 ns
Slack = 0.27 − 1.15 = −0.88 ns
Thus, multicycle hold needs correction.

26. Numerical: CPPR with Two Paths

Question:
Common clock delay = 0.22 ns, Slack before CPPR = −0.12 ns.

Formula:

New Slack = Old Slack + Common Delay

Solution: New Slack = −0.12 + 0.22 = +0.10 ns

Therefore, CPPR resolves the violation.

27. Numerical: Pipeline Improvement

Question:
Original path delay = 2.4 ns, pipelined into 3 stages.

10
Formula:

Stage Delay = Total Delay / Number of Stages

Solution: Stage Delay = 2.4 / 3 = 0.8 ns

Thus, pipelining improves maximum frequency.

28. Numerical: Max Throughput from Critical Path

Question:
Critical delay = 0.92 ns.

Formula:

Period = Critical Delay

Frequency = 1 / Period

Solution: Period = 0.92 ns

Frequency = 1 / 0.92 = 1.087 GHz
So achievable throughput is 1.087 GHz.

29. Numerical: Recovery Timing Violation

Question:
Recovery = 0.12 ns, Capture latency = 0.25 ns, Async deassert arrival = 0.42 ns.

Formula:

Required = Capture + Recovery

Slack = Required − Arrival

Solution: Required = 0.25 + 0.12 = 0.37 ns

Slack = 0.37 − 0.42 = −0.05 ns
Hence, recovery violation exists.

11
30. Numerical: Removal Timing Check
Question:
Removal = 0.1 ns, Capture latency = 0.3 ns, Async assert arrival = 0.36 ns.

Formula:

Required = Capture + Removal

Slack = Required − Arrival

Solution: Required = 0.3 + 0.1 = 0.4 ns

Slack = 0.4 − 0.36 = +0.04 ns
Therefore, removal timing is safe.

12
Advanced Static Timing Analysis (STA) Interview
Questions with Answers
This document contains advanced-level STA interview questions with detailed 3–4 line answers useful for
VLSI Physical Design, Timing Closure, and Signoff roles.

1. What is Static Timing Analysis (STA)?

Answer:
Static Timing Analysis is a vectorless method to verify timing performance of a digital design. It checks all
possible timing paths without simulation by computing arrival and required times using timing libraries,
constraints, and clock definitions. STA validates setup, hold, recovery, removal, and clock-gating checks
under worst PVT conditions. It is essential for timing closure before tapeout.

2. Explain setup and hold checks.

Answer:
Setup check ensures that data arrives at the capture flip-flop at least a setup time before the active clock
edge. It is mainly analyzed at slow process corners. Hold check ensures data remains stable after the clock
edge for the required hold time and is analyzed at fast corners. Both checks guarantee reliable sampling of
data.

3. What is slack and how is it calculated?

Answer:
Slack is the margin by which a timing path meets or violates timing. It is calculated as Slack = Required Time
− Arrival Time. If slack is positive, the path meets timing; if negative, it fails. Slack helps identify critical paths
and prioritize timing fixes.

4. What is clock skew and its impact?

Answer:
Clock skew is the difference in clock arrival times between launch and capture registers. Positive skew
relaxes setup but worsens hold, while negative skew helps hold but hurts setup. Excessive skew can create
timing violations and instability. CTS aims to balance skew for optimal timing closure.

1
5. Difference between clock latency and clock uncertainty.
Answer:
Clock latency is the actual delay of the clock from the source to a register through the clock tree. It includes
insertion and network delays. Clock uncertainty represents margin for jitter, noise, and modeling errors. It
reduces available time for data paths to ensure safe operation.

6. What are OCV, AOCV and POCV?

Answer:
OCV applies fixed derate factors to model on-chip process variation, making timing pessimistic. AOCV
improves this by using depth-based derates depending on the number of cells in a path. POCV further
refines accuracy by applying per-cell statistical variation, reducing unnecessary pessimism in signoff STA.

7. What is CRPR?
Answer:
Clock Reconvergence Pessimism Removal removes extra pessimism when launch and capture clocks share
common clock paths. Without CRPR, variations on common segments are counted twice. CRPR subtracts
the common delay portion, giving more realistic slack values and improving timing closure accuracy.

8. What is useful skew?

Answer:
Useful skew intentionally shifts clock arrival times to help critical paths meet timing. By delaying or
advancing capture clocks, extra time can be provided for setup or hold. CTS tools insert buffers to create
this skew in a controlled way. It is widely used for timing optimization.

9. Difference between max and min paths.

Answer:
Max paths are analyzed for setup checks where worst-case long delays are considered. Min paths are
analyzed for hold checks where the fastest possible data arrival is evaluated. Different corners, derates, and
constraints are applied for each. Both analyses are required for complete timing verification.

10. What is multicycle path?

Answer:
A multicycle path allows data to take more than one clock cycle to propagate between registers. Designers

2
apply set_multicycle_path constraints to relax setup or hold requirements. It is used when logic is
intentionally slow but functionally correct. Proper constraints prevent false timing violations.

11. What is false path?

Answer:
A false path is a timing path that never becomes active in real functional operation. STA tools are instructed
to ignore these paths using set_false_path . This avoids wasting effort fixing non-functional violations.
Care must be taken to not mask real critical paths.

12. What is clock gating check?

Answer:
Clock gating checks ensure the enable signal of a clock-gating cell is stable around the clock edge. This
prevents glitches on the gated clock. STA checks setup and hold of enable relative to the clock. Failing this
check can cause functional and power issues.

13. What is recovery and removal check?

Answer:
Recovery and removal checks are applied to asynchronous reset or set signals. Recovery ensures reset is
deasserted sufficiently before the active clock edge. Removal ensures reset remains stable after the clock
edge. These checks avoid metastability and incorrect state capture.

14. What is on-chip variation pessimism?

Answer:
On-chip variation accounts for delay differences within the same die due to process, voltage, and
temperature variations. Traditional methods add pessimism to be safe. Advanced techniques like AOCV and
POCV reduce over-pessimism while maintaining signoff accuracy. This improves achievable frequency.

15. What are different timing corners?

Answer:
Timing corners represent combinations of process, voltage, and temperature. SS corner models worst-case
slow delays for setup, while FF models fastest delays for hold. TT represents nominal behavior. Modern STA
uses MMMC analysis to verify timing across all important corners.

3
16. How do you fix setup violations?
Answer:
Setup violations are fixed by reducing data path delay. This can be done by upsizing cells, buffering critical
nets, improving placement, and reducing logic depth. Useful skew and clock tree optimization also help. The
goal is to make data arrive earlier at the capture register.

17. How do you fix hold violations?

Answer:
Hold violations are fixed by increasing the minimum delay of the data path. Designers insert delay buffers,
downsize fast cells, or add routing detours. Clock skew can also be adjusted. The objective is to prevent data
from changing too quickly after the clock edge.

18. What is timing derate?

Answer:
Timing derates scale cell and net delays to model variation effects. Early derates are applied for hold
analysis and late derates for setup analysis. They account for PVT uncertainty. Derates ensure STA remains
safe under manufacturing and environmental variations.

19. Difference between propagated and ideal clock.

Answer:
An ideal clock has zero delay and no skew and is mainly used before CTS. A propagated clock includes real
clock tree delays, skew, and variation. Post-CTS STA always uses propagated clocks. This provides realistic
timing analysis for signoff.

20. What is signoff STA?

Answer:
Signoff STA is the final timing verification before tapeout. It uses extracted parasitics, MMMC corners,
AOCV/POCV, SI effects, and CRPR. All timing checks must pass with clean slack. It ensures the chip will meet
frequency and reliability requirements in silicon.

Bonus Topics to Add in PDF

• SI-aware STA
• CPPR with POCV

4
 • Clock domain crossing timing
• ECO timing closure
• Path-based analysis
• MMMC setup

21. What is MMMC in STA?

Answer:
MMMC stands for Multi-Mode Multi-Corner analysis. It allows STA to analyze different operating modes and
PVT corners in a single run. Each mode may have different clocks and constraints, while corners model
process, voltage, and temperature variations. MMMC ensures timing is safe across all real operating
conditions.

22. What is path-based analysis (PBA)?

Answer:
Path-Based Analysis computes timing using the exact path delays instead of independent segment
pessimism. Unlike graph-based analysis, PBA reduces unnecessary pessimism on critical paths. It provides
more accurate slack values. PBA is mainly used during signoff for tight timing closure.

23. What is crosstalk in STA?

Answer:
Crosstalk occurs due to coupling capacitance between adjacent nets, causing delay changes and noise. It
can slow down or speed up victim nets depending on aggressor switching. SI-aware STA accounts for this
effect. Ignoring crosstalk can lead to silicon timing failures.

24. What is delta delay?

Answer:
Delta delay is the additional delay added due to signal integrity effects such as crosstalk and noise. It
modifies the original net delay during SI analysis. STA tools compute delta delays dynamically based on
aggressor behavior. This helps in more realistic timing estimation.

25. Difference between ideal, propagated and generated clocks.

Answer:
Ideal clocks have no delay and no skew and are used pre-CTS. Propagated clocks include real clock tree

5
delays after CTS. Generated clocks are derived from master clocks using dividers, muxes, or gates. STA must
correctly define generated clocks for proper timing checks.

26. What is clock domain crossing (CDC) timing?

Answer:
CDC timing deals with paths between different clock domains. Since clocks are asynchronous, normal
setup/hold checks are not valid. Designers use synchronizers and false or asynchronous constraints. Proper
CDC timing avoids metastability and functional failures.

27. What is latch-based timing analysis?

Answer:
Latch-based STA considers level-sensitive latches instead of edge-triggered flops. Timing allows time
borrowing between stages. STA must account for transparency windows and closing edges. This makes
analysis more complex than flip-flop based timing.

28. What is ECO in timing closure?

Answer:
ECO stands for Engineering Change Order used to fix late-stage timing violations. Instead of full re-place
and route, small cell swaps, buffer insertions, or net changes are applied. ECOs help achieve timing closure
quickly. They minimize design disturbance before tapeout.

29. What is useful skew vs natural skew?

Answer:
Natural skew is the unintentional skew caused by routing and CTS imbalance. Useful skew is intentionally
introduced to improve setup or hold margins. CTS tools optimize skew for critical paths. Controlled skew
improves performance without violating constraints.

30. What is clock reconvergence in STA?

Answer:
Clock reconvergence happens when clock paths diverge and later meet again at different registers.
Variations on common segments can cause pessimism. Techniques like CRPR remove double-counting.
Proper handling of reconvergence improves accurate slack reporting.

6
31. What is clock uncertainty and how is it modeled?
Answer:
Clock uncertainty represents margin added to account for clock jitter, skew, and modeling inaccuracy. It
reduces the available time for setup and increases required time for hold. STA tools apply uncertainty to
both launch and capture clocks. This ensures timing remains safe under real silicon clock variations.

32. What is inter-clock uncertainty?

Answer:
Inter-clock uncertainty is applied between two different clocks to account for phase noise and alignment
errors. It is important in multi-clock designs where clocks interact. It limits optimistic assumptions between
domains. Proper inter-clock uncertainty avoids unexpected violations in silicon.

33. What is max transition and max capacitance in STA?

Answer:
Max transition limits the slew rate of signals to ensure signal integrity and cell reliability. Max capacitance
restricts the load a driver can see. Violating these can cause large delays, noise, and functional issues. STA
checks these along with setup and hold for signoff quality.

34. What is max fanout and why is it important?

Answer:
Max fanout limits the number of loads driven by a single cell. High fanout increases delay, power, and
transition time. STA and synthesis tools insert buffers to control fanout. Maintaining fanout improves
timing, noise, and overall performance.

35. What is clock tree insertion delay?

Answer:
Insertion delay is the time taken by the clock to travel from the clock source to a register clock pin. It
includes buffer and routing delays in the clock tree. Large insertion delay reduces timing margin. CTS
optimization tries to balance insertion delay across sinks.

36. What is late mode and early mode analysis?

Answer:
Late mode models worst-case slow delays for setup analysis. Early mode models fastest delays for hold

7
analysis. Different libraries and derates are used for each. Both modes ensure the design is safe under
extreme PVT conditions.

37. What is timing exception priority?

Answer:
When multiple constraints apply to a path, STA follows a priority order. False paths override multicycle
paths, and multicycle overrides default single-cycle checks. Proper priority avoids incorrect analysis. Misuse
can hide real timing violations.

38. What is case analysis in STA?

Answer:
Case analysis fixes control signals to constant values during timing analysis. It removes impossible paths
and improves accuracy. Designers use it for mode selection signals and test enables. This reduces
pessimism and unnecessary timing effort.

39. What is pessimism in STA and how is it reduced?

Answer:
Pessimism is extra margin added to ensure safe operation under variation. While needed, too much
pessimism limits performance. Techniques like CRPR, AOCV, POCV, and PBA reduce over-pessimism. This
helps achieve higher frequency without risking silicon failure.

40. What is signoff checklist in STA?

Answer:
Signoff STA ensures clean setup, hold, recovery, removal, clock-gating, max transition, max capacitance, and
noise checks. It verifies all MMMC corners with extracted parasitics and SI enabled. ECOs are closed and
reports are reviewed. Only then is the design ready for tapeout.

42. What is a generated clock and why is it important?

Answer:
A generated clock is derived from a master clock using dividers, muxes, or logic gates. STA must understand
its frequency, phase, and relationship to the source clock. Proper definition ensures correct setup/hold
checks across derived domains. Missing generated clocks often cause false violations.

8
43. What is clock phase shift in STA?
Answer:
Clock phase shift represents intentional offset between related clocks. It is common in PLLs and divided
clocks. STA uses phase information to compute launch and capture edges accurately. Incorrect phase
modeling leads to optimistic or pessimistic timing results.

44. What is SI-aware STA?

Answer:
SI-aware STA includes signal integrity effects like crosstalk, noise, and coupling into timing analysis.
Aggressor nets can change victim delay and cause glitches. Tools calculate delta delay and noise windows.
This makes timing closer to real silicon behavior.

45. What is noise analysis in STA?

Answer:
Noise analysis checks whether coupling noise can cause functional failure or delay variation. It verifies that
noise amplitude does not violate logic thresholds. STA reports peak noise and noise slack. Fixes include
spacing, shielding, and buffering.

46. What is clock gating setup/hold check in detail?

Answer:
Clock gating checks ensure the enable signal of a clock-gating cell is stable around the active clock edge.
Setup ensures enable arrives before the edge, and hold ensures it stays stable after. This prevents glitches
on the gated clock. Violations can corrupt sequential logic behavior.

47. What is time borrowing in latch-based designs?

Answer:
Time borrowing allows data to use part of the next cycle when passing through level-sensitive latches. This
improves performance by relaxing individual stage constraints. STA must account for transparency windows
and closing edges. Incorrect modeling can hide setup violations.

48. What is endpoint slack vs path slack?

Answer:
Endpoint slack reports the worst slack at a specific capture register. Path slack represents the slack of a

9
particular timing path. Multiple paths can end at the same endpoint. Engineers analyze both to identify and
fix real critical timing bottlenecks.

49. What is a timing loop and how is it handled?

Answer:
A timing loop occurs when combinational logic feeds back without a clear clock break. STA cannot resolve
infinite paths in loops. Designers break loops using constraints like set_disable_timing or by adding
registers. Handling loops is important for correct timing analysis.

50. What is constraint sanity checking in STA?

Answer:
Constraint sanity checking verifies clocks, exceptions, and uncertainties are correctly applied. It looks for
unconstrained paths, missing clocks, and conflicting exceptions. Reports like check_timing help validate
setup. Good constraints are the foundation of reliable STA signoff.

51. What is clock latency uncertainty vs data uncertainty?

Answer:
Clock latency uncertainty models variation in clock path delays due to jitter and skew. Data uncertainty
models variation in data path delays due to PVT effects. Clock uncertainty impacts both setup and hold
margins, while data uncertainty affects arrival time computation. Separating them helps achieve accurate
and safe timing closure.

52. What is source latency and network latency?

Answer:
Source latency is the delay from the clock source (PLL/port) to the CTS root. Network latency is the delay
from CTS root to the register clock pin. Together they form total clock latency. Balancing network latency is
a key goal of CTS.

53. What is skew group in CTS/STA?

Answer:
A skew group is a set of registers that must have tightly controlled clock skew among them. CTS builds the
clock tree to meet skew targets for these groups. STA then verifies setup and hold using those skew
constraints. Proper grouping improves timing predictability.

10
54. What is clock balance vs clock optimization?
Answer:
Clock balance aims to minimize skew between clock endpoints. Clock optimization intentionally introduces
useful skew to improve setup or hold margins. Balancing focuses on equality, while optimization focuses on
performance. Modern CTS combines both approaches for timing closure.

55. What is min pulse width check?

Answer:
Min pulse width ensures that clock and data pulses are wide enough for cells to operate correctly. Too small
pulses may not be captured reliably. STA checks high and low pulse widths against library requirements.
Violations can cause functional failures in silicon.

56. What is max path group and why is it used?

Answer:
Path groups classify timing paths such as reg2reg, in2reg, reg2out, and in2out. They allow designers to
analyze and prioritize different path types separately. STA reports worst paths per group. This helps focus
optimization on the most critical interfaces.

57. What is interface timing in STA?

Answer:
Interface timing analyzes paths between blocks or between chip and external pins. It uses input/output
delays relative to clocks. Correct interface constraints ensure proper communication between IPs. Poor
interface timing often causes system-level failures.

58. What is set_input_delay and set_output_delay?

Answer:
set_input_delay constrains arrival time of external signals relative to a clock. set_output_delay
constrains required time for outputs to be stable. They model board and neighboring block delays. These
constraints are essential for accurate interface STA.

59. What is clock latency override?

Answer:
Clock latency override manually specifies clock arrival time instead of tool-computed latency. It is useful for

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early STA before CTS. Designers use it to estimate timing budgets. After CTS, propagated clocks usually
replace overrides.

60. What is unconstrained path in STA?

Answer:
An unconstrained path has no clock or timing requirement applied. STA cannot check setup/hold for it. Such
paths are dangerous because violations may go unnoticed. Reports like check_timing help detect and
fix unconstrained paths.

61. What is timing coverage?

Answer:
Timing coverage measures how much of the design is properly constrained and analyzed. High coverage
means most paths are checked by STA. Low coverage indicates missing clocks or exceptions. Good coverage
is mandatory for signoff confidence.

62. What is clock interaction in multi-clock STA?

Answer:
Clock interaction defines timing relationships between different clocks, such as synchronous, asynchronous,
or exclusive. STA uses these relationships to decide which paths to check. Incorrect interaction modeling
causes false or missed violations. Proper definitions improve CDC and multi-clock analysis.

63. What is set_clock_groups?

Answer:
set_clock_groups defines relationships between clocks, such as asynchronous, exclusive, or physically
exclusive. It tells STA which clock domains should not be timed against each other. This prevents false cross-
domain timing checks. It is widely used in CDC timing setup.

64. What is clock jitter and its effect?

Answer:
Clock jitter is the short-term variation in clock edge positions. It reduces available setup time and tightens
hold margins. STA models jitter using clock uncertainty. Excessive jitter can limit maximum achievable
frequency.

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65. What is path margin?
Answer:
Path margin is the extra timing buffer beyond zero slack to ensure robustness. Designers often target
positive margin for critical paths. It accounts for modeling inaccuracies and future ECOs. Healthy margin
improves silicon reliability.

66. What is critical path in STA?

Answer:
The critical path is the timing path with the worst (minimum) slack in the design. It determines the
maximum operating frequency. Engineers focus optimization on this path first. Improving it often improves
overall chip performance.

67. What is arrival time and required time?

Answer:
Arrival time is when data reaches the capture point. Required time is the latest (setup) or earliest (hold) time
data is allowed. Slack is the difference between them. STA computes both to verify timing correctness.

68. What is clock pessimism and clock optimism?

Answer:
Clock pessimism adds extra margin assuming worst-case variation, reducing performance. Clock optimism
assumes ideal conditions and may hide violations. STA aims to balance safety and performance using CRPR
and variation models. Too much of either is risky.

69. What is set_max_delay and set_min_delay?

Answer:
set_max_delay constrains the maximum allowed delay between two points, useful for datapath limits.
set_min_delay constrains minimum delay, often used for hold control. They override default clock-
based checks. These are used for special timing requirements.

70. What is timing closure flow?

Answer:
Timing closure is the iterative process of fixing setup, hold, noise, and constraint issues until clean slack is

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achieved. It involves synthesis, placement, CTS, routing, STA, and ECO loops. Engineers analyze reports and
optimize paths. Successful closure is required before tapeout.

71. What is clock slew and why is it important?

Answer:
Clock slew is the transition time of the clock signal from low to high or high to low. Large slew increases cell
delay, uncertainty, and power. STA checks max transition on clock nets. Controlling clock slew improves
timing accuracy and reliability.

72. What is data slew in STA?

Answer:
Data slew is the signal transition time on data nets. Poor slew degrades cell delay, increases noise
sensitivity, and may violate max transition constraints. STA models delay based on slew and load. Fixing
slew improves timing and signal integrity.

73. What is timing derate early vs late?

Answer:
Early derates model fastest delays and are mainly used for hold analysis. Late derates model slowest delays
and are used for setup analysis. They scale cell and net delays to account for variation. Proper derates
ensure safe signoff timing.

74. What is clock tree depth?

Answer:
Clock tree depth is the number of buffer levels from the clock source to endpoints. Larger depth increases
insertion delay and skew sensitivity. CTS tries to balance depth across sinks. Controlled depth helps achieve
stable and predictable clock behavior.

75. What is path segmentation in STA?

Answer:
Path segmentation breaks a long timing path into smaller logical sections for analysis and optimization. It
helps identify which part of the path contributes most to delay. Engineers focus fixes on dominant
segments. This speeds up timing closure.

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76. What is retiming and its STA impact?
Answer:
Retiming moves registers across combinational logic to balance delays. It changes path structure and
critical paths. STA must be re-run after retiming to verify new setup and hold behavior. Retiming is powerful
for performance improvement.

77. What is boundary timing?

Answer:
Boundary timing checks paths crossing block or chip boundaries. It uses input/output constraints relative to
clocks. Correct boundary timing ensures blocks integrate properly. Errors here cause system-level timing
failures.

78. What is clock mux and its timing effect?

Answer:
Clock mux selects between multiple clock sources. It introduces additional delay and uncertainty. STA must
model both data and select timing for glitch-free operation. Improper constraints on clock muxes cause
clock integrity issues.

79. What is glitch in STA context?

Answer:
A glitch is a short unwanted pulse caused by unequal path delays. In clocks, glitches are dangerous and
may trigger flops incorrectly. STA prevents glitches using clock gating and mux checks. Controlling glitches
ensures functional correctness.

80. What is timing window?

Answer:
A timing window is the interval where a signal is allowed to switch safely. It is defined by setup and hold
boundaries. STA computes windows to avoid overlaps with noise and aggressors. Correct windows prevent
functional and timing failures.

81. What is launch clock vs capture clock?

Answer:
Launch clock triggers data launch from the source register. Capture clock triggers data sampling at the

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destination register. Their relative timing defines setup and hold constraints. STA compares these edges to
compute slack accurately.

82. What is clock phase uncertainty?

Answer:
Clock phase uncertainty models variation in relative phase between clocks. It is important for PLL-derived
and divided clocks. STA subtracts phase uncertainty from available time. This prevents optimistic
assumptions across clock domains.

83. What is useful skew for hold fixing?

Answer:
Useful skew can intentionally delay the launch clock or advance the capture clock to improve hold margin. It
reduces the chance of data arriving too early. CTS can insert buffers to realize this skew. It avoids adding
many delay buffers on data paths.

84. What is clock tree shielding?

Answer:
Clock tree shielding places grounded or power nets next to clock routes. It reduces coupling noise and
crosstalk. STA benefits by lowering delta delays and noise violations. Shielding improves clock signal
integrity.

85. What is SI delta cycle?

Answer:
SI delta cycle refers to iterative recalculation of delays after considering coupling effects. Aggressors and
victims are analyzed repeatedly until stable values are reached. This improves timing accuracy under noise.
It is part of SI-aware STA.

86. What is path exception misuse risk?

Answer:
Incorrect false or multicycle paths can hide real timing violations. Over-constraining makes STA optimistic.
Engineers must validate exceptions carefully. Good practice is to justify and review every exception for
signoff safety.

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87. What is timing budget?
Answer:
Timing budget allocates allowable delay to blocks or paths. It ensures each stage meets overall frequency
targets. Budgets guide synthesis and PnR optimization. STA verifies actual delays against assigned budgets.

88. What is clock reconvergence pessimism?

Answer:
When launch and capture clocks share common paths, variation is double-counted, creating pessimism.
This reduces slack artificially. CRPR removes the common portion. It improves accuracy without sacrificing
safety.

89. What is STA convergence?

Answer:
STA convergence means repeated optimization no longer significantly improves slack. Setup, hold, and
noise are clean across corners. ECOs stabilize. At this point, the design is close to signoff readiness.

90. What is timing ECO vs functional ECO?

Answer:
Timing ECO fixes performance issues using buffering, sizing, and rerouting. Functional ECO changes logic
behavior. STA mainly drives timing ECOs. Separating them avoids introducing new functional bugs late in
the flow.

91. What is clock uncertainty split?

Answer:
Clock uncertainty split divides total uncertainty between launch and capture clocks. This balances
pessimism across both ends. It models realistic clock behavior. Proper split avoids over-penalizing one side
of the timing path.

92. What is margining in STA?

Answer:
Margining adds extra buffer beyond zero slack for robustness. It accounts for future ECOs and modeling
errors. Designers target positive WNS and TNS. Margining improves silicon yield and reliability.

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93. What is timing correlation?
Answer:
Timing correlation models how variations on different segments relate to each other. Without correlation,
pessimism increases. POCV uses statistical correlation. This gives more realistic slack for deep submicron
designs.

94. What is path pruning?

Answer:
Path pruning removes non-critical or impossible paths from analysis. It speeds up STA runtime and focuses
on real critical paths. Exceptions and case analysis help pruning. Efficient pruning improves productivity
without losing accuracy.

95. What is clock domain exclusivity?

Answer:
Exclusive clocks never operate at the same time. STA can ignore timing between them. Designers specify
exclusivity using set_clock_groups. This prevents false cross-domain violations in multi-mode designs.

96. What is STA runtime optimization?

Answer:
Large designs need runtime control using path pruning, path groups, and PBA selectively. Reducing
unnecessary corners and reports also helps. Efficient setup speeds iteration. Faster STA improves
productivity during timing closure.

97. What is worst negative slack (WNS)?

Answer:
WNS is the most negative slack among all timing paths. It indicates the single worst violation. Engineers
prioritize fixing WNS first. Improving WNS directly improves maximum achievable frequency.

98. What is total negative slack (TNS)?

Answer:
TNS is the sum of all negative slacks in the design. It reflects overall timing health. Large TNS means many
violations. After fixing WNS, engineers reduce TNS to clean all remaining paths.

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99. What is endpoint violation vs path violation?
Answer:
Endpoint violation refers to worst slack at a specific register. Path violation refers to a specific timing path
failing. Multiple paths can fail at one endpoint. STA debugging uses both views for effective fixes.

100. What makes STA signoff-quality?

Answer:
Signoff-quality STA uses extracted parasitics, MMMC corners, SI, AOCV/POCV, CRPR, and clean constraints.
All setup, hold, noise, and checks must pass with margin. Reports are reviewed carefully. Only then is the
design tapeout-ready.

Prepared for STA / Physical Design Interview Preparation.

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