Instruction Set Architecture

(ISA)

By Dr. Hadiza Ali Umar

What is an Instruction Set Architecture (ISA)?
ISA = All of the programmer-visible components and operations of the
computer
• memory organization
• address space -- how may locations can be addressed?
• addressibility -- how many bits per location?
• register set
• how many? what size? how are they used?
• instruction set
• opcodes
• data types
• addressing modes
ISA provides all information needed for someone that wants to write a program in machine
language (or translate from a high-level language to machine language).
Instruction Set Architecture
• An instruction set architecture (ISA) is an abstract model that defines the programmable
interface of the CPU of a computer, how the software can control a computer. A device (i.e. CPU)
that interprets instructions described by an ISA is an implementation of that ISA. Generally, the
same ISA is used for a family of related CPU devices.
• In general, an ISA defines the instructions, data types, Registers and the programming interface
for managing main memory such as addressing modes, virtual memory and memory
consistency mechanisms. The ISA also includes the input/output model of the programmable
interface.
• An ISA specifies the behavior implied by machine code running on an implementation of that ISA
in a fashion that does not depend on the characteristics of that implementation, providing binary
compatibility between implementations. This enables multiple implementations of an ISA that
differ in characteristics such as performance, physical size, and monetary cost (among other
things), but that are capable of running the same machine code, so that a lower-performance,
lower-cost machine can be replaced with a higher-cost, higher-performance machine without
having to replace software. It also enables the evolution of the microarchitectures of the
implementations of that ISA, so that a newer, higher-performance implementation of an ISA can
run software that runs on previous generations of implementations.
Classification of ISAs
• An ISA may be classified in a number of different ways.
• A common classification is by architectural complexity.
o A Complex Instruction Set Computer (CISC) has many specialised instructions, some of which may only be
rarely used in practical programs.
o A Reduced Instruction Set Computer (RISC) simplifies the processor by efficiently implementing only the
instructions that are frequently used in programs, while the less common operations are implemented as
subroutines, having their resulting additional processor execution time offset by infrequent use.
• Other types include:
o Very Long Instruction Word (VLIW) architectures, and the closely related
o Long Instruction Word (LIW)
o Explicitly Parallel Instruction Computing (EPIC)
These architectures seek to exploit instruction-level parallelism with less hardware than RISC and
CISC by making the compiler responsible for instruction issue and scheduling.
• Architectures with even less complexity have been studied, such as the Minimal Instruction Set
Compiler (MISC) and One-Instruction Set Computer (OISC).
Difference between CISC and RISC
ISA Design Goals
• Ease of programming (software perspective)
• Ease of implementation (hardware perspective)
• Good performance
• Compatibility
• Completeness (eg, Turing)
• Compactness – reduce program size
• Scalability / extensibility
• Features: Support for OS / parallelism / … etc
• ISA design goals / Code generation
Ease of Programming
• The ISA should make it easy to express programs and make it easy to create efficient
programs.
• Who is creating the programs?
◦Early Days: Humans.
◦No real compilers
◦Resources very limited
◦Q: What does that mean for the ISA designer?
◦A: High-level operations
• Modern days (~1980 and beyond): Compilers
◦Today’s optimizing compiler do a much better job than most humans
◦Q: What does that mean for the ISA designer?
◦A: Fine-grained, low-level instructions
Ease of Implementation
• ISA should not get in the way of optimizing implementation.
• Examples:
◦Variable length instructions
◦Varying instruction formats
◦Implied registers
◦Complex addressing modes
◦Precise interrupts
◦Appearance of atomic execution
What is performance?

• Throughput – how many programs can I execute per unit time?

• Elapsed time – how long does my program take to execute?
◦Total time from start to finish including everything (e.g., I/O)
• CPU time – only time spent in processor
Architects mostly focus on this
Abstraction layers in modern systems
Response Time (latency)

• Elapsed time
◦Total time from start to finish, including everything
• CPU time (only time spent in the processor)
• 𝐶𝑃𝑈 𝑇𝑖𝑚𝑒 = 𝐶𝑃𝑈𝑐𝑙𝑜𝑐𝑘 𝑐𝑦𝑐𝑙𝑒𝑠 × 𝐶𝑃𝑈𝑐𝑙𝑜𝑐𝑘𝑡𝑖𝑚𝑒
• CPU clock cycles = number of cycles needed to execute the program
◦# of instructions executed
◦Cycles per instruction
• CPU clock time = 1 / frequency
“The Iron Law of Performance”

• What determines each factor? How does ISA impact each?

• Instructions / Program = dynamic instruction count (not code size)
◦ Determined by program, compiler, and ISA
• Cycles / Instruction (CPI)
◦ Determined by ISA, 𝜇arch, program, and compiler
• Seconds / Cycle (critical path)
◦ Determined by 𝜇arch and technology
Cycles Per Instruction (CPI)

• Different instruction classes take different numbers of cycles.

• In fact, even the same instruction can take a different number of
cycles.
◦Example?
• When we say CPI, we really mean : Weighted CPI
Instruction Cycle
Performance
• Instruction Count (IC) -- The number of instructions the CPU executes
• Cycles per instructions -- The ratio of cycles for execution to the
number of instructions executed.
• Cycle time -- The length of a clock cycle in seconds
• We use clock speed more than second/cycle
• Clock speed is measured in Hz (e.g., MHz, GHz, etc.)
• x Hz => 1/x seconds per cycle
• 2.5GHz => 1/2.5x109 seconds (0.4ns) per cycle
CPU time

• How to improve performance:

• Reduce instruction count
• Reduce cycles per instruction
• Reduce clock time
• But there is a tension between these…
CPI example – which machine is faster?
CPI example – which machine is faster?
• Computer A: Cycle time = 250ps, CPI = 2.0
• Computer B: Cycle time = 500ps, CPI = 1.2
CMOS and Power
• Instruction set: The collection of commands the processor can
Key Aspects
understand,
of an ISA
including operations like ADD, LOAD, and JUMP.
• Data types and registers: Defines the types of data the processor can
operate
on and the number and size of the internal storage locations
(registers).
• Addressing modes: Specifies how the processor accesses data in
memory.
• Instruction format: Determines the structure and layout of the
machine code instructions.
• Memory model: Outlines how the main memory is managed.
Importance and Function of ISA
• Hardware-software interface:
The ISA is the crucial link that allows software to control the hardware.
• Programmer's manual:
It acts as a programmer's manual for assembly language and compiler writers,
as it's the portion of the machine that is visible to them.
• Processor design:
ISAs are used for a family of related CPUs, meaning that different processor
models can share the same ISA.
• Performance and efficiency:
Understanding the ISA can help developers write more efficient code and
understand how a compiler translates high-level instructions into machine code.
What goes into an ISA?
• Operands
◦How many?
◦What kind?
◦Addressing mechanisms
• Operations
◦What kind?
◦How many?
• Format/encoding
◦Length(s) of bit pattern
◦Which bits mean what
Operands – Machine Model
• Three basic types of machines
◦ Stack
◦ Accumulator
◦ Register
• Two types of register machines
◦ Register-memory
◦ Most operands in most instructions can be either a register or an
operand
• Machine model memory address
◦Load-store
◦Instructions are either load/store or register-based
Machine Model Trade-offs
• Stack and Accumulator:
◦ Each instruction encoding is short
◦ IC is high
◦ Very simple exposed architecture
• Register-Memory:
◦ Instruction encoding is much longer
◦ More work per instruction
◦ IC is low
◦ Architectural state is more complex
• Load/Store:
◦ Medium encoding length
◦ Less work per instruction
◦ IC is high
◦ Architectural state is more complex