Digital Electronics Lab (BEE 453)

LAB EXPERIMENTS

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 Digital Electronics Lab (BEE 453)

EXPERIMENT NO: 1
Aim: - Introduction to Digital Electronics Lab- Nomenclature of Digital
Ics, Specifications, Study of the Data Sheet, Concept of Vcc and Ground,
Verification of the Truth Tables of Logic Gates using TTL Ics.
APPARATUS REQUIRED: Power Supply, Digital Trainer Kit., Connecting Leads,
IC‟s (7400, 7402, 7404, 7408, 7432, and 7486)

BRIEF THEORY:

AND Gate: The AND operation is defined as the output as (1) one if and only if all the
inputs are (1) one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals &Y
is the Output terminal.
Y = A.B
OR Gate: The OR operation is defined as the output as (1) one if one or more than 0
inputs are (1) one. 7432 is the two Input OR gate IC. A&B are the input terminals & Y is
the Output terminal.
Y=A+B
NOT GATE: The NOT gate is also known as Inverter. It has one input (A) & one output
(Y). IC No. is 7404. Its logical equation is,
Y = A NOT B, Y = A‟
NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is known
as NAND operation. If all inputs are 1 then output produced is 0. NAND gate is inverted
AND gate.
Y = (A. B)‟
NOR GATE: The NOR gate has two or more input signals but only one output signal. IC
7402 is two I/P IC. The NOT- OR operation is known as NOR operation. If all the inputs
are 0 then the O/P is 1. NOR gate is inverted OR gate.

Y = (A+B)‟

EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output.
7486 is two inputs IC. EX-OR gate is not a basic operation & can be performed using
basic gates.
Y=A B

LOGIC SYMBOL:
. Logic Symbol of Gates

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 Digital Electronics Lab (BEE 453)

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 Digital Electronics Lab (BEE 453)

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7486(EX-OR) 7432(OR)

PROCEDURE:
(a) Fix the IC‟s on breadboard & give the supply.
(b) Connect the +ve terminal of supply to pin 14 & -ve to pin 7.
(c) Give input at pin 1, 2 & take output from pin 3. It is same for
all except NOT & NOR IC.
(d) For NOR, pin 1 is output & pin 2&3 are inputs.
(e) For NOT, pin 1 is input & pin 2 is output.
(f) Note the values of output for different combination of inputs
& draw the TRUTH TABLE.

OBSERVATION TABLE:

INPUTS OUTPUTS
A’ A+B (A+B)’ (A*B) (A*B )’ (A B)
A B
NOT OR NOR AND NAND Ex-OR
0 0 1 0 1 0 1 0
0 1 1 1 0 0 1 1
1 0 0 1 0 0 1 1
1 1 1

RESULT: We have learnt all the gates ICs according to the IC pin diagram.

PRECAUTIONS:

1. Make the connections according to the IC pin diagram.

2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.

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Quiz Questions with answer.

Q.1 Define gates ?

Ans. Gates are the digital circuits, which perform a specific type of logical operation.

Q.2 Define IC?

Ans. IC means integrated circuit. It is the integration of no. of components on a
common substrate.
Q.3 Give example of Demorgan‟s theorem.
Ans. (AB)‟=A‟+B‟
(A+B)‟=A‟.B‟
Q.4 (A+A) A =?
Ans. A.
Q5 Define Universal gates.
Ans. Universal gates are those gates by using which we can design any type of logical
expression.
[Link] the logical equation for AND gate.
Ans. Y=A.B
Q7 How many no. of input variables can a NOT Gate have?
Ans. One.
[Link] what conditions the output of a two input AND gate is one?
Ans. Both the inputs are one.
Q9.1+0 =?
Ans. 1
[Link] will the output of a NAND Gate be 0?
Ans. When all the inputs are 1.

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EXPERIMENT NO: 2
Aim: Implementation of the Given Boolean Function using Logic Gates in
Both SOP and POS Forms.
APPARATUS REQUIRED: Power Supply, Digital Trainer, IC‟s (7404, 7408,
7432) Connecting leads.

BRIEF THEORY: Karnaugh maps are the most extensively used tool for simplification
of Boolean functions. It is mostly used for functions having up to six variables beyond
which it becomes very cumbersome. In an n-variable K-map there are 2ⁿ cells. Each cell
corresponds to one of the combination of n variable, since there are 2ⁿ combinations of n-
variables. Gray code has been used for the identification of cells.

Example- f (A, B, C, D) =A‟BC+AB‟C+ABC‟+ABC (SOP)

Reduced form is BC+AC+AB and POS form is f(X, Y, Z) = Y‟ (X‟+Y+Z‟) (X+Z)

LOGIC DIAGRAM
SOP form

POS Form

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PROCEDURE:
(a) With given equation in SOP/POS forms first of all draw a K-
map.
(b) Enter the values of the O/P variable in each cell corresponding
to its Min/Max term.
(c) Make group of adjacent ones.
(d) From group write the minimized equation.
(e) Design the ckt. of minimized equation & verify the truth table.

RESULT/CONCLUSION: Implementation of SOP and POS form is obtained with

AND and OR gates.

PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q.1 Define K-map ?

Ans. It is a method of simplifying Boolean Functions in a systematic mathematical
way.
Q.2 Define SOP ?
Ans. Sum of Product.
Q.3 Define POS ?
Ans. Product of Sum.
Q.4 What are combinational circuits?
Ans. These are those circuits whose output depends upon the inputs present at that
instant of time.
Q.5 What are sequential circuits?
Ans. These are those circuits whose output depends upon the input present at that time
as well as the previous output.
Q.6 If there are four variables how many cells the K-map will have?
Ans. 16.
Q.7 When two min-terms can be adjacent?
Ans. 2 to the power n.
Q.8 Which code is used for the identification of cells?
Ans8. Gray Code.
Q.9 Define Byte?
Ans. Byte is a combination of 8 bits.
Q.10 When simplified with Boolean Algebra (x + y)(x + z) simplifies to
Ans. x + yz

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EXPERIMENT NO: 3
Aim: Verification of State Tables of Rs, J-k, T and D Flip-Flops using
NAND & NOR Gates
APPARATUS REQUIRED: IC‟ S 7400, 7402 Digital Trainer & Connecting
leads.

BRIEF THEORY:

 RS FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. When
I/Ps R = 0 and S = 0 then O/P remains unchanged. When I/Ps R = 0 and S = 1 the
flip-flop is switches to the stable state where O/P is 1 i.e. SET. The I/P condition
is R = 1 and S = 0 the flip-flop is switched to the stable state where O/P is 0 i.e.
RESET. The I/P condition is R = 1 and S = 1 the flip-flop is switched to the stable
state where O/P is forbidden.

 JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal

element to use. The variable J and K are called control I/Ps because they
determine what the flip- flop does when a positive edge arrives. When J and K are
both 0s, both AND gates are disabled and Q retains its last value.

 D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching
the Q output until clock pulses occur. When the clock is low, both AND gates
are disabled D can change value without affecting the value of [Link] the other
hand, when the clock is high, both AND gates are enabled. In this case, Q is
forced to equal the value of D. When the clock again goes low, Q retains or
stores the last value of D. a D flip flop is a bistable circuit whose Dinput is
transferred to the output after a clock pulse is received.

 T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock

edge, giving an output which is half the frequency of the signal to the T input.
It is useful for constructing binary counters, frequency dividers, and general
binary addition devices. It can be made from a J-K flip-flop by tying both of
its inputs high.

CIRCUIT DIAGRAM:
SR Flip Flop D Flip Flop

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JK Flip Flop T Flip Flop

PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

TRUTH TABLE:
SR FLIP FLOP:

CLOCK S R Qn+1
1 0 0 NO CHANGE
1 0 1 0
1 1 0 1
1 1 1 ?

D FLIPFLOP:

INPUT OUTPUT
0 0
1 1

JK FLIPFLOP

CLOCK S R Qn+1
1 0 0 NO CHANGE
1 0 1 0
1 1 0 1
1 1 1 Qn’

T FLIPFLOP

CLOCK S R Qn+1
1 0 1 NO CHANGE
1 1 0 Qn’

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RESULT: Truth table is verified on digital trainer.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q [Link] flop is Astable or Bistable?

Ans. Bistable.
[Link] are the I/Ps of JK flip–flop where this race round condition occurs?
Ans. Both the inputs are 1.
[Link] RS flip-flop is said to be in a SET state?
Ans. When the output is 1.
[Link] RS flip-flop is said to be in a RESET state?
Ans. When the output is 0.
[Link] is the truth table of JK flip-flop?
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 ‟
Qn,
[Link] is the function of clock signal in flip-flop?
Ans. To get the output at known time.
[Link] is the advantage of JK flip-flop over RS flip-flop?
Ans. In RS flip-flop when both the inputs are 1 output is undetermined.
[Link] D flip-flop I/P = 0 what is O/P?
Ans.0
[Link] D flip-flop I/P = 1 what is O/P?
Ans.1
[Link] T flip-flop I/P = 1 what is O/P?
Ans. Qn

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EXPERIMENT NO: 4
Aim:- Implementation and Verification of Decoder/De-Multiplexer and
Encoder using Logic Gates.

APPARATUS REQUIRED: IC 7447, 7-segment display, IC 74139 andconnecting

leads.

BRIEF THEORY:

ENCODER: An encoder is a device, circuit, transducer, software program, algorithm or

person that converts information from one format or code to another, for the purposes of
standardization, speed, secrecy, security, or saving space by shrinking size. An encoder
has M input and N output lines. Out of M input lines only one is activated at a time and
produces equivalent code on output N lines. If a device output code has fewer bits than
the input code has, the device is usually called an encoder. For example Octal-to-Binary
Encoder take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-to-8
decoder does. At any one time, only one input line has a value of 1. The figure below
shows the truth table of an Octal-to-binary encoder.

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs
Y0-Y2 are:

Y0 = I1 + I3 + I5 + I7

Y1= I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 +I7

DECODER: A decoder is a device which does the reverse operation of an encoder,

undoing the encoding so that the original information can be retrieved. The same method
used to encode is usually just reversed in order to decode. It is a combinational circuit that
converts binary information from n input lines to a maximum of 2n unique output lines. In
digital electronics, a decoder can take the form of a multiple-input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes
are different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for
the decoder to function, otherwise its outputs assume a single "disabled" output code
word. In case of decoding all combinations of three bits eight (2 3=8) decoding gates are
required. This type of decoder is called 3-8 decoder because 3 inputs and 8 outputs. For
any input combination decoder outputs are 1.

DEMULTIPLEXER: Demultiplexer means generally one into many. A demultiplexer is

a logic circuit with one input and many outputs. By applying control signals, we can steer the
input signal to one of the output lines. The ckt. has one input signal, m control

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signal and n output signals. Where 2n = m. It functions as an electronic switch to route an

incoming data signal to one of several outputs.

LOGIC DIAGRAM:

3:8 Decoder Octal to Binary Encoder

1:4 Demux

PROCEDURE:
1) Connect the circuit as shown in figure.
2) Apply Vcc & ground signal to every IC.
3) Observe the input & output according to the truth table.
OBSERVATION TABLE:

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Truth table for Decoder

Truth table for Encoder Truth table for Demux

RESULT: Encoder/ decoder and demultiplexer have been studied and verified.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q. 1 What do you understand by decoder?

Ans. A decoder is a combinational circuit that converts binary information from n
input lines to a maximum of 2n unique output lines. Most IC decoders include one or
more enable inputs to control the circuit operation.
Q. 2 What is demultiplexer?
Ans. The demultiplexer is the inverse of the multiplexer, in that it takes a single data input
and n address inputs. It has 2n outputs. The address input determine which data

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output is going to have the same value as the data input. The other data outputs will
have the value 0.
Q. 3 What do you understand by encoder?
Ans. An encoder or multiplexer is therefore a digital IC that outputs a digital code
based on which of its several digital inputs is enabled.
Q. 4 What is the main difference between decoder and demultiplexer?
Ans. In decoder we have n input lines as in demultiplexer we have n select lines.
Q. 5 Why Binary is different from Gray code?
Ans. Gray code has a unique property that any two adjacent gray codes differ by only
a single bit.
Q. 6 Write down the method of Binary to Gray conversion.
Ans. Using the Ex-Or gates.
Q. 7 Convert 0101 to Decimal.
Ans. 5
Q. 8 Write the full form of ASCII Codes?
Ans. American Standard Code for Information Interchange.
Q.9. If a register containing 0.110011 is logically added to register containing
0.101010 what would be the result?
Ans.111011
[Link] code is a weighted code or not?
Ans. Yes

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EXPERIMENT NO : 5
Aim: Implementation of 4x1 Multiplexer using Logic Gates.
APPARATUS REQUIRED: Power Supply, Digital Trainer, Connecting Leads, IC‟s
74153(4x1 multiplexer).

BRIEF THEORY:

MULTIPLEXER: Multiplexer generally means many into one. A multiplexer is a

circuit with many Inputs but only one output. By applying control signals we can steer
any input to the output .The fig. (1) Shows the general idea. The ckt. has n-input signal,
control signal & one output signal. Where 2 n = m. One of the popular multiplexer is the
16 to 1 multiplexer, which has 16 input bits, 4 control bits & 1 output bit.

PIN CONFIGURATION;–
IC 74153 (4x1 multiplexer)

LOGIC DIAGRAM:

Multiplexer (4x1) IC 74153

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PROCEDURE:
1. Fix the IC's on the bread board &give the input supply.
2. Make connection according to the circuit.
3. Give select signal and strobe signal at respective pins.
4. Connect +5 v Vcc supply at pin no 24 & GND at pin
no 12.
5. Verify the truth table for various inputs.

OBSERVATION TABLE:

Truth Table of multiplexer (4x1) IC 74153

RESULT: Verify the truth table of multiplexer for various inputs.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

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2) The connections should be tight.

3) The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q.1 Why is MUX called as “Data Selector”?

Ans. This selects one out of many inputs.
Q.2 What do you mean by Multiplexing?
Ans. Multiplexing means selecting only a single input out of many inputs.
Q.3 What is Digital Multiplexer?
Ans. The multiplexer which acts on digital data.
Q.4 What is the function of Enable input to any IC?
Ans. When this enable signal is activated.
Q.5 What is demultiplexer?
Ans. A demultiplexer transmits the data from a single source to various sources.
Q.6 Can a decoder function as a D‟MUX?
Ans. Yes
Q.7 What is the role of select lines in a Demultiplexer?
Ans. Select line selects the output line.
Q.8 Differentiate between functions of MUX & D‟MUX?
Ans. Multiplexer has only single output but demultiplexer has many outputs.
Q.9 The number of control lines required for a 1:8 demultiplexer will be
Ans. 3
Q.10 How many 4:1 multiplexers will be required to design 8:1 multiplexer?
Ans. 2

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 Digital Electronics Lab (BEE 453)

EXPERIMENT NO - 6

Aim – Implementation of 4-Bit Parallel Adder Using 7483 Ic.

APPRATUS REQUIRED – Digital trainer kit, IC 7483 (4-bit parallel adder).

BRIEF THEOR - A 4-bit adder is a circuit which adds two 4-bits numbers, say, A
and B. In addition, a 4-bit adder will have another single-bit input which is added to
the two numbers called the carry-in (Cin). The output of the 4-bit adder is a 4-bit sum
(S) and a carry-out (Cout) bit.

PIN CONFIGURATION–
Pin Diagram of IC 7483

IC 7483

LOGIC DIAGRAM:-

7483 4-bit Parallel Adder

OBSERVATION TABLE –

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Truth table of 4-bit parallel adder

PROCEDURE –
a) Make the connections as per the logic diagram.
b) Connect +5v and ground according to pin configuration.
c) Apply diff combinations of inputs to the i/p terminals.
d) Note o/p for summation.
e) Verify the truth table.

RESULT- Binary 4-bit full adder is studied and verified.

PRECAUTIONS:
1. Make the connections according to the IC pin diagram.
2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q 1 What do you understand by parallel adder?

Ans. If we place full adders in parallel, we can add two- or four-digit numbers or any
other size desired i.e. known as parallel adder.
Q2 What happens when an N-bit adder adds two numbers whose sum is greater than
or equal to 2N
Ans. Overflow.
Q3 Is Excess-3 code is weighted code or not?
Ans. Excess-3 is not a weighted code.
Q4 What is IC no. of parallel adder?
Ans. IC 7483.
Q5 What is the difference between Excess-3 & Natural BCD code?
Ans. Natural BCD code is weighted code but Excess-3 code is not weighted code.
Q6. What is the Excess-3 code for (396)10
Ans. (396)10 = (011011001001)EX-3
Q7 Can we obtain 1‟s complement using parallel adder?
Ans. Yes
Q8 Can we obtain 2‟s complement using parallel adder?
Ans. yes
Q9 How many bits can be added using IC7483 parallel adder?
Ans. 4 bits.
Q10 Can you obtain subtractor using parallel adder?
Ans. Yes

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EXPERIMENT NO :7
Aim: – Design, and Verify the 4-Bit Synchronous Counter
APPARATUS REQUIRED: Digital trainer kit and 4 JK flip flop each IC 7476 (i.e dual
JK flip flop) and two AND gates IC 7408.

BRIEF THEORY: Counter is a circuit which cycle through state sequence. Two types
of counter, Synchronous counter (e.g. parallel) and Asynchronous counter (e.g. ripple). In
Ripple counter same flip-flop output to be used as clock signal source for other flip-flop.
Synchronous counter use the same clock signal for all flip-flop.

PIN CONFIGURATION:
Dual JK Master Slave Flip Flop with clear & preset

LOGIC DIAGRAM:
4- Bit Synchronous counter

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Pin Number Description

1 Clock 1 Input
2 Preset 1 Input
3 Clear 1 Input
4 J1 Input
5 Vcc
6 Clock 2 Input
7 Preset 2 Input
8 Clear 2 Input
9 J2 Input
10 Complement Q2 Output
11 Q2 Output
12 K2 Input
13 Ground
14 Complement Q1 Output
15 Q1 Output

16 K1 Input

OBSERVATION TABLE:
Truth Table

States Count
04 03 02 01
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6

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0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15

PROCEDURE:
a) Make the connections as per the logic diagram.
b) Connect +5v and ground according to pin configuration.
c) Apply diff combinations of inputs to the i/p terminals.
d) Note o/p for summation.
e) Verify the truth table.

RESULT: 4-bit synchronous counter studied and verified.

PRECAUTIONS:
1. Make the connections according to the IC pin diagram.
2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q.1 What do you understand by counter?

Ans. Counter is a register which counts the sequence in binary form.
Q.2What is asynchronous counter?
Ans. Clock input is applied to LSB FF. The output of first FF is connected as clock to
next FF.
Q.3What is synchronous counter?
Ans. Where Clock input is common to all FF.
Q.4Which flip flop is used in asynchronous counter?
Ans. All Flip-Flops are toggling FF.
Q. 5Which flip flop is used in synchronous counter?
Ans. Any FF can be used.
Q.6 What do you understand by modulus?
Ans. The total no. of states in counter is called as modulus. If counter is modulus-n,
then it has n different states.
Q.7 What do you understand by state diagram?

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Ans. State diagram of counter is a pictorial representation of counter states directed by

arrows in graph.
Q.8 What do you understand by up/down counter?
Ans. Up/Down Synchronous Counter: two way counter which able to count up or
down.
Q.9 Why Asynchronous counter is known as ripple counter?
Ans. Asynchronous Counter: flip-flop doesn‟t change condition simultaneously
because it doesn‟t use single clock signal Also known as ripple counter because clock
signal input as ripple through counter.
Q.10 which type of counter is used in traffic signal?
Ans. Down counters.

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EXPERIMENT NO: 8
Aim: – Design, and Verify the 4-Bit Asynchronous Counter.
APPARATUS REQUIRED: Digital trainer kit and 4 JK flip flop each IC 7476 (i.e dual JK
flip flop) and two AND gates IC 7408.

BRIEF THEORY: Counter is a circuit which cycle through state sequence. Two types
of counter, Synchronous counter (e.g. parallel) and Asynchronous counter (e.g. ripple). In
Ripple counter same flip-flop output to be used as clock signal source for other flip-flop.
Synchronous counter use the same clock signal for all flip-flop.

PIN CONFIGURATION:

Pin diagram of JK M/S Flip Flop

LOGIC DIAGRAM:
4- Bit Asynchronous counter

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Pin Number Description

1 Clock 1 Input
2 Preset 1 Input
3 Clear 1 Input
4 J1 Input
5 Vcc
6 Clock 2 Input
7 Preset 2 Input
8 Clear 2 Input
9 J2 Input
10 Complement Q2 Output
11 Q2 Output
12 K2 Input
13 Ground
14 Complement Q1 Output
15 Q1 Output
16 K1 Input
PROCEDURE:
a) Make the connections as per the logic diagram.
b) Connect +5v and ground according to pin configuration.
c) Apply diff combinations of inputs to the i/p terminals.
d) Note o/p for summation.
e) Verify the truth table.

RESULT: 4-bit asynchronous counter studied and verified.

PRECAUTIONS:
1. Make the connections according to the IC pin diagram.
2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q.1 How many flip-flops are required to make a MOD-32 binary counter?
Ans. 5.
Q.2 The terminal count of a modulus-11 binary counter is .
Ans.1010.
Q.3 Synchronous counters eliminate the delay problems encountered with
asynchronous counters because the:
Ans. Input clock pulses are applied simultaneously to each stage.

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Q4. Synchronous construction reduces the delay time of a counter to the delay of:

Ans. a single flip-flop and a gate.

Q5. What is the difference between a 7490 and a 7492?

Ans.7490 is a MOD-10, 7492 is a MOD-12.

Q6. When two counters are cascaded, the overall MOD number is equal to the
of their individual MOD numbers.
Ans. Product.
Q7. A BCD counter is a .
Ans. decade counter.
Q8. What decimal value is required to produce an output at "X" ?

Ans.5.

Q9. How many AND gates would be required to completely decode ALL the states of
a MOD-64 counter, and how many inputs must each AND gate have?

Ans. 64 gates, 6 inputs to each gate.

Q.10 A ring counter consisting of five Flip-Flops will have
Ans. 5 states.

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EXPERIMENT NO: 9
Aim:- To Design &Verify Operation of Half Adder &Full Adder.

APPARATUS REQUIRED: Power supply, IC‟s, Digital Trainer, Connecting leads.

BRIEF THEORY: We are familiar with ALU, which performs all arithmetic and logic
operation but ALU doesn‟t perform/ process decimal no‟s. They process binary no‟s.

Half Adder: It is a logic circuit that adds two bits. It produces the O/P, sum & carry.
The Boolean equation for sum & carry are:
SUM = A + B
CARRY = A. B
Therefore, sum produces 1 when A&B are different and carry is 1when A&B are 1.
Application of Half adder is limited.

Full Adder: It is a logic circuit that can add three bits. It produces two O/P sum & carry.
The Boolean Equation for sum & carry are:
SUM = A + B + C
CARRY = A.B + (A+B) C
Therefore, sum produces one when I/P is containing odd no‟s of one & carry is one when
there are two or more one in I/P.

LOGIC DAIGRAM:
Half Adder Full Adder

PROCEDURE:
(a) Connect the ckt. as shown in fig. For half adder.
(b) Apply diff. Combination of inputs to the I/P terminal.
(c) Note O/P for Half adder.
(d) Repeat procedure for Full wave.
(e) The result should be in accordance with truth table.

OBSERVATION TABLE:

HALF ADDER:

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 Digital Electronics Lab (BEE 453)

INPUTS OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER:
INPUTS OUTPUTS
A B C S CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

RESULT: The Half Adder & Full Adder ckts. are verified.

PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q.1 Give the basic rules for binary addition?
Ans. 0+0 = 0; 0+1 = 1; 1+1 = 1 0 ; 1+0 = 1.
Q.2 Specify the no. of I/P and O/P of Half adder?
Ans2. Two inputs & one output.
Q.3 What is the drawback of half adder?
Ans. We can‟t add carry bit from previous stage.
Q.4 Write the equation for sum & carry of half adder?
Ans. Sum = A XOR B; carry = A.B.
Q.5 Write the equation for sum & carry of full adder?
Ans. SUM= A‟B‟C+A‟BC‟+AB‟C‟+ABC; CARRY=AB+BC+AC.
Q.6 How many half adders will be required for Implementing full adder?
Ans. Two half adders and a OR gate.
Q7 Define Bit?
Ans. Bit is an abbreviation for binary digit.
[Link] is the difference b/w half adder& half sub tractor?
Ans. Half adder can add two bits & half sub tractor can subtract two bits.
Q9. Half subtractor logic circuit has one extra logic element. Name the element?
Ans. Inverter.
Q10. Define Nibble?
Ans. Combination of four bits.

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 Digital Electronics Lab (BEE 453)

EXPERIMENT NO :10
Aim:- To Study &Verify Half Subtractor.

APPARATUS REQUIRED: Digital trainer kit,

IC 7486 (EX-OR)
IC 7408 (AND gate)
IC 7404 (NOT gate)

BRIEF THEORY: A logic circuit for the subtraction of B(subtrahend) from A

(minuend) where A& B are 1 bit numbers is referred as half- sub tractor.

LOGIC DIAGRAM :

TRUTH TABLE:

INPUT 1 (X) INPUT 2 (Y) BORROW (B) DIFFERENCE (D)

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

PROCEDURE:

1. Make the connections as per the logic diagram.

2. Connect +5v to pin 14 & ground to pin 7.
3. Apply 0 to input X & Y as per the truth table.
4. Switch on the instrument.
5. Observe the reading on 8 bits LED display.
6. Repeat steps 3 & 5 for different input as per truth table.
7. Verify the truth table.

RESULT: Half sub tractor circuit is studied and verified.

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 Digital Electronics Lab (BEE 453)

Quiz Questions with answer.

Q.1 What is half subs tractor?

Ans. Performs subs traction of two bits.
Q.2 For implementing half subs tractor how many EX-OR, AND gates and Not gates
are required?
Ans. One EX-OR, one –AND gate, one- Not gate.
Q.3 What are the logical equations for difference & borrow?
Ans. D = ĀB +A¯B
B = Ā.B
Q.4 How full subtractor is different from half subs tractor.
Ans. Full sub tractor performs subtraction of three bits but half subs tractor Performs
subtraction of two bits.
Q5 If inputs of half subs tractor are A=0, and B=1 then Borrow will be?
Ans. B=1
Q.6 Is 2‟s complement method appropriate for subtraction?
Ans. 2‟s complement method is appropriate method for subtraction.
Q.7 How many bits we use in half subtractor for subtraction?
Ans. only two bits.
Q. 8Can we use parallel adder for subtraction?
Ans. We can use parallel adder using 2‟s complement method.
Q.9 Which one is better subtractor or parallel adder for subtraction?
Ans. Parallel adder is the best option using 1‟s complement or 2‟s complement
Q.10 Which adder is used for addition of BCD numbers?
Ans. BCD adder.

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