CHAPTER 5

SEQUENTIAL CIRCUITS
 Sequential circuit is a combinational logic circuit that consists of inputs variable , logic gates and output variable .
 The combinational circuits have set of outputs, which depends only on the present combination of inputs.
 A combinational circuit produces an output based on input variables only.
 But a sequential circuit produces an output based on current input and previous output variables.
 That means sequential circuits include memory elements that are capable of storing binary information.
 That binary information defines the state of the sequential circuit at that time.
 The previous output is treated as the present state.
 So, the sequential circuit contains the combinational circuit and its memory storage elements.
 Difference between the combinational circuits and sequential circuits:

Combinational Circuits Sequential Circuits

 The outputs of the combinational circuit depend only on the  The outputs of the sequential circuits depend on both present
present inputs. inputs and present state(previous output).

 The feedback path is not present in the combinational circuit.  The feedback path is present in the sequential circuits.

 In combinational circuits, memory elements are not required.  In the sequential circuit, memory elements play an important role
and require.

 The clock signal is not required for combinational circuits.  The clock signal is required for sequential circuits.

 The combinational circuit is simple to design.  It is not simple to design.

Example: adder, subtractor, decoder, encoder, multiplexer Example: flip-flop, counter, shift register
and demultiplexer
 Latch
 Latches are sequential circuit and basic storage elements that has LOW and HIGH two stable states(bi-stable).
 It stores single bit at a time(either 0 or 1) and It is a basic form of memory.
 Latches are considered unstable in modern circuits and rarely used.
 Latches controlled by a clock transition are called flip-flops.
 Latches does not depend on the clock pulse.
 Flip flops that do not use clock pulse are referred to as latch.
SR (Set-Reset) Latch
They are also known as Set and Reset states.
The SR latch forms the basic building blocks of all other types of flip-flops.
SR Latch using NOR gates(Active HIGH input S-R latch):
When the circuit will be reset means Q value will be equal to 0 and when the circuit will be set means the Q value will be
equal to 1.
Example:
OR Truth table of Gated S-R latch
EN S R Output
0 0 0 No Change
0 0 1 No Change
0 1 0 No Change
0 1 1 No Change
1 0 0 No Change
1 0 1 Q=0
1 1 0 Q=1
1 1 1 Invalid
Example 1 : assume initially Q is RESET

Example 2: assume initially Q is RESET.

S

EN

Q
 FLIP FLOPS
 A Flip Flop is a memory element that is capable of storing one bit of information.

 A flip flop can maintain a binary state for an unlimited period of time as long as power is supplied to the circuit. Or until it is
directed by an input signal to switch states.

 A flip flop is also called as Synchronous Bistable devices because it has two stable states either 0 or 1.

 Synchronous means that the output changes state only at a specified point on the triggering input called clock(CLK), control
input; C , that is changes in the output occurs in synchronization with the clock.
• The primary difference between a flip-flop and latch is the EN/CLOCK input.

• The flip-flop’s CLOCK input is edge sensitive, meaning the flip-flop’s output changes on the edge (rising or falling) of the
CLOCK input.

• The latch’s EN input is level sensitive, meaning the latch’s output changes on the level (high or low) of the EN input.
Triggering methods of flip flop
 Triggering means provide clock pulse to change the state of memory.
 The state of a flip flop is switched by a momentary change in the input signal.
 This momentary change is called a trigger and the triggering input called clock.
Types of triggering
1. Edge triggering:

 Edge triggering contains either positive going transition(PGT) or negative going transition(NGT)
2. Level triggering: output can change with respect to input whenever clock is maintained at the selected level( at
high or low level).
 Difference between latch and flip-flop
Latch Flip-flop
It is structured based on logic gates block It is structured based on blocks of latch and logic gates
It doesn’t have clock in its internal circuits It has clock
It checks input continuously and changes output It checks input continuously and changes output with
correspondingly respect to clock signal
Sensitive to input signal only Sensitive to input and clock signal
It is level trigger It is edge trigger
It is asynchronous circuit It is synchronous circuit since clock is used as
synchronization
It requires less power It requires more power since clock is used
Latch is faster propagation delay time It is slower
Less complex in designing More complex in designing
Types of flip-flops:-
1. S-R Flip-flop
2. D flip flop
3. J-K flip flop
4. T flip flop
1. SR Flip Flop
 The S and R inputs of the S-R flip-flop are called synchronous inputs because data on this inputs are transferred to the flip
flop’s output only on the triggering edge of the clock pulse.
 SR flip flop is the simplest type of flip flops.
 It stands for Set- Reset flip flop.

Construction of SR Flip Flop By Using NAND Latch

Clock S R Q Q’ status
0 x x Q Q’ No change
1 0 0 Q Q’ No change
1 0 1 0 1 RESET
1 1 0 1 0 SET
1 1 1 0 0 invalid

truth table of SR flip flop

Clock=1 means either PGT or NGT
Remember, the flip flop cannot change state except on the triggering edge of the a clock pulse.
Example: Determine the output waveform for Q. The given inputs are S, R and clock. Assume initially Q is zero.
Example: determine Q and Q’, assume initially Q=0.
Example: determine the output Q and Q’. Assume initially Q=0
 D flip flop
 In SR NAND FLIP FLOP circuit, the undefined input condition of S = “1" and R = “1" is forbidden(invalid).
 It is the drawback of the SR flip flop.
 We connect the inverter between on the Reset inputs for producing another modified SR type of flip flop circuit called D flip
flop, (Data or Delay flip flop) to reject the invalid state.
 The D flip flop is the most important flip flop from other clocked types. It ensures that at the same time, both the inputs, i.e., S
and R, are never equal to 1.
 The Delay flip-flop is designed using a gated SR flip-flop with an inverter connected between the inputs allowing for a single
input D(Data).
 In D flip flop, the single input "D" is referred to as the "Data" input.
 When the data input is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would change and become reset.
Truth table
Clock D Q Q’ status
0 x Q Q’ No change
1 0 0 1 RESET
1 1 1 0 SET

Examples: determine the output Q and Q’ for the given inputs D and CLOCK. Assume initially Q is RESET.
Exercise:
 J-K FLIP FLOP
 The JK flip flop is one of the most used flip flops in digital circuits.
 JK flip flop full form is Jack-Kilby flip flop. It is named after its inventor Jack Kilby.
 this is a modified version of an S-R flip-flop with no “invalid” or “illegal” output state.
 The JK Flip Flop removes these two drawbacks of SR Flip Flop.
 The cross-coupling of the SR flip-flop permits the previous invalid condition of (S = "1", R = "1") to be used to produce the
"toggle action" as the two inputs are now interlocked.
Truth table
Clock J K Q Q’ status
0 x x Q Q’ No change
1 0 0 Q Q’ No change
1 0 1 0 1 RESET
1 1 0 1 0 SET
1 1 1 Q’ Q Toggle

Table: Truth table for both positive edge triggering and negative edge triggering
Race Around Condition In JK Flip-flop
 For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as long as CLK is high, which
makes the output of the flip-flop unstable or uncertain.
 Toggle means switch between two state.

 Race around condition means toggling is happening at the output many a time within a single clock period.
 This problem is called race around condition in J-K flip-flop.
 This problem (Race Around Condition) can be avoided by ensuring that the clock input is at logic “1” only for a very short
time, use edge trigger and use master-slave flip flop.
Example: Assume initially Q is RESET state
Example: Determine the output waveform for the following. Assume initially Q is zero.

Exercise: assume initially Q is reset

Exercise:
 T FLIP-FLOP
 We can construct the "T Flip Flop" by making changes in the "J-K Flip Flop“ if we need toggled output only..
 T Flip-Flop is a single input logic circuit that holds or toggles its output according to the input state.
 T (toggle) flip-flop has two inputs: a clock and a T input. When T is 0, clock pulses have no effect on the output.
 When T is 1, when a clock pulse arrives, the output toggles.

Logic Symbol of Positive edge triggered T flip-flop circuit diagram of T flip flop

Clock T Q Q’ status
0 x Q Q’ No change
1 0 Q Q’ No change
1 1 Q’ Q Toggle
Truth table truth table Positive edge triggered T flip-flop
 Master-Slave JK flip flop
 The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series configuration.
 Out of these, one acts as the “master” and the other as a “slave”.
 The output from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs
of the master flip flop.
 The inverter is connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop.
 In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop then it
becomes 0 for slave flip flop.
Working of a master slave flip flop
• When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system. The slave flip-flop is
isolated until the CP goes to 0.
• When the CP goes back to 0, information is passed from the master flip-flop to the slave and output is obtained.
• Firstly, the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so the master
responds before the slave.
• If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the negative transition of the clock
forces the slave to reset, thus the slave copies the master.
• If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition of the clock sets
the slave, copying the master.
• If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative transition of the
clock.
• If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
J=K=1 and CLK=1, Qm=active and Q=memory
J=K=1 and CLK=1 , Qm=memory and Q=active
Example: the following waveform is only for the case of J=K=1

Waveform diagram of master-slave flip-flop