SN74HC126, SN54HC126

[Link] SN74HC126,
SCLS103F – MARCH SN54HC126
1984 – REVISED APRIL 2021
SCLS103F – MARCH 1984 – REVISED APRIL 2021

SNx4HC126 Quadruple Buffers with 3-State Outputs

1 Features 3 Description
• Buffered inputs This device contains four independent buffers with
• Wide operating voltage range: 2 V to 6 V 3-state outputs. Each gate performs the Boolean
• Wide operating temperature range: function Y = A in positive logic.
–40°C to +85°C
Device Information(1)
• Supports fanout up to 10 LSTTL loads
PART NUMBER PACKAGE BODY SIZE (NOM)
• Significant power reduction compared to LSTTL
logic ICs SN74HC126D SOIC (14) 8.70 mm × 3.90 mm
SN74HC126DB SSOP (14) 6.50 mm × 5.30 mm
2 Applications SN74HC126N PDIP (14) 19.30 mm × 6.40 mm
• Enable digital signals SN74HC126NS SO (14) 10.20 mm × 5.30 mm
SN74HC126PW TSSOP (14) 5.00 mm × 4.40 mm
SN54HC126J CDIP (14) 21.30 mm × 7.60 mm
SN54HC126FK LCCC (20) 8.90 mm × 8.90 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

1OE 1 14 VCC
1A 2 13 4OE
1Y 3 12 4A
4 11
2OE 4Y
2A 5 10 3OE
2Y 6 9 3A
7 8
GND 3Y

Functional pinout

An©IMPORTANT
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Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagram......................................... 10
2 Applications..................................................................... 1 8.3 Feature Description...................................................10
3 Description.......................................................................1 8.4 Device Functional Modes..........................................11
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 12
5 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 12
Pin Functions.................................................................... 3 9.2 Typical Application.................................................... 12
6 Specifications.................................................................. 4 10 Power Supply Recommendations..............................14
6.1 Absolute Maximum Ratings........................................ 4 11 Layout........................................................................... 14
6.2 Recommended Operating Conditions.........................4 11.1 Layout Guidelines................................................... 14
6.3 Thermal Information....................................................4 11.2 Layout Example...................................................... 14
6.4 Electrical Characteristics - 74..................................... 5 12 Device and Documentation Support..........................15
6.5 Electrical Characteristics - 54..................................... 5 12.1 Documentation Support.......................................... 15
6.6 Switching Characteristics - 74.....................................6 12.2 Related Links.......................................................... 15
6.7 Switching Characteristics - 54.....................................7 12.3 Support Resources................................................. 15
6.8 Operating Characteristics........................................... 7 12.4 Trademarks............................................................. 15
6.9 Typical Characteristics................................................ 7 12.5 Electrostatic Discharge Caution..............................15
7 Parameter Measurement Information............................ 9 12.6 Glossary..................................................................15
8 Detailed Description......................................................10 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 10 Information.................................................................... 15

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2003) to Revision F (April 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated to new data sheet standards................................................................................................................ 1
• Increased D (86 to 151.7), DB (96 to 108.0), NS (76 to 122.6), and PW (113 to 151.7); decreased N (80 to
62.5) °C/W.......................................................................................................................................................... 4

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5 Pin Configuration and Functions

1A 1OE NC VCC 4OE
1OE VCC
1A 4OE 3 2 1 20 19
1Y 4 18 4A
1Y 4A
NC 5 17 NC
2OE 4Y
2OE 6 16 4Y
2A 3OE
2Y 3A NC 7 15 NC

GND 3Y 2A 8 14 3OE
9 10 11 12 13

Figure 5-1. D, DB, N, NS, PW, or J Package 2Y GND NC 3Y 3A

14-Pin SOIC, SSOP, PDIP, SO, TSSOP, or CDIP Figure 5-2. FK Package
Top View 20-Pin LCCC
Top View

Pin Functions
PIN
D, DB, N, I/O DESCRIPTION
NAME NS, PW, or FK
J
1OE 1 2 Input Channel 1, Output Enable
1A 2 3 Input Channel 1, Input A
1Y 3 4 Output Channel 1, Output Y
2OE 4 6 Input Channel 2, Output Enable
2A 5 8 Input Channel 2, Input A
2Y 6 9 Output Channel 2, Output Y
GND 7 10 — Ground
3Y 8 12 Output Channel 3, Output Y
3A 9 13 Input Channel 3, Input A
3OE 10 14 Input Channel 3, Output Enable
4Y 11 16 Output Channel 4, Output Y
4A 12 18 Input Channel 4, Input A
4OE 13 19 Input Channel 4, Output Enable
VCC 14 20 — Positive Supply
1, 5, 7, 11, 15,
NC — Not internally connected
17

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA
TJ Junction temperature(3) 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
tt Input transition time VCC = 4.5 V 500 ns
VCC = 6 V 400
SN54HC126 –55 125
TA Operating free-air temperature °C
SN74HC126 –40 85

6.3 Thermal Information

SN74HC126
THERMAL METRIC(1) D (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Junction-to-ambient thermal
RθJA 133.6 108.0 62.5 122.6 151.7 °C/W
resistance
Junction-to-case (top) thermal
RθJC(top) 89 57.8 50.2 81.8 79.4 °C/W
resistance
Junction-to-board thermal
RθJB 89.5 58.3 42.2 83.8 94.7 °C/W
resistance
Junction-to-top characterization
ΨJT 45.5 18.0 29.8 45.4 25.2 °C/W
parameter

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SN74HC126
THERMAL METRIC(1) D (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Junction-to-board
ΨJB 89.1 57.6 42.0 83.4 94.1 °C/W
characterization parameter
Junction-to-case (bottom)
RθJC(bot) N/A N/A N/A N/A N/A °C/W
thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.4 Electrical Characteristics - 74

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C -40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9
IOH = –20 µA 4.5 V 4.4 4.499 4.4
High-level VI = VIH
VOH 6V 5.9 5.999 5.9 V
output voltage or VIL
IOH = –6 mA 4.5 V 3.98 4.3 3.84
IOH = –7.8 mA 6V 5.48 5.8 5.34
2V 0.002 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1
Low-level output VI = VIH
VOL 6V 0.001 0.1 0.1 V
voltage or VIL
IOL = 6 mA 4.5 V 0.17 0.26 0.33
IOL = 7.8 mA 6V 0.15 0.26 0.33
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 µA
current
Three-state VO = VCC
IOZ 6V ±0.01 ±0.5 ±5 µA
leakage current or 0
VI = VCC
ICC Supply current IO = 0 6V 8 80 µA
or 0
Input
Ci 2 V to 6 V 3 10 10 pF
capacitance

6.5 Electrical Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9 1.9
IOH = –20
4.5 V 4.4 4.499 4.4 4.4
µA
6V 5.9 5.999 5.9 5.9
High-level VI = VIH or
VOH V
output voltage VIL IOH = –6
4.5 V 3.98 4.3 3.84 3.7
mA
IOH = –7.8
6V 5.48 5.8 5.34 5.2
mA

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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 0.002 0.1 0.1 0.1
IOL = 20
4.5 V 0.001 0.1 0.1 0.1
µA
Low-level VI = VIH or 6V 0.001 0.1 0.1 0.1
VOL V
output voltage VIL
IOL = 6 mA 4.5 V 0.17 0.26 0.33 0.4
IOL = 7.8
6V 0.15 0.26 0.33 0.4
mA
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 ±1 µA
current
Three-state
VO = VCC
IOZ leakage 6V ±0.01 ±0.5 ±5 ±10 µA
or 0
current
VI = VCC or
ICC Supply current IO = 0 6V 8 80 160 µA
0
Input 2 V to
Ci 3 10 10 10 pF
capacitance 6V

6.6 Switching Characteristics - 74

over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
TEST
PARAMETER FROM TO VCC 25°C –40°C to 85°C UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX
2V 47 120 180
CL = 50 pF 4.5 V 14 24 36 ns
6V 11 20 31
tpd Propagation delay A Y
2V 67 150 225
CL = 150 pF 4.5 V 19 30 45 ns
6V 15 25 39
2V 57 120 180
CL = 50 pF 4.5 V 16 24 36 ns
6V 12 20 31
ten Enable delay OE Y
2V 100 135 202
CL = 150 pF 4.5 V 20 27 40 ns
6V 17 23 36
2V 35 120 180
tdis Disable delay OE Y CL = 50 pF 4.5 V 17 24 36 ns
6V 15 20 31
2V 28 60 90
CL = 50 pF 4.5 V 8 12 18 ns
6V 6 10 15
tt Transition-time Y
2V 45 210 315
CL = 150 pF 4.5 V 17 42 63 ns
6V 13 36 53

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6.7 Switching Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
TEST
PARAMETER FROM TO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 47 120 180 150
CL = 50 pF 4.5 V 14 24 36 30 ns
6V 11 20 31 26
tpd Propagation delay A Y
2V 67 150 225 188
CL = 150 pF 4.5 V 19 30 45 38 ns
6V 15 25 39 33
2V 57 120 180 150
CL = 50 pF 4.5 V 16 24 36 30 ns
6V 12 20 31 26
ten Enable delay OE Y
2V 100 135 202 169
CL = 150 pF 4.5 V 20 27 40 36 ns
6V 17 23 36 30
2V 35 120 180 150
tdis Disable delay OE Y CL = 50 pF 4.5 V 17 24 36 30 ns
6V 15 20 31 26
2V 28 60 90 75
CL = 50 pF 4.5 V 8 12 18 15 ns
6V 6 10 15 13
tt Transition-time Y
2V 45 210 315 265
CL = 150 pF 4.5 V 17 42 63 53 ns
6V 13 36 53 45

6.8 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 2 V to 6 V 45 pF
per gate

6.9 Typical Characteristics

TA = 25°C

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7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)

Figure 6-1. Typical output voltage in the high state Figure 6-2. Typical output voltage in the low state
(VOH) (VOL)

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7 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.

Test VCC VCC

90% 90%
Point Input
S1 10% 10%
0V
RL tr(1) tf(1)
From Output
Under Test
VOH
CL(1) S2 90% 90%
Output
10% 10%
VOL
tr(1) tf(1)
A. CL= 50 pF and includes probe and jig capacitance.
A. tt is the greater of tr and tf.
Figure 7-1. Load Circuit
Figure 7-2. Voltage Waveforms Transition Times
VCC
Output
50% 50%
Control
0V
(3) (4)
tPZL tPLZ
§ 9CC
Output
Waveform 1 50%
S1 at VLOAD(1) 10%
VOL
tPZH(3) tPHZ(4)
VOH
Output 90%
Waveform 2 50%
S1 at GND(2)
§0V
A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays

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8 Detailed Description
8.1 Overview
This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y =
A in positive logic.
8.2 Functional Block Diagram

xOE

xA xY

8.3 Feature Description

8.3.1 Balanced CMOS 3-State Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The SN74HC126 can drive a load with a total capacitance less than or equal to the maximum load listed in
the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the
provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between
the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
3-State outputs can be placed into a high-impedance state. In this state, the output will neither source nor sink
current, and leakage current is defined by the IOZ specification in the Electrical Characteristics - 74. A pull-up
or pull-down resistor can be used to ensure that the output remains HIGH or LOW, respectively, during the
high-impedance state.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground
in parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is
calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input
leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the
Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy
input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to
the standard CMOS input.

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8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.

VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

Table 8-1. Function Table
INPUTS OUTPUT
OE A Y
L X Z
H L L
H H H

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

In this application, a 3-state buffer is used to enable or disable a data connection as shown in Figure 9-1. It
is common to see all four channels of a device used together for controlling a 4-bit data bus, however each
channel of the device can be used independently. Unused channels should have the inputs terminated at ground
or VCC and the output left unconnected.
When the output of the device is active, the data signal will be replicated at the output. When the output of
the device is disabled, the output will be in a high-impedance state, and the output voltage will be determined
by the circuit connected to the output pin. This circuit is most commonly used when a bus must be completely
disabled. One example of this situation is when the circuitry connected to the output is to be powered off for an
extended period of time to save system power, and the inputs to that circuitry cannot have a voltage present due
to protective clamp diodes.
9.2 Typical Application

System
Controller

OE

A Y
Data Output

Figure 9-1. Typical application schematic

9.2.1 Design Requirements

[Link] Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC126 plus the maximum supply current, ICC, listed in the Electrical Characteristics - 74. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.

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[Link] Input Considerations

Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HC126, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC126 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions.
Refer to Section 8.3 for additional information regarding the inputs for this device.
[Link] Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics - 74. Similarly,
the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics - 74.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC126
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves

Data

Output

OE

Figure 9-2. Typical application timing diagram

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to the
0.1 F device

1OE 1 14 VCC Unused

1A 2 13 4OE inputs tied
to VCC
1Y 3 12 4A
Unused
2OE 4 11 4Y output left
floating
2A 5 10 3OE
2Y 6 9 3A
Avoid 90°
corners for GND 7 8 3Y
signal lines

Figure 11-1. Example layout for the SN74HC126

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN74HC126 SN54HC126
 PACKAGE OPTION ADDENDUM

[Link] 27-Sep-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

5962-86848012A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-
86848012A
SNJ54HC
126FK
5962-8684801CA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8684801CA
SNJ54HC126J
SN54HC126J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC126J
SN54HC126J.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC126J
SN74HC126D Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 HC126
SN74HC126DBR Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126DBR.A Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126DR.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126DR1G4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126DR1G4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126DT Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 HC126
SN74HC126N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC126N
SN74HC126N.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC126N
SN74HC126NSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126NSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126PW Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI -40 to 85 HC126
SN74HC126PWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126PWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126PWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126PWRG4.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC126
SN74HC126PWT Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI -40 to 85 HC126
SNJ54HC126FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-
86848012A
SNJ54HC
126FK

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 27-Sep-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

SNJ54HC126FK.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-
86848012A
SNJ54HC
126FK
SNJ54HC126J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8684801CA
SNJ54HC126J
SNJ54HC126J.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8684801CA
SNJ54HC126J

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

[Link] 27-Sep-2025

OTHER QUALIFIED VERSIONS OF SN54HC126, SN74HC126 :

• Catalog : SN74HC126
• Military : SN54HC126

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

[Link] 26-Sep-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC126DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC126NSR SOP NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC126PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC126PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 26-Sep-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC126DBR SSOP DB 14 2000 353.0 353.0 32.0
SN74HC126NSR SOP NS 14 2000 353.0 353.0 32.0
SN74HC126PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC126PWRG4 TSSOP PW 14 2000 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 26-Sep-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-86848012A FK LCCC 20 55 506.98 12.06 2030 NA
SN74HC126N N PDIP 14 25 506 13.97 11230 4.32
SN74HC126N N PDIP 14 25 506 13.97 11230 4.32
SN74HC126N.A N PDIP 14 25 506 13.97 11230 4.32
SN74HC126N.A N PDIP 14 25 506 13.97 11230 4.32
SNJ54HC126FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54HC126FK.A FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

[Link]
 EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

[Link]
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

[Link]
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

[Link]
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

[Link]
 PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

[Link]
 EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

[Link]
 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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