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Cadence Genus & Modus DFT Guide

This document outlines the steps to synthesize and prepare for DFT using Cadence Genus and Modus. It includes gathering RTL files, preparing SDC constraints, creating a Genus TCL script for synthesis, and performing DFT insertion in Modus. Additionally, it lists the necessary files and offers further assistance with TCL scripts and testbench simulation.

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26ddd
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130 views2 pages

Cadence Genus & Modus DFT Guide

This document outlines the steps to synthesize and prepare for DFT using Cadence Genus and Modus. It includes gathering RTL files, preparing SDC constraints, creating a Genus TCL script for synthesis, and performing DFT insertion in Modus. Additionally, it lists the necessary files and offers further assistance with TCL scripts and testbench simulation.

Uploaded by

26ddd
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

✅ 2.

Steps to Run This in Cadence Genus + Modus


You want to synthesize and prepare for DFT using Cadence. Here's how.

🧩 Step 1: Gather RTL Files

List all Verilog files (and submodules) in a file called riscv_file_list.tcl:

tcl
CopyEdit
ALU/ALU.v
ControlUnit/Control.v
DataMemory/DataMemory.v
Datapath/Datapath.v
InstructionMemory/InstructionMemory.v
RegisterFile/RegisterFile.v
Processor/Processor.v

(You do not include testbenches like Processor_tb.v for synthesis.)

🛠️Step 2: Prepare SDC Constraints

Create riscv_constraints.sdc with a clock:

sdc
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create_clock -name clk -period 10 [get_ports clk]
set_input_delay 2 -clock clk [all_inputs]
set_output_delay 2 -clock clk [all_outputs]

🧠 Step 3: Genus TCL Script (riscv_genus.tcl)


tcl
CopyEdit
# Load libraries
set_db library {your_lib_file.lib}
set_db lef_library {your_lef_file.lef}

# Read RTL
read_hdl -sv -f riscv_file_list.tcl
elaborate
read_sdc riscv_constraints.sdc

# Synthesis
synthesize -to_mapped
write_hdl > riscv_synth.v
write_sdf > [Link]
report_area > [Link]
report_timing > [Link]
Then run:

bash
CopyEdit
genus -files riscv_genus.tcl

🔍 Step 4: DFT Insertion (in Modus)

After synthesis, move to Cadence Modus for scan insertion:

tcl
CopyEdit
read_netlist riscv_synth.v
read_liberty -both your_lib.lib
read_sdc riscv_constraints.sdc
set_db design_name Processor

# Define scan signals


set_scan_configuration -style multiplexed_flipflop
set_dft_signal -type ScanEnable -port scan_en
set_dft_signal -type ScanIn -port scan_in
set_dft_signal -type ScanOut -port scan_out
create_test_structure -all
insert_dft

# Save netlist and reports


write_netlist -output riscv_dft.v
report_scan_chain > scan_chain.rpt
report_dft_coverage > [Link]

🧾 Summary of Files You Need


File Purpose
riscv_file_list.tcl List of Verilog RTL files
riscv_constraints.sdc Timing and I/O constraints
riscv_genus.tcl Synthesis script
riscv_dft.tcl Scan insertion script (optional)

✅ What’s Next?
Let me know if you want:

 A full ready-made TCL script for your synthesis and DFT


 To add scan ports to the Processor.v module
 Help with testbench simulation using Xcelium

I can generate any of these for you.

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