CISC – Complex Instruction Set Computer

• CISC is a computer architecture in which the processor supports a large

number of complex instructions.
• Each instruction can perform multiple low-level operations, such as
loading data from memory, performing an arithmetic operation, and storing
the result back to memory — all in a single instruction.

CISC vs RISC Architectures CISC instruction

ADD A, B
This might read A and B directly from memory, add them, and store
the result back — all in one instruction.

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Main Objectives of CISC: Characteristics of CISC

1. Large Instruction Set
•CISC processors may have hundreds of instructions
• Reduce the number of instructions in a program •Some instructions are very complex and take many steps to execute
• Make programming easier (especially in assembly)
2. Variable-Length Instructions
• Reduce memory usage by writing fewer lines of code
•Instructions can be 1 byte, 2 bytes, or more
•This makes instruction decoding slow and complex

3. Memory-to-Memory Operations
•Many CISC instructions can access memory directly

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4. Multiple Clock Cycles
•A single instruction may take multiple clock cycles to complete RISC (Reduced Instruction Set Computer)
5. Microprogrammed Control Unit • RISC is a CPU design approach that uses simple instructions,
•CISC processors usually use a microprogrammed control unit fixed length format, and many registers to improve speed
•This increases hardware complexity but supports complex instructions and efficiency.
• RISC is a computer architecture designed to use a small set of
6. Many Addressing Modes simple and fast instructions. Each instruction is designed to
•Supports many ways to access memory (direct, indirect, indexed, etc.) execute in one clock cycle (ideally) and only load and store
instructions access memory.
7. Difficult to Pipeline
• one machine instruction per machine cycle. A machine
•Because instructions vary in length and execution time, pipelining is inefficient cycle is defined to be the time it takes to fetch two operands
Examples of CISC: from registers, perform an ALU operation, and store the result in
•Intel x86 family (8086, 80286, Pentium, etc.) a register.
•VAX • Example: ARM, MIPS, SPARC, RISC-V
•Motorola 68000
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Main Objective of RISC: Basic Principles of RISC

1. Load/Store Architecture
• Only two types of instructions can access memory:
• Increase execution speed • LOAD – Transfers data from memory to register
• Improve performance via pipelining • STORE – Transfers data from register to memory
• Simplify hardware design • All other operations are done between registers
• Instead of performing many things in one instruction (like CISC), LOAD R1, A
RISC uses many simple instructions to perform a task. LOAD R2, B
ADD R3, R1, R2
STORE R3, C

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 2. Fixed-Length Instructions 5. Hardwired Control Unit
• All instructions are same length (usually 32 bits) • Uses a hardwired control unit instead of microprogramming
• This allows: • This is faster and more efficient
• Faster fetching
6. Easy Pipelining
• Easier decoding
• Efficient pipelining
3. Large Number of Registers
• RISC processors have more general-purpose registers
• This:
• Reduces memory access
• Increases speed.
4. Simple Addressing Modes
• Very few addressing modes (usually 3–5)
• Makes circuit design simple

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• Advantages of CISC
• Less code required
Advantages of RISC
•Faster execution • Easier for assembly language programming
•Simple hardware • More powerful single instructions
•Low power consumption
•Easy pipelining • Disadvantages of CISC
•Better performance per watt • Complex hardware
• Slower execution
Disadvantages of RISC
•More lines of code • High power consumption
•Requires better compiler optimization • Difficult pipelining
•Higher memory usage

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RISC vs RISC Architectures
Control unit Usually microprogrammed Usually hardwired

CISC (Complex Instruction RISC (Reduced Instruction Addressing modes Many addressing modes Few addressing modes
Feature
Set Computer) Set Computer)
Smaller code (due to Larger code (more
Code size
Supports a large number of Supports small number of complex instructions) instructions needed)
Meaning
complex instructions simple instructions
Difficult (varied instruction
Pipelining Easy & efficient
Instruction length Variable length instructions Fixed length instructions length)

One instruction may take Usually one clock cycle per Power consumption Higher Lower
Execution time
multiple clock cycles instruction
Performance Slower due to complexity Faster due to simplicity

Uses Load/Store architecture

Instructions can directly Intel x86, VAX, Motorola ARM, MIPS, SPARC, RISC-
Memory access (only LOAD/STORE access Examples
access memory 68000 V
memory)
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RISC designs may benefit from the inclusion of some CISC

features.
CISC designs may benefit from the inclusion of some RISC
features.
The result is that the more recent RISC designs, notably the
PowerPC, are no longer “pure” RISC and the more recent CISC
designs, notably the Pentium II and later Pentium models, do
incorporate some RISC characteristics.

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