168 Introduc on to Embedded Systems

Programming the 8051

6 Microcontroller

LEARNING OBJECTIVES

LO 1 Learn how to program the 8051 microcontroller using Assembly Language

Discuss the direct, indirect, register, immediate and indexed addressing modes
supported by 8051. Learn about register instruc ons and register specific
instruc ons supported by 8051
LO 2 Discuss what an instruc on and instruc on set is
Know the different instruc ons supported by 8051 instruc on set architecture
Describe the internal and external data transfer instruc ons, data exchange
instruc ons, Stack memory related data transfer instruc ons and code memory
read instruc ons supported by 8051
Learn the addi on and subtrac on, mul plica on and division, increment and
decrement, and decimal adjust instruc ons supported by 8051
Iden fy the different logical instruc ons (Rotate, Shi , Complement, etc.)
supported by 8051
Understand the bit manipula on instruc ons supported by 8051
List the different program execu on control transfer instruc ons supported by
8051. Learn the uncondi onal program control transfer instruc ons (Jump,
Subrou ne Call, return from ISR and func on call, etc.) supported by 8051
Learn the condi onal program control transfer instruc ons (Decrement and
Jump if non zero, Compare and jump if not equal, Jump if carry flag is set or
not set, Jump if a specified bit is set or not, etc.) supported by 8051

As you learned in the basic 8085/8088 microprocessor class, an Instruction consists of two parts namely;
Opcode and Operand(s). The opcode tells the processor what to do on executing an instruction. The
operand(s) is the parameter(s) required by opcode to complete the action. The term Instruction Set refers to
the set of instructions supported by a processor/controller architecture. The instruction set of 8051 family
microcontroller is broadly classified into five categories namely; Data transfer instructions, Arithmetic
 Programming the 8051 Microcontroller 169

instructions, Logical instructions, Boolean instructions and Program control transfer instructions. Before
going to the details of each type of instructions, it is essential to understand the different addressing modes
supported by the 8051 microcontroller.

6.1 DIFFERENT ADDRESSING MODES SUPPORTED BY 8051

The term ‘addressing mode’ refers to “How the operand is specified in an LO 1 Learn how to
instruction” along with opcode. The operand may be one or a combination program the 8051
of the following–memory location(s), contents of memory location(s), microcontroller using
register(s), or constant. Depending on the type of operands, the addressing Assembly Language
modes are classified as follows.

6.1.1 Direct Addressing

The operand is specified as an 8 bit memory address. For 8051 processor, only the lower 128 byte internal
data memory and the SFRs are directly accessible.
For example, MOV A, 07H (Moves the content of memory location 07H to the accumulator. 07H refers
to the address of data memory at location 7. If memory location 07H contains the value 255, executing this
instruction will modify the content of A to 255) uses MOV as opcode and A, 07H as operands (Fig. 6.1).

Registers Data memory

A Memory
address
B
R0
07 H 255 (FFH)

R7

Fig. 6.1 Illustration of direct memory addressing (E.g. MOV A, 07H)

6.1.2 Indirect Addressing

As the name indicates, the operand is specified indirectly in indirect addressing. A register is used for holding
the address of the memory variable on which the operations are to be performed. The indirect operations are
performed using @register technique. For 8-bit internal data memory operations, register R0 or R1 is used
as the indirect addressing register. The whole 256 bytes (if present physically on the chip) can be accessed
by indirect addressing.
E.g. MOV R0, #55H ; Load R0 with 55H, The address of mem loc
MOV A,@R0 ; Load Accumulator with the contents of the-
; memory location pointed by R0
Register R0 is loaded with 55H (85 in decimal) on executing the first instruction. Here R0 is used as
the indirect addressing register and data memory 55H is the memory variable on which the operations are
performed. Executing the second instruction moves the contents of memory address 55H to the accumulator.
This can be interpreted as MOV A, content @Memory Address 55H. Suppose 55H contains 255, executing
the second instruction will load the accumulator with 255 (Fig. 6.2).
170 Introduc on to Embedded Systems

Registers Data memory

A Memory
address
B
R0 55H
55H 255 (F FH )

R7

Fig. 6.2 Illustration of indirect memory addressing with 8bit indirect register (E.g. MOV A, @R0)

Among the scratchpad registers R0 to R7, only R0 and R1 can be used for indirect addressing. For 16bit
external data memory/memory mapped register operations, 16bit register DPTR is used as the indirect
addressing register. The whole 64K bytes of the external memory (if present physically on chip) can be
accessed by indirect addressing.
E.g. MOV DPTR, #0055H ; Load DPTR register with 0055H, The-
; address of the memory location
MOVX A,@DPTR ; Load Accumulator with the contents-
; of the memory location pointed by DPTR
Executing these two instructions moves the content of external data memory at address 0055H to the
Accumulator (Fig. 6.3).

Registers External data memory

A Memory
address
B
DPH 00H
DPL 55H 0055H 255 (FFH)

Fig. 6.3 Illustration of Indirect memory addressing with 16bit Indirect Register (E.g. MOVX A, @DPTR)

Indirect addressing is same as the pointer concept in C Programming. Indirect addressing is commonly
used for operations similar to pointer based operations in C Programming like array, external memory access,
etc.

6.1.3 Register Addressing

Register addressing is of two types. In some instructions, the register operand is implicitly specified by
some bits of the opcode. These types of instructions are referred as Register Instructions. Some instructions
implicitly work on certain specific registers. They are known as Register Specific Instructions.
 Programming the 8051 Microcontroller 171

[Link] Register Instruc ons

In register instructions, the register operand is specified by some bits of the opcode itself. If scratchpad
registers R0 to R7 are used as operands, they can be specified along with the opcode by using the last 3 bits
of the opcode. Such instructions are code efficient since the opcode itself specifies one operand; it eliminates
the need for storing the operand as a byte in code memory and also saves the time in fetching the operand.
Generally register variable access is faster than general memory access.
E.g. MOV R0, 01H
This is a two byte instruction where the first operand R0 is indicated by the last 3 bits of the opcode
byte.
Register to register data transfer is not allowed and hence instructions like MOV R1, R2 are invalid.
[Link] Register Specific Instruc ons
Some of the 8051 instructions are specific to certain registers. Examples are accumulator and data pointer
specific instructions.
E.g. ADD A, #50
During the assembly process, this instruction is converted to a two byte instruction in which A is implicitly
specified by the opcode corresponding to ADD.

6.1.4 Immediate Constants

Constants can be an operand for some instructions. If an instruction makes use of a constant data as the
operand, the type of addressing is called immediate addressing. In immediate addressing, a constant follows
the opcode as operand in code memory. An immediate constant is represented with a leading ‘#’ symbol in
the assembly code. A leading ‘#’ tells the assembler that the operand is a constant. For example, if you want
to load accumulator with the constant 9, the following instruction will do it.
MOV A, #09

6.1.5 Indexed Addressing

Indexed addressing is used for program memory access. This addressing mode is used for reading look
up table from code memory and is Read Only. A 16bit register is used for holding the base address of the
lookup table. The offset of the table entry from which the data to be retrieved is loaded in Accumulator. The
instruction MOVC is used for indexed addressing.
E.g. MOV DPTR, #2008H
MOV A, #00
MOVC A, @A+DPTR
The above example assumes that the lookup table is at memory location 2008H and so the base address
of the lookup table is 2008H. The first instruction loads the base pointer address 2008H to the base pointer
register DPTR. The table index is provided by the accumulator register. To access the corresponding entry of
the table, load accumulator with the offset from the base address. For accessing the base element the offset
should be 0. The second instruction loads the offset to accumulator. For example, if you want to access
the entry which is just above the base entry, the accumulator should be loaded with 1. Executing the third
instruction moves the content of the table entry at memory location 0+2008H to the accumulator. Since the
172 Introduc on to Embedded Systems

offset address register, accumulator, is an 8bit register, the maximum size of the look up table is 256 bytes
(Base address + 0 to Base address + 255).
Another register, which is 16bit wide, used for indexed addressing is Program Counter (PC). The only
difference in using PC for indexed addressing when compared to DPTR is that the PC is not available to user
for direct manipulation and user cannot directly load the desired base address to the PC register by a MOV
instruction as in the case of DPTR. Instead the desired address is loaded to the PC by diverting the program
flow to the location where the Lookup table is held in the code memory by using a CALL instruction.
First the desired table index is loaded to the accumulator register and a call is made to the location where
the lookup table is stored. For this type of tables, the index should be within 1 to 255 (including both). 0
cannot be used as an index since the execution of MOVC A,@A+DPTR increments the PC to the address of
the RET instruction’s memory location. If you use a 0 index along with the PC, the contents retrieved will
be the binary data corresponding to the RET instruction. Code memory lookup tables are usually used for
storing string constants and other configuration data. Another use of indexed addressing is the ‘case jump’
instruction in 8051. Here the jump instruction’s destination address is calculated as the sum of the base
pointer (PC) and the Accumulator data.

Example 1
Write an assembly program to display the numbers from 0 to 9 on a 7-segment common-anode LED display
which is connected to Port 2 of the 8051. The seven segment codes for displaying the numerals 0 to 9 on the
common anode LED is stored as lookup table in the code memory starting at 0050H. Use DPTR register for
holding the base address of the table.
Please refer to the section on 7-segment LED Display given in Chapter 2 for more details on 7-segment
LED Display. Figure 6.4 illustrates the interfacing of common anode LED Display with Port 2 of 8051.

VCC Vcc
AT89C51
Common anode
R

7-segment LED display

DP G F E D C B A
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
GND P2.0

Fig. 6.4 Circuit for interfacing 7-segment LED display with 8051
 Programming the 8051 Microcontroller 173

Now we need to design the different bit patterns (code) to be outputted to the Port 2 pins to display the
numbers from 0 to 9 on the LED Display. The following table explains the same. Refer to the LED segment
arrangement diagram given earlier for clarification.

Digit DP G F E D C B A Code
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 (Hex)
0 1 1 0 0 0 0 0 0 C0
1 1 1 1 1 1 0 0 1 F9
2 1 0 1 0 0 1 0 0 A4
3 1 0 1 1 0 0 0 0 B0
4 1 0 0 1 1 0 0 1 99
5 0 0 0 1 0 0 1 0 12
6 0 0 0 0 0 0 1 0 02
7 1 1 1 1 1 0 0 0 F8
8 1 0 0 0 0 0 0 0 80
9 1 0 0 1 0 0 0 0 90

Now the codes for displaying the digits and the port interfacing for the LED display is complete. The next
step required for setting up the decimal counter for counting from 0 to 9 is the development of firmware. The
flow chart given in Fig. 6.5 illustrates the firmware requirements for building the decimal counter.

Start

Store the display codes corresponding to 0 to 9 in

code memory location starting from 0050H

1. Initialise Port 2
2. Initialise Stack Pointer
3. De-select ADC chip
4. Load DPTR with the base address of look-up
table stored in code memory

Initialise Index Register to 0

1. Get the ‘Display Code’ from the code memory

address pointed by DPTR and Index Register
YES 2. Load P2 with the data retrieved from code
memory
NO
[Link] for 1 second
2. Increment Index Register

Index Register = 9?

Fig. 6.5 Flowchart for displaying digits using 7-Segment LED Display
174 Introduc on to Embedded Systems

The firmware for implementing the decimal counter is given below.

;####################################################################
;7_Segment_LED_DPTR.src
;Firmware for Implementing Decimal Counter and displaying count in
;7 Segment LED Display
;The display code for displaying digits 0 to 9 are stored in code-
;memory starting from code memory address 0050H.
;The DPTR register holds the base address of the lookup table-
;holding the display codes. Accumulator is used as the index-
;register for retrieving the codes corresponding to 0 to 9
;from code memory. Written & Compiled for A51 Assembler
;Written by Shibu K V. Copyright (C) 2008
;####################################################################
ORG 0023H
ORG 0000H ; Reset vector
JMP 0100H ; Jump to code mem location 0100H to start-
; execution
ORG 0003H ; External Interrupt 0 ISR location
RETI ; Simply return. Do nothing
ORG 000BH ; Timer 0 Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0013H ; External Interrupt 1 ISR location
RETI ; Simply return. Do nothing
ORG 001BH ; Timer 1 Interrupt ISR location
RETI ; Simply return. Do nothing
; Serial Interrupt ISR location
RETI ; Simply return. Do nothing
;####################################################################
;Define the codes for displaying the digits from 0 to 9
;The codes are stored in a lookup table in code memory-
;starting from 0050h
;The DB definition usage is assembler specific
ORG 0050H
DECIMAL_CODES: DB 0C0H, 0F9H, 0A4H, 0B0H, 99H, 12H, 02H, 0F8H, 80H,90H
;####################################################################
; Start of main Program
ORG 0100H
MOV P2, #0FFH ; Turn off all LED segments
MOV SP, #08H ; Set stack at memory location 08H
MOV DPTR,#0050H ; Load the lookup table start address
RESET: CLR A ; Set index to zero.
MOV R7,A ; Backup index register
 Programming the 8051 Microcontroller 175

REPEAT: MOVC A,@A+DPTR ; Get the display code

MOV P2, A ; Load P2 with Display code
CALL DELAY ; Wait for 1 second
INC R7 ; Increment index
MOV A, R7
CJNE A, #10, REPEAT ; Are all 9 digits displayed?
; All 9 digits displayed. Reset counter to 0
JMP RESET
;####################################################################
;Routine for generating 1 second delay
;Delay generation is dependent on clock frequency
;This routine assumes a clock frequency of 12.00MHZ
;LOOP1 generates 248 x 2 Machine cycles (496microseconds) delay
;LOOP2 generates 200 x (496+2+1) Machine cycles (99800microseconds)
;delay. LOOP3 generate 10 x (99800+2+1) Machine cycles
;(998030microseconds) delay
;The routine generates a precise delay of 0.99 seconds
;####################################################################
DELAY: MOV R2, #10
LOOP1: MOV R1, #200
LOOP2: MOV R0, #248
LOOP3: DJNZ R0, LOOP3
DJNZ R1, LOOP2
DJNZ R2, LOOP1
RET
END ;END of Assembly Program

6.2 THE 8051 INSTRUCTION SET

As mentioned earlier, the 8051 Instruction Set is broadly classified into five LO 2 Discuss what
categories namely; Data transfer instructions, Arithmetic instructions, Logical an instruction and
instructions, Boolean instructions and Program control transfer instructions. instruction set is
The following sections describe each of them in detail.

6.2.1 Data Transfer Instructions

Data transfer instructions transfer data between a source and destination. The source can be an internal data
memory, a register, external data memory, code memory or immediate data. Destination may be an internal
data memory, external data memory or a register.
[Link] Internal Data Transfer Opera ons
Internal data transfer instructions perform the movement of data between, register, memory location,
accumulator and stack. MOV instruction is used for data transfer between register, memory location and
accumulator. PUSH and POP instructions transfer data between memory location/register and stack. The
following table summarises the various internal data transfer instructions.
176 Introduc on to Embedded Systems

Instruction Action Comments Machine Exec. Time

Mnemonic Cycles (ms)
MOV <dest>, <dest> = <src> Copies the content of <src> to <dest>. <dest> 2† 2*(fOSC/12)
<src> can be one of the registers B, R0, R1, … R7, any
SFR, a direct internal data memory or an internal
data memory pointed indirectly by the indirect
addressing register R0 or R1 and @. <src> can be
any of the above said locations or an immediate
constant. (General register to register based direct
and indirect data transfer (e.g. MOV R0, R1;
MOV @R0, @R1; MOV @R0, R1; MOV R0, @
R1; etc) is not allowed in the case of registers R0
to R7)
MOV A,< src > A= <src> Copies the content of <src> to Accumulator. 1 fOSC/12
<src> can be registers B, R0, R1, … R7, any SFR,
a direct internal data memory, or an internal data
memory pointed indirectly by indirect addressing
register R0 or R1 and @ or an immediate constant
MOV < dest >, A <dest> =A Copies the content of A to destination. <dest> can 1 fOSC/12
be registers B, R0, R1, …R7, any SFR, or a direct
internal data memory or an internal data memory
pointed indirectly by indirect addressing register
R0 or R1 and @
MOV DPTR=16bit Loads DPTR register with a 16bit data (immedi- 2 2*(fOSC/12)
DPTR,#const data (const) ate addressing)
PUSH <src> SP=SP+1 (@ Increment Stack Pointer register by one and stores 2 2*(fOSC/12)
SP)=<src> the content of <src> at the location pointed by SP
register.
POP <dest> <dest> = @ SP Retrieve the content from the location pointed by 2 2*(fOSC/12)
SP = SP-1 stack pointer to <dest> and decrement SP register
by one
XCH A,<byte> temp = A Exchange data between accumulator and a mem- 1 fOSC/12
A = byte ory location/ register/a memory location pointed
byte = temp indirectly by indirect addressing register.
XCHD A,@Ri Exchanges the low nibble (lower 4 bits) of ‘A’ 1 fOSC/12
(i=0 or 1) with the low nibble of data pointed by indirect
addressing Register R0 or R1
MOV instruction copies the content of source to destination. Only the destination is modified. The source
data remains unchanged.
[Link] Stack Memory Related Data Transfer
‘Stack’ is an internal memory for storing variables temporarily. Stack memory is normally used for storing the
data during subroutine calls. In 8051, by default the stack memory is allocated from the memory location 07H
onwards by loading the stack pointer (SP) register with 07H on power on reset. PUSH instruction stores data
on stack memory. The PUSH instruction first increments the SP by one and copies the data to the memory
†
For all data transfer instruction involving an immediate constant as the source, and scratchpad register R0 to R7 as the destination
(e.g. MOV R0,#00; MOV @R0, #00) the execution cycle is 1 machine cycle.
 Programming the 8051 Microcontroller 177

location pointed by the SP register. POP instruction retrieves the data, which is stored on the stack memory
using PUSH instruction. POP instruction copies the data stored in memory location pointed by SP register to
the variable given along with POP instruction and decrements the SP by one. In 8051 architecture the stack
memory grows upward in memory and follows Last In First Out (LIFO) method. PUSH and POP instructions
use only direct addressing mode and hence the instructions PUSH R0, PUSH R1, PUSH A, etc. are not
valid. They are valid only if the arguments are used with absolute addressing. Hence the valid instructions
corresponding to them are PUSH AR0, PUSH AR1, and PUSH ACC, etc. The operation of PUSH and POP
instructions are illustrated in Fig. 6.6 and Fig. 6.7.

Registers Data memory

Memory
SP 07H address
R0
Load R0
with 55 MOV R0, #55
Get Contents of R0 PUSH AR0 Increment SP register * 07H
Store the Contents of
R0 at Memory Location 55 08H
* Random Data Pointed by SP

Fig. 6.6 Illustration of PUSH instruction

Registers Data memory
Memory
SP 08H
* Random data address
R0

Retrieve the contents * 07H

Load R0 with the of the memory location
POPed Data
POP AR0 55 08H
Pointed by SP register
Decrement SP register

Fig. 6.7 Illustration of POP instruction

The upper 128 bytes of RAM are not implemented physically in the basic 8051 architecture and its
ROMless counterpart 8031. With these devices, if the SP is set to a location in the upper 128 byte area, the
PUSHed bytes will be lost and POPed bytes will be indeterminate.
[Link] Data Exchange Instruc ons
The data exchange instructions exchange data between a memory location and the accumulator register.
Data exchange instructions modify both memory location and accumulator register. 8051 supports two data
exchange instructions, namely, XCH A, <memloc> and XCHD A, @Ri.
The XCH A,<memloc> instruction performs the exchange of the data at memory location ‘memloc’ with
the accumulator. By using MOV instructions the XCH instruction can be implemented as
MOV R0, A
MOV A, memloc ; ‘memloc’ is a memory in the range
; 00H to 7FH
MOV memloc, R0
It requires three instructions and 4 machine cycles and a temporary variable R0 to achieve this. Whereas
the XCH A, <memloc> accomplishes this task with a single instruction and one machine cycle. The XCHD
178 Introduc on to Embedded Systems

A,@Ri (where i = 0 or 1) instruction exchanges the low nibbles between the accumulator and the data memory
pointed by the indirect memory register R0 or R1. Both XCH and XCHD are accumulator specific instructions.
The operation of XCH A, <memloc> and XCHD A,@Ri instructions are illustrated in Figs 6.8 and 6.9.

Registers Memory Data memory

address
A 0FH
07H F0H

Before executing XCH A, 07H instruction

Registers Data memory

Memory
address
A F0H
07H 0FH

After executing XCH A, 07H instruction

Fig. 6.8 Illustration of XCH A, <memloc> Instruction

Registers Data memory

Memory
address
A 0FH
07H F0H
R0 07H
Before executing XCHD A, @R0 instruction

Registers Memory Data memory

address
A 00H
07H FFH
R0 07H

After executing XCHD A, @R0 instruction

Fig. 6.9 Illustration of XCHD A,@Ri Instruction

[Link] External Data Memory Instruc ons

External data memory instructions are used for transferring data between external memory and processor.
The registers involved in external data memory instructions are the Data Pointer (DPTR) or the indirect
addressing register R0/R1 and the accumulator. Only indirect addressing works on external data memory
operations. If the external data memory is 16bit wide, a 16bit register DPTR is used for holding the 16 bit
address to function as the external memory pointer. During 16bit external data memory operations Port 0
emits the content of DPL register (Lower order 8bit address) and Port 2 emits the content of DPH register
(Higher order 8 bit address).
If the external data memory is only 8bit wide, either the DPTR or the indirect address register R0 or R1
can be used for holding the 8bit address to function as the external memory pointer. If DPTR is used as
 Programming the 8051 Microcontroller 179

the memory pointer register, Port 0 emits the content of DPL register (Lower order 8bit address) and Port
2 emits the content of DPH register. If R0 or R1 is used as the memory pointer register, Port 0 emits the
contents of R0 or R1 register (Lower order 8bit address) and Port 2 emits the contents of its SFR register (P2
SFR). The instruction mnemonic used for external data transfer operation is MOVX and depending on the
memory pointer register the operand will be R0, R1 or DPTR. The accumulator is the implicit operand in
MOVX instruction. The direction of external data memory operation (Read or write operation) is determined
by the use of the accumulator register. If the accumulator register is used as the source register, the external
data memory operation is a Write operation and the WR\ signal is also asserted. The external data memory
operation is a Read operation if the accumulator is used as destination register. This also generates the RD\
signal.
External data memory related instructions are listed in the table given below.

Instruction Mnemonic Comments Machine Cycles Exec. Time (ms)

MOVX A,@Ri Read the content of external data memory (8bit 2 2* (fOSC/12)
address) pointed by R0 or R1 to accumulator
MOVX @Ri,A Write accumulator content to external data memo- 2 2* (fOSC/12)
ry (8bit address) pointed by R0 or R1
MOVX A,@DPTR Read the content of external data memory (16 bit 2 2* (fOSC/12)
address) pointed by DPTR register to accumulator
MOVX @DPTR,A Write accumulator content to external data memo- 2 2* (fOSC/12)
ry (16bit address) pointed by DPTR register

The following sample code illustrates how to read and write from and to an 8bit external memory.
; Method-1
; Using Indirect register R0

MOV R0, #055H ; Let 55H be the external data memory

; address
MOVX A,@R0 ; Reads the content of 55H to accumulator
MOV A, #00H ; Clear Accumulator
MOVX @R0, A ; Writes 0 to external memory 55H
; Method-2
; Using Data Pointer (DPTR) Register
MOV DPTR, #55H ; Let 55H be the external data memory
; address
MOVX A,@DPTR ; Reads the content of 55H to accumulator
MOV A, #00H ; Clear Accumulator
MOVX @DPTR, A ; Writes 0 to external memory 55H

The following sample code illustrates how to read and write data from and to a 16bit external memory.
MOV DPTR, #2055H ; Let 2055H be the external data memory
; address
MOVX A,@DPTR ; Reads the content of 2055H to Accumulator
MOV A, #01H ; Load Accumulator with 1
MOVX @DPTR, A ; Writes 1 to external memory 2055H
180 Introduc on to Embedded Systems

Figure 6.10 is given the Instruction fetch and execute sequence for the MOVX instruction.

Machine cycle (M1) Machine cycle (M2)

T State
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
Clock Cycles
P P P P P P P P P P P P P P P P P P P P P P P P
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

ALE

PSEN
RD

P2 PCH out DPH or P2 SFR out PCH out PCH ou

P0 ADDR
INST PCL INST Data PCL INST PCL
(DPL/Ri)
in out in in out in out
out

Fig. 6.10 Timing diagram for MOVX instruction when the program memory is external

MOVX is a two machine cycle instruction. The opcode fetching starts at state-1 (S1) of the first machine
cycle and it is latched to the instruction register. A second program memory fetch occurs at State 4 (S4) of the
same machine cycle. Program memory fetches are skipped during the second machine cycle. This is the only
time program memory fetches are skipped. The instruction-fetch and execute sequence and timing remains
the same regardless the physical location of program memory (it can be either internal or external). If the
program memory is external, the Program Strobe Enable (PSEN) is asserted low on each program memory
fetch and it is activated twice per machine cycle (Fig. 6.10). Since there is no program fetch associated with
the second machine cycle of MOVX instruction, PSEN is not asserted during this (two PSEN signals are
skipped). During the second machine cycle of MOVX instruction, the address and data bus are used for data
memory access.
The lower order address bus is multiplexed with the data bus in 8051 and Port 0 outputs the lower order
address bus during external memory operations and it is available at S5-S6 states of the first machine cycle.
Since it is available only for a short duration of 1 to 1.5 states, it should be latched. The trigger for latch is
provided by the signal Address Latch Enable (ALE). ALE is asserted twice in each machine cycle (during S1
Phase 2 (S1P2) and S4 Phase 2 (S4P2)). Since data is outputted to or read from the external memory at State
1 (S1) to State 3 (S3) of the second machine cycle, during a MOVX instruction, ALE is not emitted at S1P2
of the second machine cycle. Without a MOVX instruction ALE is emitted twice per each machine cycle and
it can be used as a clock signal to any device.
 Programming the 8051 Microcontroller 181

The control signal PSEN is not asserted if the program memory is internal to the chip. However, ALE
signal is asserted even if the program memory is internal.
The external data memory timing for external data memory write is similar to the Read operation except
that the control signal used is WR\ instead of RD\ and the data for writing is available in the place of ‘Data
in’ in the above timing diagram . The timing for all signals remains the same.
[Link] Code Memory Read Instruc ons
Code memory read instruction is used for reading from the code memory. There is only one instruction for
code memory read operation and it is MOVC. Detailed description of MOVC instruction is given in an earlier
section with subtitle “Indexed Addressing”. Please refer back.

6.2.2 Arithmetic Instructions

Arithmetic instructions perform basic arithmetic operations including addition, subtraction, multiplication,
division, increment and decrement. The various arithmetic instructions supported by 8051 are listed below.
Instruction Action Comments Machine Exec. Time
Mnemonic Cycles (ms)
ADD A,<loc> A = A+<loc> Add the content of <loc> with accumulator and stores the 1 fOSC/12
result in accumulator. <loc> can be registers B, R0, R1, …
R7 or any SFR or an immediate constant or an internal data
memory or an internal data memory pointed indirectly by
indirect addressing register R0 or R1 and @
ADDC A= A+<loc> Add the content of <loc> with accumulator and carry 1 fOSC/12
A,<loc> + Carry bit bit and stores the result in accumulator. <loc> can be
(PSW.7) registers B, R0,R1, …R7 or any SFR or an immediate
constant or an internal data memory or an internal
data memory pointed indirectly by indirect addressing
register R0 or R1 and @
SUBB A,<loc> A=A-<loc>- Subtract the content of <loc> from accumulator and bor- 1 fOSC/12
Carry bit row bit and stores the result in accumulator. <loc> can
(PSW.7) be registers B, R0,R1, …R7 or any SFR or an internal
data memory or an immediate constant or an internal
data memory pointed indirectly by indirect addressing
register R0 or R1 and @
INC A A=A+1 Increments accumulator content by one. (Accumulator 1 fOSC/12
Specific Instruction)
INC <loc> <loc > = Increments the content of <loc> by 1. <loc> can be 1 fOSC/12
<loc> + 1 registers B, R0,R1, …R7, or any SFR or an internal data
memory or an internal data memory pointed indirectly
by indirect addressing register R0 or R1 and @
INC DPTR DPTR = Increments the content of 16bit register DPTR by one. 2 2*(fOSC/12)
DPTR + 1 (DPTR Specific Instruction)
DEC A A=A–1 Decrements accumulator content by one. (Accumulator 1 fOSC/12
Specific Instruction)
DEC <loc> <loc > = Decrements the content of <loc> by 1. <loc> can be 1 fOSC/12
<loc> – 1 registers B, R0, R1, …R7 or any SFR or an internal data
memory or an internal data memory pointed indirectly
by indirect addressing register R0 or R1 and @
182 Introduc on to Embedded Systems

MUL AB A=AxB Multiplies accumulator with B register and stores the 4 4*(fOSC/12)
result in accumulator & B (Lower order byte of result
in accumulator and higher order byte in B register)
DIV AB A = integer Divides accumulator with B register and stores the result 4 4*(fOSC/12)
part of [A/B] in accumulator and remainder in B register
B=Remainder
of [A/B]
DA A Decimal adjust Accumulator. Used in BCD arithme- 1 fOSC/12
tic

[Link] Addi on and Subtrac on

The 8051 supports the addition of 8bit binary numbers and stores the sum in the accumulator register. The
instructions ADD A,<loc> and ADDC A,<loc> are used for performing addition operations. Both of these
instructions are accumulator specific, meaning the accumulator is an implicit operand in these instructions.
The ADD A,<loc> is used for performing a normal addition and the carry flag gets modified accordingly
on executing this instruction. If the addition results in an output greater than FFH, the carry flag is set and
the accumulator content will be the final result–FFH + carry. The carry flag is reset when the result of an
addition is less than or equal to FFH. The ADDC A,<loc> instruction operates in the same way as that of
ADD A,<loc> instruction except that it adds the carry flag with A and <loc>. The changes to the carry flag
on executing this instruction remains the same as that of executing the ADD A, <loc> instruction. Executing
these instructions modify the content of accumulator only and <loc> remains unchanged.
The instruction SUBB A, <loc> performs the subtraction operation. The carry flag acts as the borrow
indicator in the subtraction operation. The SUBB A, <loc> instruction subtracts the borrow flag and the
contents pointed by <loc> from accumulator and modifies the accumulator with the result. The content of
<loc> remains unchanged. For performing a normal subtraction operation, first clear the carry flag and then
call the SUBB A, <loc> instruction. The carry (borrow) flag gets modified accordingly on executing this
instruction. If the subtraction results in a –ve number (‘A’ less than (<loc> + Carry)), the borrow (carry) flag
is set and the accumulator content will be the 2’s complement† representation of the result (e.g. Accumulator
*

contains 0FEH and borrow (carry) flag is 0, executing the instruction SUBB A, #0FFH results in –1 which is
represented in the accumulator by the 2’s complement form of 1. Hence the content of accumulator becomes
FFH (2’s complement form of 1) and the borrow (carry) flag is also set). The carry flag is reset when the result
of a subtraction is +ve (‘A’ is greater than (<loc> + Carry)). The SUBB A, <loc> instruction is accumulator
specific, meaning accumulator is an implicit operand for this instruction.

Example 1
The accumulator register contains 80H and B register contains 8FH. Add accumulator content with B register.
Explain the output of the summation and the status of the carry flag after the addition operation.
Adding 80H with 8FH results in 10FH. Since 10FH requires more than 8 bits to represent, the accumulator
holds only the least significant 8 bits of the result (Here 0FH). The carry bit CY present in the Program Status
Word (PSW) register is set to indicate that the output of the addition operation resulted in a number greater
than FFH. Figure 6.11 illustrates the addition operation and the involvement of Carry bit (CY).

†* 2’s complement of a number = 1’s complement of the number +1

 Programming the 8051 Microcontroller 183

D7 D6 D5 D4 D3 D2 D1 D0

A CY 1 0 0 0 0 0 0 0 80H

ADD A,B +

B 1 1 0 0 0 1 1 1 1 8FH

CY 0 0 0 0 1 1 1 1 0FH
A
=1

Fig. 6.11 Illustration of ADD instruction operation

Example 2
Register R0 contains 0BH. Add the contents of register R0 with the sum obtained in the previous example
using ADDC instruction. Explain the output of the summation and the status of the carry flag after the
addition operation.
The instruction ADDC A, R0 adds accumulator content with contents of register R0 and the carry flag
(CY). Before executing this instruction, the accumulator contains the sum of previous addition operation,
which is 0FH and the carry flag (CY) is in the set state. Register R0 contains 0BH. Executing the instruction
ADDC A, R0 adds 0FH with 0BH and 1. The resulting output is 1BH which is less than FFH. This resets the
carry flag. Accumulator register holds the sum. It should be noted that each addition operation sets or resets
the carry flag based on the result of addition, regardless of the previous condition of the carry flag. Figure
6.12 explains the ADDC operation.

D7 D6 D5 D4 D3 D2 D1 D0

A 0 0 0 0 1 1 1 1 0FH

CY
ADDC A,R0 + =1

R0 0 0 0 0 1 0 1 1 0BH
1 1 1 1

A CY 0 0 0 1 1 0 1 1 1BH
=0

Fig. 6.12 Illustration of ADDC instruction operation

Example 3
The accumulator register contains 8FH and B register contains 0FH. The borrow Flag (CY) is in the set state.
Subtract the contents of accumulator with borrow and B register. Explain what is the output of the subtraction
and the status of the borrow flag after the subtraction operation.
8051 supports only SUBB instruction for subtraction. The SUBB instruction subtracts the borrow flag
(CY) and the number to be subtracted, from accumulator. The subtraction operation is implemented by
184 Introduc on to Embedded Systems

adding accumulator with the 2’s complement of borrow flag and the 2’s complement of the number to be
subtracted.
The 2’s complement of borrow flag (CY=1) results in FFH. The 2’s complement of B register content
(0FH) yields F1H. The accumulator content is added with the 2’s complement of borrow flag (8FH + FFH)
and the result (8E) is added with the 2’s complement of B register (8EH + F1H). This results in 7FH with the
borrow flag (CY) in the set state. The final step in the subtraction operation is complementing the borrow flag
(Carry Flag). A value of 1 for borrow flag after complementing indicates that the result is negative whereas
a value of 0 indicates that the result of subtraction is positive. If the result is negative, accumulator contains
the 2’s complement of the negative number. Figure 6.13 illustrates subtract with borrow operation and the
involvement of borrow bit (CY).

CY 0 0 0 0 0 0 0 1 01H
=1

1's Complement of 1 1 1 1 1 1 1 0 FEH

Carry
2's Complement of
Carry = 1's 1 1 1 1 1 1 1 1 FFH
Complement of
Carry + 1

B 0 0 0 0 1 1 1 1 0FH

1's Complement of B 1 1 1 1 0 0 0 0 F0H

2's Complement of B
= 1's Complement of 1 1 1 1 0 0 0 1 F1H
B+1
A 1 0 0 0 1 1 1 1 8FH

+
SUBB B
CY 1 1 1 1 1 1 1 1 FFH
1 1 1 1 1 1 1 1

A CY 1 0 0 0 1 1 1 0 8EH
=1
+
1 1 1 1 0 0 0 1 F1H
1

A CY 0 1 1 1 1 1 1 1 7FH
=1
Complement
CY 0 1 1 1 1 1 1 1 A=
=0 7FH

Fig. 6.13 Illustration of SUBB instruction operation

 Programming the 8051 Microcontroller 185

[Link] Mul plica on and Division

The instruction MUL AB multiplies two 8bit unsigned numbers and stores the 16bit result in the register pair
A, B. The accumulator stores the lower order 8 bits of the result and B register stores the higher order 8 bits
of the result. The overflow flag (OV) is set when the product is greater than 0FFH and cleared otherwise. The
carry flag becomes cleared state irrespective of the product.
The DIV AB instruction divides the content of accumulator register with the content of B register and stores
the integer part of the quotient (A/B) in accumulator and the modulus (A%B) in B register (e.g. If A contains
03H and B contains 02H, executing the instruction DIV AB loads accumulator with 01H (3/2) and B register
with 01H (3%2). 8051 does not have a divide by zero interrupt mechanism to indicate a divide by zero error.
However 8051 indicates the divide by zero condition by setting the overflow flag (OV) in the Program Status
Word (PSW) register. The values returned in A and B are undefined for a divide-by-zero operation.
The overflow flag (OV) and carry flag (CY) are cleared for normal division operation.
MUL and DIV instructions are accumulator and register B specific instructions. They work only with these
two registers. If register B is not used for multiplication and division, it can be used for temporary storage.

Example 1
Convert the binary number FFH present in the accumulator to unpacked BCD and store the resultant 3 digit
BCD number in consecutive memory locations starting from 20H
BCD numbers are numbers with base 10. BCD numbers use digits 0 to 9 for representing a number. They
are normally used for representing a meaningful decimal number. Each digit in the BCD number represents
the consecutive powers of 10. For example, the BCD number 255 is interpreted as 2 × 102 + 5 × 101 + 5
× 100. Binary numbers follow the base 2 numbering system. Regardless of the numbering system, digital
systems internally represent the numbers in binary format. For an 8bit word length controller/processor,
the maximum number value that can be represented in binary is 11111111, which is equivalent to FFH in
hexadecimal and 255 in decimal. For retrieving the digits of a decimal number, the number is divided with 10
repeatedly until the quotient is zero. The remainder from each division gives the successive LSB digits of the
corresponding BCD number. For example, for 255, the first division gives the quotient as 25 and remainder
as 5, hence the LSB digit for the BCD number is 5. The next division of the quotient by 10 gives 2 as quotient
and 5 as remainder. The remainder 5 forms the next LSB digit for the BCD. Performing one more division
with 10 on the quotient (2) gives 0 as quotient and 2 as remainder. This remainder acts as the MSB digit
for the corresponding BCD number. In fact for an 8bit binary number, only two divisions are required. The
remainders from the two consecutive divisions form the consecutive LSB digits for the BCD number and the
quotient after the second division becomes the MSB digit for the corresponding BCD number. The following
assembly code implements this principle. The DIVAB instruction performs the successive divisions with 10.

;####################################################################
;binary_unpacked_bcd.src
;Firmware for converting binary number to unpacked BCD
;The binary number to be converted is present in the accumulator
;The BCD corresponding to the converted binary is stored in-
;memory location starting from 20H with the least significant digit
;of BCD stored in memory location 20H
;Written & Compiled for A51 Assembler
;Written by Shibu K V. Copyright (C) 2008
;####################################################################
ORG 0000H ; Reset vector
186 Introduc on to Embedded Systems

JMP 0100H ; Jump to start of main program

ORG 0003H ; External Interrupt 0 ISR location
RETI ; Simply return. Do nothing
ORG 000BH ; Timer 0 Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0013H ; External Interrupt 1 ISR location
RETI ; Simply return. Do nothing
ORG 001BH ; Timer 1 Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0023H ; Serial Interrupt ISR location
RETI ; Simply return. Do nothing
;####################################################################
; Start of main Program
ORG 0100H
MOV A, #0FFH ; Load Accumulator with the binary number
MOV R0, #20H ; Load the mem location for storing BCD Digit
MOV R1, #2 ; Load division counter
CONTINUE:MOV B, #10
DIV AB
MOV @R0,B ; B holds the remainder, which is the BCD
INC R0 ; Increment mem loc to store next BCD Digit
DJNZ R1,CONTINUE
MOV @R0,A ; The last BCD digit is the quotient
JMP $ ; Loop forever
END ;END of Assembly Program

Example 2
Convert the packed BCD number ‘98’ stored in the accumulator to corresponding binary number and store
the result in accumulator.
The packed BCD number is stored using a single byte. The higher 4 bits of the byte store the most significant
digit of the packed BCD number and the lower 4 bits store the least significant digit of the BCD number.
Hence the accumulator representation of packed BCD is 10001000b (98H). The binary value corresponding
to this packed BCD is the binary representation of 9 × 101 + 8 × 100 = 9 × 10 + 8 × 1 = 90 + 8.

;####################################################################
;packedbcd_to_binary.src
;Firmware for converting packed BCD to binary
;The BCD number to be converted is present in accumulator
;The resultant binary number is held in Accumulator register
;Written & assembled for A51 Assembler
;Written by Shibu K V. Copyright (C) 2008
;####################################################################
ORG 0000H ; Reset vector
JMP 0100H ; Jump to start of main program
ORG 0003H ; External Interrupt 0 ISR location
RETI ; Simply return. Do nothing
 Programming the 8051 Microcontroller 187

ORG 000BH ; Timer 0 Interrupt ISR location

RETI ; Simply return. Do nothing
ORG 0013H ; External Interrupt 1 ISR location
RETI ; Simply return. Do nothing
ORG 001BH ; Timer 1 Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0023H ; Serial Interrupt ISR location
RETI ; Simply return. Do nothing
;####################################################################
; Start of main Program
ORG 0100H
MOV A, #98H ; Packed BCD representing 98
MOV R0, A ; Backup BCD number
SWAP A ; Extract the MSB of packed BCD
ANL A, #0FH ; Extract the MSB of packed BCD
MOV B, #10 ;
MUL AB ; Get the positional weight for MSB digit
MOV R1, A ; Store the temporary result
MOV A, R0 ; Retrieve the original BCD number
ANL A, #0FH ; Extract the LSB of packed BCD
ADD A,R1 ; Final result
JMP $ ; Loop forever
END ;END of Assembly Program

[Link] Increment and Decrement

The increment instruction (INC) increments the content of the location pointed by the operand. The INC A
instruction is an accumulator specific instruction which increments the content of accumulator. Executing the
instruction INC A will not modify the carry flag. The INC <loc> instruction increments the content pointed
by <loc>. If the content pointed by the operand of INC instruction is FFH, on executing the INC instruction,
the content simply rolls over to 00H. None of the status bits are modified to indicate this rollover. INC DPTR
instruction is DPTR register specific instruction and it increments the content of 16bit DPTR register by one.
The following piece of assembly code illustrates the usage of INC instruction.

MOV 00H,#80H ; Load Data memory location 00H (R0) with 80H
MOV A,#0FFH ; Load Accumulator with FFH
MOV DPTR,#00FFH ; Load DPTR with 00FFH
INC 00H ; Increment the contents of Data memory-
; location 00H. It becomes 81H
INC A ; Increment the content of Accumulator. It-
; becomes 00H
INC DPTR ; Increment the content of DPTR Register. It-
; becomes 0100H

The decrement instruction (DEC) decrements the content of the location pointed by the operand. The DEC
A instruction is an accumulator specific instruction which decrements the content of accumulator. Executing
the instruction DEC A will not modify the carry flag. The DEC <loc> instruction decrements the content
188 Introduc on to Embedded Systems

pointed by <loc>. If the content pointed by the operand of DEC instruction is 00H, executing the DEC
instruction simply rolls over it to FFH. None of the status bits are modified to indicate this. The following
code snippet illustrates the usage of DEC instruction.

MOV 00H,#80H ; Load Data memory location 00H (R0) with 80H
MOV A,#0FFH ; Load Accumulator with FFH
DEC 00H ; Decrement the contents of Data memory-
; location 00H. It becomes 7FH
DEC A ; Decrement the content of Accumulator. It-
; becomes FEH

There is no specific instruction to decrement the DPTR register content by one in 8051 instruction set.
However decrementing the DPTR can be achieved by using other instructions in the optimal way.
[Link] Decimal Adjust
The DA A instruction adjusts the accumulator content to give a meaningful BCD result in BCD arithmetic.
Binary Coded Decimal (BCD) is a number representation in numeric systems. In the BCD number system,
numerals from 0 to 9 are used for representing a number. Based on the number of BCD digits represented in a
single byte, the BCD numbers are known as packed and unpacked BCDs. In the unpacked BCD representation,
a single BCD digit (0 to 9) is represented by a single byte whereas in the packed BCD representation two
BCD digits (00 to 99) are represented using a single byte. ADD and ADDC instructions used for BCD
addition should follow a DA A instruction to bring the Accumulator content to a meaningful BCD result. It
should be noted that the DA A instruction will not convert a binary number to a BCD. The DA A instruction
always follow the ADD instruction.

Example 1
Write an assembly program to add two packed BCD numbers ‘28’ and ‘12’ stored in consecutive memory
locations starting from data memory address 50H. The result of the addition should be adjusted for BCD.
The Assembly code snippet shown below illustrates the implementation.

;####################################################################
;BCD_addition.src
;Firmware for adding two packed BCD numbers
;The BCD numbers to be added are present in the memlocation 50H & 51H
;The resultant BCD number is held in Accumulator register
;After addition the result is adjusted for BCD
;Written & assembled for A51 Assembler
;Written by Shibu K V. Copyright (C) 2008
;####################################################################
ORG 0000H ; Reset vector
JMP 0100H ; Jump start of main program
ORG 0003H ; External Interrupt 0 ISR location
RETI ; Simply return. Do nothing
ORG 000BH ; Timer 0 Interrupt ISR location
 Programming the 8051 Microcontroller 189

RETI ; Simply return. Do nothing

ORG 0013H ; External Interrupt 1 ISR location
RETI ; Simply return. Do nothing
ORG 001BH ; Timer 1 Interrupt ISR location
RETI ; Simply return. Do nothing
ORG 0023H ; Serial Interrupt ISR location
RETI ; Simply return. Do nothing
;####################################################################
; Start of main Program
ORG 0100H
MOV 050H, #28H ; Packed BCD representing 28
MOV 051H, #12H ; Packed BCD representing 12
MOV A, 050H ; Move the first BCD number to Accumulator
ADD A, 051H ; Add with second BCD number
DA A ; Decimal adjust the result
JMP $ ; Loop forever
END ;END of Assembly Program

If the accumulator is not adjusted for decimal, after the addition, the accumulator content will be 3AH.
Adjusting the accumulator for decimal, after the addition operation, produces a meaningful result, 40H
(Which is the sum of the BCDs 28 and 12).

6.2.3 Logical Instructions

Logical instructions perform logical operations such as ‘ORing’, ‘ANDing’, ‘XORing’, complementing,
clearing, bit rotation and swapping nibbles of a byte, etc. The list of logical instructions supported by 8051
is tabulated below.

Instruction Action Comments Machine Exec. Time

Mnemonic Cycle (ms)
ORL A,<loc> A = A|<loc> Perform bitwise logical OR the content of 1 fOSC/12
Accumulator with the content of <loc> and
stores the result in Accumulator. <loc> can be
registers B, R0, R1, …R7, or any SFR, an im-
mediate constant, an internal data memory or
an internal data memory pointed indirectly by
indirect addressing register R0 or R1 and @
ORL <loc>,A <loc> = A|<loc> Bitwise logical OR the content of the accumu- 1 fOSC/12
lator with the content of <loc> and stores the
result in memory location <loc>. <loc> can be
any SFR or an internal data memory
ORL <loc>,#const <loc> = Bitwise logical OR the content of <loc> with 2 2*(fOSC/12)
<loc>|const an immediate constant and stores the result
in memory location <loc>. <loc> can be any
SFR or an internal data memory
190 Introduc on to Embedded Systems

ANL A,<loc> A=A&<loc> Bitwise logical AND the content of the accu- 1 fOSC/12
mulator with the content of <loc> and stores
the result in Accumulator. <loc> can be B,
R0, R1, …R7, or any SFR, an internal data
memory or an immediate constant or an inter-
nal data memory pointed indirectly by indirect
addressing register R0 or R1 and @
ANL <loc>,A <loc> = A&<loc> Bitwise logical AND the content of the accu- 1 fOSC/12
mulator with the content of <loc> and stores
the result in memory location <loc>. <loc> can
be any SFR or an internal data memory
ANL <loc>,#const <loc> = Bitwise logical AND the content of <loc> with 2 2*(fOSC/12)
<loc>&const an immediate constant and stores the result in
memory location <loc>. <loc> can be any SFR
or an internal data memory
XRL A,<loc> A = A^<loc> Bitwise logical XOR the content of the accu- 1 fOSC/12
mulator with the content of <loc> and stores
the result in Accumulator. <loc> can be B,
R0, R1, …R7, or any SFR, an internal data
memory or an immediate constant or an inter-
nal data memory pointed indirectly by indirect
addressing register R0 or R1 and @
XRL <loc>,A <loc> = A^<loc> Logical XOR the content of the accumulator 1 fOSC/12
with the content of <loc> and stores the result
in memory location <loc>. <loc> can be any
SFR or an internal data memory
XRL <loc>,#const <loc> = <loc> ^ Logical XOR the content of <loc> with an 2 2*(fOSC/12)
const immediate constant and stores the result in
memory location <loc>. <loc> can be any SFR
or an internal data memory
CLR A A = 00H Clear the content of accumulator (Loads 0 to 1 fOSC/12
Accumulator)
CPL A A = ~A Complement the content of the accumulator. 1 fOSC/12
1s are replaced by 0s and 0s by 1s.
RL A A = A<1 Rotate the Accumulator content 1 bit to the 1 fOSC/12
left. The MSB of the accumulator is shifted out
to the LSB position of the accumulator
RLC A A = A<1 Rotate the accumulator content 1 bit to the 1 fOSC/12
left through carry bit. The MSB of the accu-
mulator is shifted out to carry bit and content
of carry bit enters at the LSB position of the
Accumulator
RR A A = A>1 Rotate the accumulator content 1 bit to the 1 fOSC/12
right. The LSB of the Accumulator is shifted
out to the MSB position of the Accumulator
 Programming the 8051 Microcontroller 191

RRC A A = A>1 Rotate the accumulator content 1 bit to the 1 fOSC/12

right through carry bit. The LSB of the accu-
mulator is shifted out to carry bit and content
of carry bit enters at the MSB position of the
accumulator
SWAP A Before swap Exchanges between the low nibble and high 1 fOSC/12
A = Nib2 Nib1 nibble of the accumulator.
After swap
A = Nib1 Nib2

The ANL instruction performs bitwise ANDing operation. The operation of ANL instruction is illustrated
below. Suppose the Accumulator contains 80H and if it is ANDed with an immediate constant 80H, the
following actions shown in Fig. 6.14 take place.

Accumulator 1 0 0 0 0 0 0 0 80H

AND operation & & & & & & & &

Constant 1 0 0 0 0 0 0 0 80H

Result in 1 0 0 0 0 0 0 0 80H
accumulator
Fig. 6.14 Illustration of ANL instruction operation

Similarly the ORL instruction performs the bitwise ORing operation. For example, let us assume that the
accumulator contains 01H and it is ORed with an immediate data 80H. The result will be 81H and it is stored
in the accumulator. It is explained in Fig. 6.15.

Accumulator 0 0 0 0 0 0 0 1 01H

‘OR’ operation | | | | | | | |

Constant 1 0 0 0 0 0 0 0 80H

Result in 1 0 0 0 0 0 0 1 81H
accumulator
Fig. 6.15 Illustration of ORL instruction operation

The XRL instruction performs the bitwise XORing operation. The principle of XOR is that if both the
XORing bits are same (both are either 0 or 1) the output bit is 0 and if the XORing bits are complement
to each other the output bit is 1. For example, if the accumulator content is 81H and an XOR operation of
the accumulator with an immediate constant 80H yields 01H as output. The XRL instruction operation is
explained in Fig. 6.16.
192 Introduc on to Embedded Systems

Accumulator 1 0 0 0 0 0 0 1 81H

‘XOR’ operation ^ ^ ^ ^ ^ ^ ^ ^
Constant 1 0 0 0 0 0 0 0 80H

Result in 0 0 0 0 0 0 0 1 01H
accumulator
Fig. 6.16 Illustration of XRL instruction operation

The CLR A and CPL A instructions are accumulator specific instructions. The CLR A instruction clears
the content of accumulator (loads accumulator with 00H), whereas the CPL A instruction complements
the accumulator content (negates the accumulator content). Both CLR A and CPL A instructions are single
machine cycle instructions.
Assuming accumulator contains F0H, Fig. 6.17 illustrates the operation of CLR A and CPL A
instructions.

Accumulator 1 1 1 1 0 0 0 0 F0H

Accumulator after CLR A 0 0 0 0 0 0 0 0 00H

instruction execution
(a) CLR A instruction operation

Accumulator 1 1 1 1 0 0 0 0 F0H

‘CPL’ operation

0 0 0 0 1 1 1 1 0FH

(b) CPL A instruction operation

Fig. 6.17 Illustration of (a) CLR A instruction operation (b) CPL A instruction operation

Rotate instructions rotates the bits of the Accumulator. All Rotate instructions are Accumulator specific
instructions and Accumulator is the implicit register for rotate operations. Accumulator bits can be either
rotated to left or right.
The RL A instruction rotates the accumulator bits to the left by one position and the MSB of the accumulator
comes in place of the LSB. For example, the accumulator contains 80H, after executing an RL A instruction,
the contents of the accumulator will become 01H. It is illustrated in Fig. 6.18.
The RLC A instruction is similar in operation to RL A instruction except that in RLC A instruction the MSB
of the Accumulator is shifted to the Carry bit (CY) and the content of carry flag at the moment of execution of
the RLC A instruction is shifted to the LSB of Accumulator. The operation of RLC A instruction is illustrated
in Fig. 6.19. Assuming the Accumulator contains 80H and the carry bit is in the cleared state (0). Executing
the RLC A instruction sets the carry flag and modifies the Accumulator content to 00H.
One more execution of the RLC A instruction will change the accumulator content to 01H and resets the
carry flag.
 Programming the 8051 Microcontroller 193

Accumulator 1 0 0 0 0 0 0 0 80H

Result in Accumulator
after RLA instruction 0 0 0 0 0 0 0 1 01H
execution
Fig. 6.18 Illustration of RL A instruction operation

CY
0

Accumulator 1 0 0 0 0 0 0 0 80H

CY
1
Result in Accumulator
after RLC A instruction 0 0 0 0 0 0 0 0 00H
execution
Fig. 6.19 Illustration of RLC A instruction operation

The RR A instruction rotates the accumulator bits to the right by one position and the LSB of the
accumulator comes in place of the MSB. For example if the accumulator contains 01H, after executing the
RR A instruction, the contents of the accumulator will become 80H (Fig. 6.20).

Accumulator 0 0 0 0 0 0 0 1 01H

Result in Accumulator
after RR A instruction 1 0 0 0 0 0 0 0 80H
execution
Fig. 6.20 Illustration of RR A instruction operation

The RRC A instruction is similar to RLC A instruction except that in RRC A instruction the LSB of the
accumulator is shifted to the carry bit (CY) and the content of carry flag at the moment of execution of
RRC A instruction is shifted to the MSB of the accumulator. Assuming that the accumulator contains 01H
and the carry bit is in the set state (1). Executing the RRC A instruction sets the carry flag and modifies the
accumulator content to 80H (Fig. 6.21).
The SWAP A instruction interchanges the lower and higher order nibbles of the Accumulator. Assuming
the accumulator contains F5H, executing SWAP A instruction modifies the accumulator content to 5FH.
The SWAP A instruction shown in Fig. 6.22 is very helpful in BCD to binary conversion.
194 Introduc on to Embedded Systems

CY
1

Accumulator 0 0 0 0 0 0 0 1 01H

Carry Flag after RRC A CY

instruction execution 1
Result in Accumulator
after RRC A 1 0 0 0 0 0 0 0 80H
instruction execution
Fig. 6.21 Illustration of RRC A instruction operation

Accumulator 1 1 1 1 0 1 0 1 F5H

Result in Accumulator
after SWAP A instruction 0 1 0 1 1 1 1 1 5FH
execution
Higher Nibble Lower Nibble
Fig. 6.22 Illustration of SWAP A instruction operation

6.2.4 Boolean Instructions

The 8051 CPU provides extensive support for bit manipulation instructions. Internal RAM of 8051 contains
128 bit-addressable memory and all SFRs whose address ends with 0H and 8H are bit addressable. Boolean
instructions are used for performing various operations like bit transfer, bit manipulation, logical operations
on bits, program control transfer based on bit state, etc.
The carry bit ‘C’, present in the Special Function Register PSW, takes the role of accumulator in all bit
related operations. The various Boolean instructions supported by the 8051 CPU are listed below. It is to be
noted that all bit access is through direct addressing only.

Instruction Action Comments Machine Exec. Time

Mnemonic Cycles (ms)
Bit manipulation & transfer Instructions
MOV C, Bit C = Bit Moves Bit to carry flag 1 fOSC/12
MOV Bit, C Bit = C Moves carry flag to Bit 2 2*(fOSC/12)
CLR C C=0 Clears carry flag 1 fOSC/12
CLR Bit Bit = 0 Clears specified Bit 1 fOSC/12
 Programming the 8051 Microcontroller 195

SETB C C=1 Sets carry flag 1 fOSC/12

SETB Bit Bit = 1 Sets specified Bit 1 fOSC/12
Logical Operations on Bits
Logical AND Carry flag with Bit and store the
ANL C, Bit C = C & Bit 2 2*(fOSC/12)
result in Carry flag
C=C& Logical AND the complemented value of Bit with
ANL C, /Bit 2 2*(fOSC/12)
(.NOT. Bit†) Carry flag and store the result in Carry flag
Logical OR Carry flag with Bit and store the result
ORL C, Bit C = C | Bit 2 2*(fOSC/12)
in Carry flag
C= C | (.NOT. Logical OR the complemented value of Bit with
ORL C, /Bit 2 2*(fOSC/12)
Bit††) Carry flag. Result in Carry flag
CPL C C=.NOT.C Complements the Carry flag 1 fOSC/12
CPL Bit C=.NOT. Bit Complements Bit 1 fOSC/12
Program Control transfer based on Bit status
If (C)
JC rel Jump to the relative address ‘rel’ if Carry flag is 1 2 2*(fOSC/12)
Jump to rel
If (!C)
JNC rel Jump to the relative address ‘rel’ if Carry flag is 0 2 2*(fOSC/12)
Jump to rel
If (Bit) Jump to the relative address ‘rel’ if the specified Bit
JB Bit, rel 2 2*(fOSC/12)
Jump to rel is 1
If (!Bit) Jump to the relative address ‘rel’ if the specified Bit
JNB Bit, rel 2 2*(fOSC/12)
Jump to rel is 0
If (Bit)
{
If the specified Bit is 1, clear the bit and jump to the
JBC Bit, rel Clear Bit; 2 2*(fOSC/12)
relative address ‘rel’
Jump to rel;
}

The Boolean instructions are very useful in bit manipulation operation for bit-addressable SFRs.
Manipulation of port status registers (P0 to P3) is a typical example. The usage of Boolean instructions is
illustrated below.
MOV C, P2.0 ; Load carry flag with Port pin 2.0’s status.
MOV P2.0, C ; Load Port 2.0 latch with content of carry flag
SETB C ; Set the carry flag
CLR C ; Clear carry flag
ANL C, P2.0 ; Logical AND P2.0 Latch bit with Carry flag and
; load Carry bit with the result

†
The actual state of the bit remains unchanged. If bit 0H is in the cleared state, executing the instruction ANL C, /0H will not change
the state of bit 0H to set.
††
The actual state of the Bit remains unchanged. If bit 0H is in the cleared state, executing the instruction ORL C, /0H will not change
the state of bit 0H to set.
196 Introduc on to Embedded Systems

The JC rel and JNC rel instructions has got special significance in comparison operation. The 8051
supports only one compare instruction, CJNE, which checks only for the equality of the register/data pair
compared. There is no built in instruction for checking above or below condition (Compare and jump if above
and Compare and jump if below). These conditions can be checked by using the JC and JNC instructions in
combination with the CJNE instruction. The CJNE instruction followed by the JNC instruction implements
the Compare and jump if above condition and the CJNE instruction followed by the JC instruction implements
the Compare and jump if below condition. The following code snippet illustrates the same. Assume that the
accumulator content is 50H and it is compared against 51H.

//Implementation of Compare and Jump if above

CJNE A, #51H,above?
; Check whether accumulator content is greater than 51H
; The Carry flag is cleared if Accumulator >= const
above?: JNC acc_high
; Accumulator < 51H. Do the rest of processing here
acc_high: ; Accumulator >= 51H. Do the rest of processing here
//Implementation of Compare and Jump if below
CJNE A, #51H, below?
; Check whether accumulator content is less than 51H
; The Carry flag is set if Accumulator < const
below?: JC acc_low
Accumulator >= 51H. Do the rest of processing here
acc_low: ; Accumulator < 51H. Do the rest of processing here

6.2.5 Program Control Transfer Instructions

The Program control transfer instructions change the program execution flow. The 8051 instruction set supports
two types of program control transfer instructions namely; Unconditional program control instructions and
Conditional program control instructions. They are explained below.
[Link] Uncondi onal Program Control Transfer Instruc ons
The unconditional program control instructions transfer the program flow to any desired location in the code
memory. The unconditional program control instructions supported by 8051 are listed below.

Instruction Mnemonic Action Comments Machine Cycles Exec. Time (ms)

JMP address Jump to the specified address 2 2*(fOSC/12)
JMP @A+DPTR Jump to the address (A+DPTR) 2 2*(fOSC/12)
Call subroutine located at the code
CALL address 2 2*(fOSC/12)
memory ‘address’
RET Return from a subroutine 2 2*(fOSC/12)
RETI Return from an Interrupt routine 2 2*(fOSC/12)
NOP No operation (Do nothing) 1 fOSC/12
 Programming the 8051 Microcontroller 197

Jump Instruc ons The instruction JMP represents three type of jumps. They are SJMP, LJMP and AJMP
and they are used in appropriate contexts. If the programmer is not interested in analysing the contexts, he/
she can simply use the JMP instruction.
SJMP instruction stands for Short Jump. The destination address is given as an offset to the current address
held by the Program Counter (PC). The SJMP instruction is a two byte instruction consisting of the opcode
for SJMP and the relative offset address which is one byte. The jump distance for the SJMP instruction is
limited to the range of –128 to +127 bytes relative to the instruction following the jump.
LJMP instruction stands for Long Jump. The destination address for LJMP is given as the real physical
address of the code memory location to which the jump is intended. The LJMP instruction is a three byte
instruction consisting of the opcode for LJMP and the two byte physical address of the location to which the
program flow is to be diverted. The jump location can be anywhere within the 64K program memory.
The third type of jump instruction AJMP stands for Absolute Jump. The AJMP instruction encodes the
destination address as 11-bit constant. The instruction is two byte long consisting of the opcode, which itself
contains higher 3 bits of the 11-bit constant. Rest 8 bits of the destination address is held by the second byte
of the instruction. When an AJMP instruction is executed, these 11 bits are substituted for the lower 11 bits in
the Program Counter (PC). The higher 5 bits of the Program Counter remains the same. Hence the destination
will be within the same 2K block of the current instruction. In general AJMP is used for jumping within a
memory block.
The programmer need not bother about handling these three jumps, what he/she can do is simply provide
the destination address as label or a 16 bit constant. The assembler converts the JMP instruction to any of the
three jump instruction depending on the context.
Case jumps for diverting program execution flow dynamically can be implemented using JMP
@A+DPTR instruction. The destination address is computed during run time as the sum of the DPTR register
content and accumulator. Normally DPTR is loaded with the address of a jump table which holds jump
instructions to the memory location corresponding to a ‘case’. For an n-way branching requirement, the
accumulator is loaded with 0 through n–1. The following code snippet illustrates the implementation of a
switch case statement using JMP @ A+DPTR.
//switch case in ‘Embedded C’
switch (var)
{
Case0:
// Action…
Case1:
// Action…
Case2:
// Action…
}
Corresponding switch case implementation in 8051 Assembly using JMP @ A+DPTR
var EQU 50H ;Assume memory location 50H is holding variable ‘var’
MOV DPTR, #CASE_TABLE ;Load the base address of jump table
MOV A,var; Load Accumulator with the case index
RL A ; Convert the case table index to corresponding offset
JMP @A+DPTR ; Jump to the case condition
;###################################################################
198 Introduc on to Embedded Systems

CASE_TABLE:
AJMP CASE0 ; Jump to location implementing code for CASE0
AJMP CASE1 ; Jump to location implementing code for CASE1
AJMP CASE2 ; Jump to location implementing code for CASE2
CASE0: ; Action corresponding to case0
CASE1: ; Action corresponding to case1
CASE2: ; Action corresponding to case2

Locations CASE0, CASE1 and CASE2 should contain the action item to be implemented for each case
statement.
The subroutine calling instruction CALL is of two types; namely LCALL and ACALL. LCALL is a three
byte instruction of which the first byte represents the opcode and the second and third bytes hold the physical
address of the program memory where the subroutine, which is to be executed, is located. For LCALL the
subroutine can be anywhere within the 64K byte of program memory. ACALL is similar to AJMP. ACALL is
a two byte instruction of which the first byte holds the opcode as well as the higher 3 bits of the 11-bit address
of the location where the subroutine is located. The second byte holds the remaining 8 bits of the address
location. ACALL is used for calling a subroutine which is within the 2K block of the instruction, calling the
subroutine.
RET instruction performs return from a subroutine call. Executing the RET instruction brings the program
flow back to the instruction following the CALL to the subroutine. RETI performs the return from an interrupt
routine. RETI instruction is similar to the RET instruction in all respect except that the RETI informs the
interrupt system that the interrupt in progress is serviced.
The NOP instruction does not perform anything specific. It simply forces the CPU to wait for one machine
cycle. It is very useful for generating short waits. It simply eats up the processor time. For example, if you
need a short delay between the toggling of a control line/device select line or port pin, simply add some NOP
instructions. The following code snippet illustrates the usage of NOP instruction in programming.
SETB P2.0 ; Pull P2.0 line HIGH
NOP ; Hold P2.0 line HIGH for 2 machine cycles
NOP
CLR P2.0 ; Release P2.0 line

[Link] Condi onal Program Control Transfer Instruc ons

The conditional program control transfer instructions transfer the program flow depending on certain
conditions. The program flow is diverted from the normal line only if a specified condition is met. The
conditional program control transfer instructions supported by 8051 are listed below.

Instruction Action Comments Machine Exec. Time

Mnemonic Cycles (ms)
If (A == 0) Jump to the relative address ‘rel’ if Accumulator
JZ rel 2 2*(fOSC/12)
Jump to ‘rel’ content is zero.
If (A != 0) Jump to the relative address ‘rel’ if Accumulator
JNZ rel 2 2*(fOSC/12)
Jump to ‘rel’ content is non zero.
Decrement the contents of <loc> and jumps to
<loc>=<loc>–1
the relative address ‘rel’ if content of <loc> is non
DJNZ <loc>, rel If(<loc>!=0) 2 2*(fOSC/12)
zero <loc> can be a direct memory or scratchpad
Jump to ‘rel’
registers R0 through R7 or any SFR.
 Programming the 8051 Microcontroller 199

Compares the content of Accumulator with the

CJNE A, <loc>, If (A!=<loc>) content of <loc> and jumps to the relative address
2 2*(fOSC/12)
rel Jump to ‘rel’ ‘rel’ if both are not equal. <loc> can be a direct
memory or an immediate constant.
Compares the content of <loc> with an immedi-
ate constant and jumps to the relative address
CJNE <loc>, If (<loc>!= #data)
‘rel’ if both are not equal. <loc> can be a memory 2 2*(fOSC/12)
#data, rel Jump to ‘rel’
pointed indirectly or register R0 through R7 or
Accumulator.

All the conditional branching instructions specify the destination address by relative offset method and
so the jump locations are limited to –128 to +127 bytes from the instruction following the conditional jump
instruction. Even if the user specifies the actual address, the assembler converts it to an offset at the time of
assembling the code.
Unlike the 8085 and 8086 CPU architecture, there is no zero flag for 8051. The instructions JZ and
JNZ instructions implement the zero flag check functionality by checking the accumulator content for zero.
DJNZ instruction is used for setting up loop control and generating delays. CJNE instruction compares two
variables and check whether they are equal. CJNE instruction in combination with the carry flag can be used
for testing the conditions ‘greater than’, ‘greater than or equal’ and ‘less than’. The two bytes in the operand
field of CJNE are taken as unsigned integers. If the first is less than the second, the Carry bit is set (1). If
the first is greater than or equal to the second, the carry bit is cleared. Boolean instructions are also used for
conditional program control transfer. Please refer to the “Program Control Transfer based on bit status” under
the Boolean Instructions section for more details.
Please refer to the Online Learning Centre for the Complete 8051 Instruction Set reference

Summary
� An Instruction consists of two parts namely; Opcode and Operand(s). The Opcode tells the processor
what to do on executing an instruction. Operand(s) is the parameter(s) required by opcode LO1
to complete the action
� Addressing Mode refers to the way in which an operand is specified in an instruction along with the
opcode LO1
� Direct Addressing, Indirect Addressing, Register Addressing, Immediate Addressing and Indexed
Addressing are the addressing modes supported by 8051 LO1
� Instructions in which the register operand is implicitly specified by some bits of the opcode referred
as register Instructions, whereas instructions which implicitly work on certain specific
registers are known as Register Specific Instructions LO2
� The instruction set of 8051 family microcontroller is broadly classified into five categories, namely;
Data transfer instructions, Arithmetic instructions, Logical instructions, Boolean
LO2
instructions and Program Control Transfer instructions
� ‘Stack’ is an internal memory for storing variables temporarily. The instruction PUSH saves data
to the stack and the instruction POP retrieves the pushed data from the stack memory LO2
� Data transfer instructions transfer data between a source and destination. The data transfer can be
between register or memory (internal or external). Arithmetic instructions perform arithmetical
operations like addition, subtraction, multiplication, division, increment and decrement LO2
200 Introduc on to Embedded Systems

� Logical instructions perform logical operations such as ‘ORing’, ‘ANDing’, ‘XORing’,

complementing, clearing, bit rotation and swapping nibbles of a byte, etc LO2
� Boolean instructions perform various operations like bit transfer, bit manipulation, logical
operations on bits, program control transfer based on bit state, etc. The carry bit ‘C’, present in the
Special Function Register PSW, takes the role of Accumulator in all bit related LO2
operations
� Program Control transfer instructions change the program execution flow. The 8051 instruction set
supports two types of program control transfer instructions namely; Unconditional
LO2
program control instructions and Conditional program control instructions
� The unconditional program control instructions transfer the program flow to any desired location
in the code memory. JMP, CALL, RET, RETI and NOP are the unconditional program
control transfer instructions in 8051 instruction set LO2
� The conditional program control transfer instructions transfer the program flow depending on
certain conditions. The program flow is diverted from the normal line only if a specified condition is
met. Jump on Zero (JZ), Jump on Non Zero (JNZ), Decrement and Jump if Non Zero (DJNZ),
Compare and Jump if not equal (CJNE), Jump if specified bit is set (JB), Jump if specified bit is not
set (JNB), Jump if the bit is set and clear the bit (JBC), Jump if Carry flag is set (JC) and Jump if
Carry flag is not set (JNC) are the conditional program control transfer instructions in
8051 LO2
� The DJNZ instruction is used for setting up loop control and generating delays. CJNE instruction
compares two variables and check whether they are equal. CJNE instruction in combination with
the Carry flag can be used for testing the conditions ‘greater than’, ‘greater than or equal’ LO2
and ‘less than’

Keywords
Opcode: The command that tells the processor what to do on execu ng an instruc on [LO 1]
Operand(s): The parameter(s) required by an opcode to complete the ac on [LO 1]
Addressing Mode: The way in which an operand is specified in an instruc on along with opcode [LO 1]
Direct Addressing: The addressing mode in which the operand is specified as direct memory address [LO 1]
Indirect Addressing: The addressing mode in which the operand is specified as memory address indirectly,
using indirect addressing registers [LO 1]
Register Addressing: Addressing mode in which the operand is specified as Registers [LO 1]
Register Instruc ons: Instruc ons in which the register operand is implicitly specified by some bits of the
opcode [LO 1]
Register Specific Instruc ons: Instruc ons which implicitly work on certain specific registers only [LO 1]
Immediate Addressing: Addressing mode in which the operand is specified as immediate constants [LO 1]
Indexed Addressing: Addressing mode in which the operand is specified through an index register [LO 1]
Data Transfer Instruc ons: Instruc ons for transferring data between a source and des na on [LO 2]
Stack: Internal memory for storing variables temporarily [LO 2]
PUSH: Instruc on for pushing data to the stack memory [LO 2]
POP: Instruc on for retrieving the pushed data bytes from stack memory [LO 2]
 Programming the 8051 Microcontroller 201

Data Exchange Instruc ons: Instruc ons for exchanging data between a memory loca on and the accumulator
register in 8051 architecture [LO 2]
External Data Memory Instruc on: Instruc on for transferring data between external memory and processor
[LO 2]
Arithme c Instruc ons: Instruc ons for performing basic arithme c opera ons including addi on, subtrac on,
mul plica on, division, increment and decrement [LO 2]
2’s Complement: A binary data representa on used in subtrac on opera on [LO 2]
Binary Coded Decimal (BCD): Numbers with base 10. Represented using digits 0 to 9 [LO 2]
Unpacked BCD: A single BCD digit (0 to 9) represented in a single byte [LO 2]
Packed BCD: Two BCD digits (00 to 99) represented using a single byte [LO 2]
Decimal Adjust Accumulator (DAA): An instruc on for adjus ng the accumulator content to give a meaningful
BCD, a er BCD arithme c [LO 2]
Logical Instruc ons: Instruc ons for performing logical opera ons such as ‘ORing’, ‘ANDing’, ‘XORing’,
complemen ng, clearing, bit rota on and swapping nibbles of a byte, etc [LO 2]
Boolean Instruc ons: Instruc ons for performing various opera ons like bit transfer, bit manipula on, logical
opera ons on bits, program control transfer based on bit state, etc [LO 2]

Objec ve Ques ons

1. What are the different addressing modes supported by 8051?
(a) Direct Addressing (b) Indirect Addressing
(c) Register Addressing (d) Indexed Addressing
(e) Immediate Addressing (f) All of these
2. Which is the addressing mode for the instruction MOV A, #50H
(a) Direct (b) Indirect (c) Immediate (d) None of these
3. Which is the addressing mode for the instruction MOV A, 50H
(a) Direct (b) Indirect (c) Immediate (d) None of these
4. Which is the addressing mode for the instruction MOV A, @R0
(a) Direct (b) Indirect (c) Immediate (d) None of these
5. Which is the addressing mode for the instruction MOVC A, @A+DPTR
(a) Direct (b) Indirect (c) Immediate (d) None of these
6. Code memory starting from 0050H holds a lookup table of 10 bytes. The first element of the lookup table is
00H. What is the content of accumulator after executing the following piece of code?
MOV A, #00H
LCALL TABLE
NOP
ORG 004EH
TABLE: MOVC A, @A+PC
RET
(a) 00H (b) 22 (c) 22H (d) Undefined
(e) None of these
202 Introduc on to Embedded Systems

7. Register R0 contains 50H and Accumulator contains 01H. What will be the contents of R0 and A after
executing the instruction MOV A,R0
(a) R0 = 01H; A = 01H (b) R0 = 50H; A = 01H
(c) R0 = 01H; A = 50H (d) R0 = 50H; A = 50H
(e) None of these
8. Data memory location 00H contains F0H and Stack Pointer (SP) contains 07H. What will be the contents of
memory location 00H and SP after executing the instruction PUSH 00H
(a) Data memory location 00H = 07H; SP = 07H
(b) Data memory location 00H = F0H; SP = 07H
(c) Data memory location 00H = F0H; SP = 08H
(d) Data memory location 00H = F0H; SP = 06H
(e) None of these
9. Data memory location 00H contains F0H and Stack Pointer (SP) contains 08H. The memory location 08H
contains 0FH. What will be the contents of memory location 00H, 08H and SP after executing the instruction
POP 00H
(a) Memory location 00H = 0FH; Memory location 08H = F0H; SP = 08H
(b) Memory location 00H = F0H; Memory location 08H = F0H; SP = 07H
(c) Memory location 00H = 0FH; Memory location 08H = 0FH; SP = 07H
(d) Memory location 00H = 0FH; Memory location 08H = 0FH; SP = 09H
(e) None of these
10. Data memory location 0FH contains 00H and the accumulator contains FFH. What will be the contents of
data memory location 0FH and the accumulator after executing the instruction XCH A, 0FH
(a) Memory location 0FH = 00H; Accumulator = FFH
(b) Memory location 0FH = 00H; Accumulator = 00H
(c) Memory location 0FH = FFH; Accumulator = 00H
(d) Memory location 0FH = FFH; Accumulator = FFH
(e) None of these
11. Data memory location 0FH contains A5H, Accumulator contains 5AH and register R0 contains 0FH.
What will be the contents of data memory location 0FH, Register R0 and accumulator after executing the
instruction XCHD A, @R0
(a) Memory location 0FH = A5H; Accumulator = 5AH; R0 = 0FH
(b) Memory location 0FH = 55H; Accumulator = AAH; R0 = 0FH
(c) Memory location 0FH = AAH; Accumulator = 55H; R0 = 0FH
(d) Memory location 0FH = A5H; Accumulator = 55H; R0 = AAH
(e) None of these
12. Register DPTR holds 2050H. Explain the result of executing the instruction MOVX @DPTR, A
(a) P2 SFR = 20H; P1 SFR = 50H during the first machine cycle; RD\ signal is asserted once
(b) P2 SFR = 50H; P1 SFR = 20H during the first machine cycle; RD\ signal is asserted once
(c) P2 SFR = 20H; P1 SFR = 50H during the first machine cycle; WR\ signal is asserted once
(d) P2 SFR = 50H; P1 SFR = 20H during the first machine cycle; WR\ signal is asserted once
(e) None of these
13. The Program Strobe Enable (PSEN) signal is asserted during program fetching if
(a) The program memory is external to the controller
(b) The Program memory is internal to the controller
(c) The Program memory is either internal or external to the controller
14. How many program fetches occur per machine cycle?
(a) 1 (b) 2 (c) 3 (d) 4
 Programming the 8051 Microcontroller 203

15. How many ‘program memory fetches’ are skipped during the execution of MOVX instruction?
(a) 1 (b) 2 (c) 3 (d) 4
16. The Address Latch Enable (ALE) signal is asserted how many times in a machine cycle?
(a) 1 (b) 2 (c) 3 (d) 4
17. How many times the ALE signal is skipped during the execution of a MOVX instruction?
(a) 1 (b) 2 (c) 3 (d) 4
18. Which of the following is true about MOVC instruction
(a) Used for reading from Program memory (b) Uses Indexed Addressing technique
(c) Both a & b (d) None of these
19. The content of Accumulator is FFH and the Carry Flag is in the cleared state. What will be the contents of
Accumulator and carry flag after executing the instruction ADD A,#1
(a) Accumulator = 01H; Carry flag = 1 (b) Accumulator = 01H; Carry flag = 0
(c) Accumulator = 00H; Carry flag = 0 (d) Accumulator = 00H; Carry flag = 1
20. Accumulator register contains 0FH and the Carry flag CY is in the set state. What will be the state of Carry
flag after executing the instruction ADD A,#0F0H
(a) 1 (b) 0 (c) Indeterminate
21. The content of the accumulator is FFH and the Carry flag is in the cleared state. What will be the contents of
the accumulator and carry flag after executing the instruction ADDC A,#1
(a) Accumulator = 01H; Carry flag = 1 (b) Accumulator = 01H; Carry flag = 0
(c) Accumulator = 00H; Carry flag = 0 (d) Accumulator = 00H; Carry flag = 1
22. Accumulator register contains 0FH and the Carry flag CY is in the cleared state. What will be the contents
of Carry flag and Accumulator after executing the instruction SUBB A,#0F0H
(a) Accumulator = E1H; Carry flag = 1 (b) Accumulator = E1H; Carry flag = 0
(c) Accumulator = 1FH; Carry flag = 0 (d) Accumulator = 1FH; Carry flag = 1
23. Accumulator register contains F0H and the Carry flag CY is in the cleared state. What will be the contents
of the Carry flag and the accumulator after executing the instruction SUBB A,#0FH
(a) Accumulator = E1H; Carry flag = 1 (b) Accumulator = E1H; Carry flag = 0
(c) Accumulator = 1FH; Carry flag = 0 (d) Accumulator = 1FH; Carry flag = 1
24. Accumulator register contains 0FFH and the B register contains 02H. What will be the contents of the
Accumulator and B register after executing the instruction MUL AB
(a) Accumulator = 0FEH; B = 01H (b) Accumulator = 00H; B = 0FEH
(c) Accumulator = 0FEH; B = 00H (d) Accumulator = 01H; B = 0FEH
25. Accumulator register contains 0FFH, B register contains 02H and the Carry flag is in the cleared state. What
will be the contents of the Carry flag and Overflow flag after executing the instruction MUL AB
(a) Carry flag = 1; Overflow flag = 0
(b) Carry flag = 0; Overflow flag = Remains same as the previous value
(c) Carry flag = 1; Overflow flag = 1
(d) Carry flag = 0; Overflow flag = 1
26. Accumulator register contains 0FFH, B register contains 02H and the Overflow flag is in the cleared state.
What will be the contents of the Carry flag and Overflow flag after executing the instruction MUL AB
(a) Carry flag = remains same as the previous value; Overflow flag = 0
(b) Carry flag = remains same as the previous value; Overflow flag = 1
(c) Carry flag = 1; Overflow flag = 1
(d) Carry flag = 0; Overflow flag = 1
27. Accumulator contains 0FFH and the B Register contains 02H. What will be the contents of the accumulator
and B register after executing the instruction DIV AB
204 Introduc on to Embedded Systems

(a) Accumulator = 01H; B = 7FH (b) Accumulator = 7FH; B = 01H

(c) Accumulator = 7FH; B = 00H (d) Accumulator = 00H; B = 7FH
28. Accumulator register contains 0FFH and the B register contains 0H. What will be the contents of the
accumulator, B register and Overflow flag after executing the instruction DIV AB
(a) Accumulator = 00H; B = 00H; Overflow flag = 1
(b) Accumulator = 0FFH; B = 00H; Overflow flag = 0
(c) Accumulator = Undefined; B = Undefined; Overflow flag = 1
(d) Accumulator = Undefined; B = Undefined; Overflow flag = 0
29. Accumulator register contains 0FFH and the Carry flag CY is in the cleared state. What will be the contents
of Carry flag and the accumulator after executing the instruction INC A
(a) Accumulator = 00H; Carry flag = 1 (b) Accumulator = 00H; Carry flag = 0
(c) Accumulator = 01H; Carry flag = 0 (d) Accumulator = 01H; Carry flag = 1
30. Accumulator register contains 00H and the Carry flag CY is in the cleared state. What will be the contents
of Carry flag and Accumulator after executing the instruction DEC A
(a) Accumulator = 00H; Carry flag = 1 (b) Accumulator = 00H; Carry flag = 0
(c) Accumulator = FFH; Carry flag = 0 (d) Accumulator = FFH; Carry flag = 1
31. DPTR contains 2050H. What will be the content of DPTR after executing the following instructions
XCH A, DPL
DEC A
CJNE A, #0FFH, skip_dec
DEC DPH
skip_dec:
XCH A, DPL
(a) 2050H (b) 2049H (c) 2051H (d) 204FH
32. Accumulator register contains 0FH. What will be the content of the accumulator after executing the instruction
DA A
(a) 0FH (b) 15 H (c) 15 (d) 00H
33. Accumulator register contains the BCD number 28. What will be the content of the accumulator after
executing the instruction ADD A,#12H
(a) 40H (b) 3AH (c) 40 (d) None of these
34. Accumulator register contains the BCD number 28. What will be the content of the accumulator after
executing the following instructions
ADD A,#12H
DAA
(a) 40H (b) 3AH (c) 40 (d) None of these
35. Accumulator register contains 0FH. What will be the content of the accumulator after executing the
instruction ORL A, #0F0H
(a) 0FH (b) F0H (c) FFH (d) 00H
36. Accumulator register contains 0FH. What will be the content of the accumulator after executing the
instruction ANL A, #0F0H
(a) 0FH (b) F0H (c) FFH (d) 00H
37. Accumulator register contains 0AAH. What will be the content of the accumulator after executing the
instruction XRL A, #0D5H
(a) AAH (b) 7FH (c) D5H (d) FFH
38. Accumulator register contains 7FH and carry flag is in the set state. What will be the contents of Accumulator
and carry flag after executing the instruction CLR A
 Programming the 8051 Microcontroller 205

(a) Accumulator = 7FH; Carry flag = 0 (b) Accumulator = 7FH; Carry flag = 1
(c) Accumulator = 00H; Carry flag = 0 (d) Accumulator = 00H; Carry flag = 1
39. What changes will happen on executing the instruction CLR 00H
(a) The code memory location 00H becomes 00H
(b) The data memory location 00H becomes 00H
(c) The external data memory location 00H becomes 00H
(d) The LS Bit of the data held by data memory location 20H becomes 0
40. Accumulator register contains 0FH and carry flag is in the set state. What will be the contents of the
Accumulator and carry flag after executing the instruction CPL A
(a) Accumulator = 0FH; Carry flag = 0 (b) Accumulator = 0FH; Carry flag = 1
(c) Accumulator = F0H; Carry flag = 0 (d) Accumulator = F0H; Carry flag = 1
41. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of Accumulator
and carry flag after executing the instruction RL A
(a) Accumulator = 02H; Carry flag = 0 (b) Accumulator = 02H; Carry flag = 1
(c) Accumulator = 80H; Carry flag = 0 (d) Accumulator = 80H; Carry flag = 1
42. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of Accumulator
and carry flag after executing the instruction RLC A
(a) Accumulator = 02H; Carry flag = 0 (b) Accumulator = 02H; Carry flag = 1
(c) Accumulator = 03H; Carry flag = 0 (d) Accumulator = 03H; Carry flag = 1
43. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of the
accumulator and carry flag after executing the instruction RR A
(a) Accumulator = 02H; Carry flag = 0 (b) Accumulator = 02H; Carry flag = 1
(c) Accumulator = 80H; Carry flag = 0 (d) Accumulator = 80H; Carry flag = 1
44. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of the
accumulator and carry flag after executing the instruction RRC A
(a) Accumulator = 80H; Carry flag = 0 (b) Accumulator = 80H; Carry flag = 1
(c) Accumulator = 03H; Carry flag = 0 (d) Accumulator = 03H; Carry flag = 1
45. Accumulator register contains 5FH. What will be the content of the accumulator after executing the instruction
SWAP A
(a) 00H (b) F5H (c) 5FH (d) 00H
46. What changes will happen on executing the instruction CPL 00H
(a) The code memory location 00H becomes 00H
(b) The data memory location 00H becomes 00H
(c) The external data memory location 00H becomes 00H
(d) The LS Bit of the data held by data memory location 20H is complemented
47. The carry bit is in the set state and the port status bit P1.0 is in the cleared state. What will be the values of
Carry bit and P1.0 after executing the instruction ANL C, /P1.0
(a) Carry flag = 0; P1.0 = 0 (b) Carry flag = 0; P1.0 = 1
(c) Carry flag = 1; P1.0 = 0 (d) Carry flag = 1; P1.0 = 1
48. The Carry bit is in the cleared state and the Port status bit P1.0 is in the cleared state. What will be the values
of Carry bit and P1.0 after executing the instruction ORL C, /P1.0
(a) Carry flag = 0; P1.0 = 0 (b) Carry flag = 0; P1.0 = 1
(c) Carry Flag = 1; P1.0 = 0 (d) Carry flag = 1; P1.0 = 1
49. Which of the following Jump instruction is the optimal instruction if the offset (relative displacement of
jump location from the current instruction location) of the jump location is greater than 127 and less than
–128 and is within the same 2K block of the current instruction
206 Introduc on to Embedded Systems

(a) AJMP (b) SJMP (c) LJMP (d) All of these

50. The program execution needs to be diverted to a location within the 2K memory block of the current instruction
and the 11 least significant bits of the code memory address to which the jump is intended is 050FH. The
AJMP instruction is used for implementing the jump. What is the machine code for implementing the AJMP
instruction for jumping to the specified location?
(a) 01H, 0FH, 05H (b) 01H, 05H, 0FH (c) A1H, 0FH (d) None of these
51. Which of the following Jump instruction encodes the jump location as absolute memory address
(a) SJMP (b) AJMP (c) LJMP (d) All of these
(e) only (b) and (c)
52. All the conditional branching instructions specify the destination address by
(a) Relative offset method
(b) Absolute address method
(c) Either relative or absolute address method
(d) None of these

Review Ques ons

1. Explain with examples the different addressing modes supported by 8051 CPU. [LO 1]
2. What is the difference between Register Instructions and Register Specific Instructions? Give an example for
each. [LO 2]
3. What is the difference between Immediate addressing and Indexed addressing? State where these addressing
techniques are used. Give an example for each. [LO 1]
4. What is Data transfer instruction? Explain the different data transfer instructions supported by 8051 CPU.
[LO 2]
5. Explain the arithmetic operations/instructions supported by 8051 CPU. [LO 2]
6. Accumulator register contains 01H and Carry flag is in the state. What will be the contents of accumulator
and Carry flag on executing the instruction [LO 1, LO 2]
RR A
RR C A
7. Examine the following piece of code and explain whether the program will work in the expected way. Justify
your statement [LO 1, LO 2]
MOV P1.0, P1.2
8. In the following code snippet, the jump location is intended to a memory address with offset beyond +127.
Suggest a workaround to solve this issue [LO 1, LO 2]
CJNE A,#01H, JUMP_HERE
..............................
...............................
;The relative address of label ‘ JUMP_HERE ‘ is greater than 127 JUMP_HERE: XCH A,B
9. Explain the stack memory related data transfer instructions in detail. [LO 1, LO 2]
10. Explain the data exchange instructions in detail with examples. [LO 1, LO 2]
11. Explain the timing diagram for the MOVX instruction execution when the program memory is internal to the
processor. [LO 1, LO 2]
 Programming the 8051 Microcontroller 207

12. Explain the difference between ADD, ADDC and DAA instructions. Explain the significance of DAA
instruction? [LO 1, LO 2]
13. Explain the instruction for division operation. How is a divide by zero condition handled in the 8051
architecture? [LO 1, LO 2]
14. Explain the different logical operations supported by 8051 and the corresponding instruction in detail.
[LO 1, LO 2]
15. Explain the different Boolean instructions supported by 8051. [LO 1, LO 2]
16. Explain the different unconditional program control transfer instructions supported by 8051.[LO 1, LO 2]
17. Explain the different conditional program control transfer instructions supported by 8051. [LO 1, LO 2]
18. Explain the implementation of switch() case statement using jump tables. [LO 1, LO 2]
19. The 8051 status register doesn’t contain a zero flag. Explain how the 8051 architecture implements the Jump
on zero and Jump on non-zero conditions. [LO 1, LO 2]
20. Explain the difference between LCALL and ACALL for subroutine invocation? Which one is faster in
execution and why? [LO 1, LO 2]
21. Explain the difference between RET and RETI instructions. [LO 1, LO 2]
22. Explain the different types of jumps supported by 8051 architecture. Which one is faster in execution and
why? [LO 1, LO 2]

Lab Assignments
1. A lookup table with 6 bytes is stored in code memory location starting from 8000H. Write a small 8051
assembly program to read the lookup table
2. Implement a BCD counter to count from 00 to 99 with a delay of 1 second between the successive counts.
Display the count using two 7-Segment LED displays in multiplexed configuration
3. Optimise the following piece of code (Rewrite the code with instructions/operations giving the same
functionality) for memory size and performance
ORG 0000H
JB P1.0, PORT_SET
MOV A, #50H
LJMP SKIP
PORT_SET: CLR P1.0
SKIP: LCALL DELAY
ORG 0050H
DELAY: NOP
NOP
RET

4. Write a 8051 assembly language program using timer interrupt for generating a 50 Hz square wave at the
port pin P1.0. The oscillator frequency applied to the microcontroller is 12.00MHz
5. Write a 8051 assembly language program for generating a 5 kHz square wave at the port pin P1.0. The
oscillator frequency applied to the microcontroller is 12.00 MHz.
208 Introduc on to Embedded Systems

6. Write a 8051 Assembly language program to generate the Fibonacci series of a given number. Assume the
number whose Fibonacci number is to be calculated is received from the hyper terminal application
running on a PC to which the microcontroller is interfaced. Upon receiving the number from the hyper
terminal application, the Fibonacci series for the number is generated and it is sent to the hyper terminal
application running on the PC. The program also inserts the character ‘,’ to separate the two consecutive
numbers in the series while sending it. The numbers are sent with their corresponding ASCII value (e.g.
0 is sent as 30H). The serial communication parameter settings for both hyper terminal application and
microcontroller program are: baudrate = 9600, 1 start bit, 8 data bits, 1 stop bit, No parity. Use a crystal
resonator with frequency 11.0592MHz for designing the microcontroller hardware.
7. Write a 8051 assembly language program to find the largest number from an array of 10 numbers. The
array is located in the data memory and the start address of the array is 20H.
8. Write a 8051 assembly language program to generate a PWM signal of ON time 100 microseconds and
duty cycle of 39.06%, at port pin P1.0
9. Explain with code snippet how the 8051 timer can be used for the measurement of the width of an
unknown pulse
10. It is required by an experimental setup to count the number of pulses arrived during a time period of 50
milliseconds. Explain with code snippets how it can be implemented using the 8051 timers.