Name of Institution
Amity School of Engineering &
Technology
[Link]. CSE, Semester V
Computer Architecture
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Name of Institution
Module – 5
Multiprocessors
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Multiprocessor Name of Institution
A multiprocessor is a computer with multiple processors in one unit.
At various levels of solving a problem, the processors of a
multiprocessor system may be able to interact and cooperate.
The processors communicate with one another by passing messages
or by sharing a common memory.
Two or more CPUs make up a multiprocessor system.
The term “processor” can refer to either a central processing
unit (CPU) or an input-output processor in a multiprocessor (IOP).
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Characteristics of Multiprocessor
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The following are the important characteristics of multiprocessors.
1. Parallel Processing: This requires the use of many processors at
the same time.
2. Distributed Computing: In addition to parallel computing, this
distributed processing requires the use of a processor network.
3. Supercomputing: This entails using the quickest machines to
address large, computationally difficult issues.
4. Pipelining: a method that divides a task into multiple subtasks
that must be completed in a specified order.
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Characteristics of Multiprocessor
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5. Vector Computing: This is a method that divides a task into
multiple subtasks that must be completed in a specified order.
6. Systolic: arrangement of processors in an array where data flows
synchronously between neighbouring processors from one step to
the next.
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Interconnection Structures
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Interconnection structures in multiprocessor systems are the physical
configurations that connect CPUs, memory, and I/O devices.
There are five types of Interconnection Structures:
1. Time-shared/ Common bus.
2. Multiport memory.
3. Crossbar switch.
4. Multistage switching network.
5. Hypercube system.
Each has different characteristics in terms of
performance, cost, and complexity. 6
Interconnection Structures
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1. Time-shared common bus:
The time-shared common bus interconnection structures provide a
common communication path by connecting all the functional units
like I/O processor, processor, memory unit, etc.
▪ Only one processor can communicate with the memory.
▪ Overall transfer rate within the system is limited by the speed of the
single path.
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Interconnection Structures
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2. Multiport memory
Here, separate buses for every memory module and CPU. Every processor
in a multiport memory is connected to each memory unit.
Advantages:
- The high transfer rate can be achieved because of the multiple paths.
Disadvantages:
- It requires expensive
memory control logic
and a large number of
cables and connections
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Interconnection Structures
Name of Institution
3. Crossbar switch
It consists of several intersection cross-points between processor buses
and memory module paths. Each switch point has control logic.
Advantages:
- Supports simultaneous transfers from all memory modules
Disadvantages:
- hardware required to
implement the switch
is large and complex.
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Interconnection Structures
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4. Multistage switching network
It is a two-input, two output interchange switch.
Advantages:
- Supports simultaneous transfers from all memory modules
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Interconnection Structures
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5. Hypercube System
Here, we can connect 𝑁 = 2𝑛 processors, and each of the processors
forms a node for the cube.
Each processor forms a node of the cube, in effect it contains not
only a CPU but also local memory and I/O interface.
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Inter-processor Arbitration
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Inter-processor arbitration is a mechanism used in multiprocessor
systems to resolve conflicts when multiple processors or devices try
to access a shared resource, like a bus or memory, at the same time.
It acts as a mediator/controlling device that decides;
which request gets priority, granting access to only one at a time to
prevent data conflicts and ensure efficient data transfer.
For detailed information, go to Module 4 (Bus Arbitration Techniques)
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Inter-processor communication and synchronization
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Inter-processor communication is the process of exchanging data and
signals between different processors.
Synchronization ensures these communications happen in an
orderly and controlled manner, preventing conflicts when accessing
shared resources.
- The communication efficiency of the inter-processor network
depends on the communication routing protocol, processor speed,
data link speed, and the topology of the network.
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Advanced computer architecture
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Advanced Computer Architecture focuses on improving the speed,
efficiency, scalability, parallelism of computer systems and energy
efficiency in computing systems.
It explores how processors, memory, and I/O
systems are designed and optimized to execute programs efficiently.
Processor Designer Year Type Word Size
Intel Pentium Intel 1993 CISC 32-bit
Intel Pentium Pro Intel 1995 CISC 32-bit
Apple–IBM–Motorola 32-bit/
PowerPC 1991– RISC
(AIM) 64-bit
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Advanced computer architecture
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The main features that distinguish advanced architectures;
1. Pipelining
2. Superscalar Processing
3. Dynamic Execution
4. Parallel Processing
5. Cache Hierarchy and Memory Optimization
6. Multiprocessor and Multicore Systems
7. RISC and CISC Architectures
8. Vector and Array Processing
9. Interconnection Networks
10. Advanced Architectures (Emerging Trends) 15
Advanced computer architecture
Name of Institution
1. Pipelining: Breaking instruction execution into multiple stages so different instructions are
processed simultaneously.
2. Superscalar Processing: Multiple instructions are issued and executed in parallel within one clock
cycle.
3. Dynamic Execution: Instructions are executed as soon as their operands are ready, not necessarily
in the program order.
4. Parallel Processing: Using multiple processors or cores to execute different tasks simultaneously.
5. Cache Hierarchy and Memory Optimization: Using multiple cache levels (L1, L2, L3) to reduce
memory access time.
6. Multiprocessor and Multicore Systems: Multiple CPUs in one system and multiple cores on a
single chip sharing memory.
7. RISC and CISC Architectures
8. Vector and Array Processing
9. Interconnection Networks: Communication pathways that connect processors, memory modules,
and I/O devices.
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10. Advanced Architectures (Emerging Trends): Combining CPUs, GPUs, and AI accelerators
Pentium Processor (P5 Architecture)
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Introduced by Intel in 1993.
It is a superscalar processor, meaning it can
execute more than one instruction per clock cycle.
Architecture Features
1. Superscalar Architecture
Has two instruction pipelines.
It can execute two instructions simultaneously if they are independent.
2. 32-bit Data Bus and 64-bit External Bus
Internally, it has 32-bit data bus.
Externally, it has a 64-bit data bus for faster memory access.
3. Instruction Pipeline: Pentium uses a five-stage pipeline
4. Separate Caches: two on-chip 8 KB caches: One for instruction
and one for data.
5. Bus Interface Unit (BIU): Controls data flow between the CPU
and external memory.
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Pentium Processor Name of Institution
Performance:
• Clock speed ranged from 60 MHz to 200 MHz.
• Achieved ~100 MIPS (Million Instructions Per Second) performance.
• Used in early desktop PCs and servers.
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Pentium Pro Processor (P6 Architecture)
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Introduced in 1995 as a successor to Pentium.
Designed mainly for servers and high-performance
computers.
It introduced out-of-order execution.
Architecture Features
1. Superpipelined and Superscalar Architecture
Has multiple pipelines and supports speculative, out-of-order
execution.
2. Pentium Pro used a 14-stage pipeline.
3. L2 Cache Integration
Includes 256 KB, 512 KB, or 1 MB L2 cache
Cache runs at full CPU clock speed, greatly increasing
performance.
4. 32-bit Processor: optimized for 32-bit operating systems.
5. Advanced pipelined Bus Interface for higher bandwidth.
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Pentium Pro Processor (P6 Architecture)
Name of Institution
Performance:
• Clock speeds from 150 MHz to 200 MHz.
• Better performance in 32-bit code and server workloads.
• Laid the foundation for later CPUs like Pentium II, Pentium III, and
Core processors.
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PowerPC ArchitectureName of Institution
PowerPC Architecture are microprocessor for
personal computers.
PowerPC is a RISC (Reduced Instruction
Set Computer) architecture which are very
powerful and low-cost microprocessors.
RISC architecture tries to keep the
processor as busy as possible.
Key Features
•RISC Design: Emphasizes simple instructions that execute in a single
cycle, leading to efficient pipelining and high performance.
•32-bit and 64-bit Support: Offers both 32-bit and 64-bit implementations.
•Superscalar Architecture: Capable of executing multiple instructions
per clock cycle, enhancing throughput.
•Floating-Point Support: Includes separate registers and units for
floating-point operations, improving computational efficiency.
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Name of Institution
Thank You!
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