Pipelining
Overview
Pipelining is widely used in modern
processors.
Pipelining improves system performance in
terms of throughput.
Pipelined organization requires sophisticated
compilation techniques.
Making the Execution of
Programs Faster
Use faster circuit technology to build the
processor and the main memory.
Arrange the hardware so that more than one
operation can be performed at the same time.
In the latter way, the number of operations
performed per second is increased even though
the elapsed time needed to perform any one
operation is not changed.
Traditional Pipeline Concept
Ann,Brian, Cathy, Dave
each have one load of clothes A B C D
to wash, dry, and fold
Washer takes 30 minutes
Dryer takes 40 minutes
“Folder” takes 20 minutes
Traditional Pipeline Concept
6 PM 7 8 9 10 11 Midnight
Time
30 40 20 30 40 20 30 40 20 30 40 20
Sequential laundry takes 6
A hours for 4 loads
If they learned pipelining, how
long would laundry take?
B
D
Traditional Pipeline Concept
6 PM 7 8 9 10 11 Midnight
Time
T 30 40 40 40 40 20
a
A
s
Pipelined laundry takes 3.5 hours
k for 4 loads
B
O
r C
d
e D
r
Traditional Pipeline Concept
Pipelining doesn’t help
6 PM 7 8 9
latency of single task, it
Time helps throughput of entire
workload
T
a 30 40 40 40 40 20 Pipeline rate limited by
slowest pipeline stage
s
A Multiple tasks operating
k
simultaneously using
different resources
O B
Potential speedup = Number
r pipe stages
d C Unbalanced lengths of pipe
e stages reduces speedup
r
D Time to “fill” pipeline and
time to “drain” it reduces
speedup
Stall for Dependences
Use the Idea of Pipelining in a
Computer
Fetch + Execution
Time
I1 I2 I3
Time
Clock cycle 1 2 3 4
F E F E F E
1 1 2 2 3 3 Instruction
I1 F1 E1
(a) Sequential execution
I2 F2 E2
Interstage buffer
B1
I3 F3 E3
Instruction Execution
fetch unit (c) Pipelined execution
unit
Figure 8.1. Basic idea of instruction pipelining.
(b) Hardware organization
Time
Clock cy cle 1 2 3 4 5 6 7
Instruction
I1 F1 D1 E1 W1
I2 F2 D2 E2 W2
I3 F3 D3 E3 W3
I4 F4 D4 E4 W4
(a) Instruction execution div ided into f our steps
Use the Idea of Pipelining in a Computer
Interstageuff
b ers
D : Decode
F : Fetch instruction E: Execute W : Write
instruction and f etch operation results
operands
B1 B2 B3
(b) Hardware organization
Figure 8.2. A 4-stage pipeline.
Fetch + Decode+ Execution + Write
Role of Cache Memory
Each pipeline stage is expected to complete in one
clock cycle.
The clock period should be long enough to let the
slowest pipeline stage to complete.
Faster stages can only wait for the slowest one to
complete.
Since main memory is very slow compared to the
execution, if each instruction needs to be fetched
from main memory, pipeline is almost useless.
Fortunately, we have cache.
Pipeline Performance
The potential increase in performance
resulting from pipelining is proportional to the
number of pipeline stages.
However, this increase would be achieved
only if all pipeline stages require the same
time to complete, and there is no interruption
throughout program execution.
Unfortunately, this is not true.
Time
Clock c
y cle 1 2 3 4 5 6 7 8 9
Instruction
I1 F1 D1 E1 W1
I2 F2 D2 E2 W2
I3 F3 D3 E3 W3
I4 F4 D4 E4 W4
I5 F5 D5 E5
Pipeline Performance
Figure 8.3. Effect of an xecution
e operation taking more than one ycle.
clock c
Pipeline Performance
The previous pipeline is said to have been stalled for two clock
cycles.
Any condition that causes a pipeline to stall is called a hazard.
Data hazard – any condition in which either the source or the
destination operands of an instruction are not available at the
time expected in the pipeline. So some operation has to be
delayed, and the pipeline stalls.
Instruction (control) hazard – a delay in the availability of an
instruction causes the pipeline to stall.
Structural hazard – the situation when two instructions require
the use of a given hardware resource at the same time.
Pipeline Performance
Time
Clock c ycle 1 2 3 4 5 6 7 8 9
Instruction Instruction
hazard I1 F1 D1 E1 W 1
I2 F2 D2 E2 W 2
I3 F3 D3 E3 W 3
(a) Instruction execution steps in successive clock cycles
Time
Clock c ycle 1 2 3 4 5 6 7 8 9
Stage
F: Fetch F1 F2 F2 F2 F2 F3
D: Decode D1 idle idle idle D2 D3
E: Execute E1 idle idle idle E2 E3
W: Write W 1
idle idle idle W 2
W 3
(b) Function performed by each processor stage in successive clock cycles
Idle periods –
stalls (bubbles)
Figure 8.4. Pipeline stall caused by a cache miss in F2.
Time
Clock cy cle 1 2 3 4 5 6 7
Instruction
I1 F1 D1 E1 W1
I 2 (Load) F2 D2 E2 M2 W2
I3 F3 D3 E3 W3
Pipeline Performance
I4 F4 D4 E4
I5 F5 D5
Figure 8.5. Effect of a Load instruction on pipeline timing.
Load X(R1), R2
Structural
hazard
Pipeline Performance
Again, pipelining does not result in individual
instructions being executed faster; rather, it is the
throughput that increases.
Throughput is measured by the rate at which
instruction execution is completed.
Pipeline stall causes degradation in pipeline
performance.
We need to identify all hazards that may cause the
pipeline to stall and to find ways to minimize their
impact.