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Summer 2022 Digital Electronics Exam

This document outlines the supplementary examination details for the B. Tech course in Digital Electronics at Dr. Babasaheb Ambedkar Technological University, Lonere, for Summer 2022. It includes instructions for students, a breakdown of questions across five sections, and various topics such as K-Maps, flip-flops, finite state machines, and logic families. The exam is designed to assess students' understanding and application of digital electronics concepts.

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10 views2 pages

Summer 2022 Digital Electronics Exam

This document outlines the supplementary examination details for the B. Tech course in Digital Electronics at Dr. Babasaheb Ambedkar Technological University, Lonere, for Summer 2022. It includes instructions for students, a breakdown of questions across five sections, and various topics such as K-Maps, flip-flops, finite state machines, and logic families. The exam is designed to assess students' understanding and application of digital electronics concepts.

Uploaded by

gauravsuryawanshi237
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

DR.

BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE


Supplementary Examination – Summer 2022
Course: B. Tech. Branch: E&TC Semester: III
Subject Code & Name: BTETC303 Digital Electronics
Max Marks: 60 Date: Duration: 3 Hr.
Instructions to the Students:
1. All the questions are compulsory.
2. Use of non-programmable scientific calculators is allowed.
3. Assume suitable data wherever necessary and mention it clearly.
(Level/CO) Marks

Q. 1 Solve Any Two of the following. 12


A) Simplify following expression using K-Map (2) 6
f (A,B,C,D) = Σm (1,4,7,12,13, 14,15) + d (0, 5, 8)
B) Implement Binary to Gray code Converter. (3) 6
C) Draw and explain Binary Full Adder. Design the logic diagram for full adder. (1) 6

Q.2 Solve Any Two of the following. 12


A) Design 3-bit synchronous up counter using JK flip flop. (3) 6
B) Convert D Flip-flop to T flip-flop. (2) 6
C) Draw and explain Universal shift Register. (4) 6

Q. 3 Solve Any One of the following. 12


A) An FSM is given as in the below diagram. find out (3) 12

1. What is the output sequence for the given input data sequence
001010110110110111?
2. What is the behaviour of the above Finite state machine?
3. Decide the Flip-flop which can be used by avoiding external logic gates.
B) a. Explain Basic design steps with example- State diagram, State table, State (4) 12
reduction, State assignment.
b. Explain briefly with the difference between the Mealy model and Moore
model.
Q.4 Solve Any Two of the following. 12
A) Compare Characteristics of TTL, CMOS, ECL, RTL, I2L and DCTL logic families. (3) 6
B) Define and explain: (1,2) 6
i)Fan in and Fan out ii) Noise immunity iii) Propagation Delay
C) Explain in brief the operation of CMOS NAND Gate with schematic (3) 6
diagram.

Q. 5 Solve Any Two of the following. 12


A) Implement given Boolean functions using PLA, PAL and PROM (4) 6
F1 (A,B,C)= Σm(0, 2,6,7)
F2(A,B,C)= Σm(1, 3,4,5,7)
B) Write VHDL code for Mux 4:1 using dataflow and behavioural (4) 6
architecture style.
C) Classify memories RAM and ROM. (3) 6
*** End ***
The grid and the borders of the table will be hidden before final printing.

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