Logic Gates: Previous Year Questions
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ELECTRONICS: LOGIC GATES
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. Which one of the following is a universal gate ?
6. If the input signals (A and B) and output signal
[GATE 2020]
are as below the circuit dlement is
A
B A
(a) AND (b) NOT B
(c) OR (d)NAND
2.
Output
The above combination of logic gates repesents
the operations [GATE 2021] (a) AND gate (b) OR gate
(a) NAND (b) OR (c) NOR gate (d) XOR gate
(c) AND (d) NOR
3. The output Y for the following circuit is 7. The Boolean expression P+ P Q , where P and Q
[HCU PhD 2020] are the inputs to a circuit, represents the following
logic gate
A
Y
(a) AND (b) NAND
B (c) NOT (d) OR
(a) A (b) B 8. The simplest logic gate circuit corresponding to
(c) 0 (d) 1 the Boolean expression, Y = P + PQ is :
[GATE 2008]
4.
P Y
(a) Q
Fig.(i) Fig. (ii)
Figures (i) and (ii) represents respectively,
P
(a) NOR, NOR (b) NOR, NAND
(c) NAND, NAND (d) OR, NAND Y
5. A half-adder can be consructed using two 2 (b)
input logic gates. one of them is an AND gates Q
the other is
P
(a) OR (b) NAND (c) Q Y
(c) NOR (d) EX-OR (d) None of these
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9. Which one of the following DOES NOT repre- _______
(a) y A.B (b) y A.B
sent an exclusive OR operation for inputs A and B
? [GATE 2015] (c) y A.B (d) y A + B
(a) A B AB (b) AB BA 14. For the digital circuit given below, the output X is
[GATE 2016]
(c) A B A B (d) A B AB
A
X
10. Consider the circuit shown below. B
[TIFR 2012] C
A
Y (a) A B C (b) A B C
B
(c) A B C (d) A B C
The minimum number of NAND gates required
to design this circuit is 15.
(a) 6 (b) 5
A
(c) 4 (d) 3
11. The Boolean expression : Z
C
B(A + B) + A. (B +A) can be realized using
minimum number of [GATE 2005] B
(a) 1 AND gate (b) 2 AND gates
(c) 1 OR gate (d) 2 OR gates. The output Z =
12. The circuit shown can be used as
(a) AC AB (b) ABC
[GATE 2005]
(c) ABC ACB (d) ABC CB
Vin 1
Vout 16. Which of the following circuits will act like a 4-
Vin 2 input NAND gate? [JEST 2014]
R
(a)
(a) NOR gate (b) OR gate
(c) NAND gate (d) AND gate (b)
13. The logic circuit shown in the figure below
[NET Dec. 2012]
A (c)
y
HIGH
B
(d)
implements the Boolean expression
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20. Which of the following options is true for a two
17. What is Y for the circuit shown below ? [JEST] input XOR gate ? [GATE 2002]
A Input Output
B Y A B
C
(a) 0 1 1
(a) Y A B B C (b) 1 0 0
(c) 0 0 1
(b) Y A B B C
(d) 1 1 1
(c) Y A B B C
21. 1011 binary input have been applied at
(d) Y A B B C X 3 X 2 X 1 X 0 input in the shown logic circuit made
18. The following circuit (where RL >> R) performs of XOR gates. The binary output Y3Y2Y1Y0 of the
the operation of [GATE 2008] circuit will be
X3 Y3
R X2 Y2
V1
V0
X1 Y1
R
V2
RL
X0 Y0
V1 (a) 1101 (b) 1010
(c) 1111 (d) 0101
(a) OR gate for a negative logic system
22. Shown in the figure is a combination of logic gates.
(b) NAND gate for a negative logic system.
The output values at P and Q are correctly repre-
(c) AND gate for a positive logic system. sented by which of the following ?
(d) AND gate for a negative logic system.
1 P
19. For any set of inputs A and B, the following
circuits give the same output Q, except one.
0 Q
Which one is it ? [GATE 2010]
A (a) 0 0 (b) 1 1
B Q (c) 0 1 (d) 1 0
(a) 23. The output of the following logic circuit can be
simplified to [GATE 2019]
(b) A
Q
B X
Y
A
B Q
Z
(c)
A
(d) Q
B
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(a) X+YZ (b) Y+XZ
A
(c) XYZ (d) X+Y+Z B
24. The timing diagrams for a two input OR gate are C
X
given below. [HCU PhD 2015] B
A
1 C
0 A
F
1 B
0 A
(a) B X
(a) C
B X
(b) (b)
C
(c) B X
(c)
C
(d) A
B X
25. The output ‘Y’ of the ircuit given below is (d)
[HCU PhD 2021] C
A
27. For the logic circuit shown in figure, the required
input condition (A, B, C) to make the output (X) =
1 is,
A
B
A
U1
B
B XOR U3 X
AND
U2
B C
XNOR
C
(a) AC (b) BC
(c) AB (d) AC (a) 1, 0, 1
26. The equivalent circuit of the logic circuit given (b) 0, 0, 1
below is [HCU PhD 2015]
(c) 1, 1, 1
(d) 0, 1, 1
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28. Consider the digital circuit shown below in which a simplified equivalent circuit is
the input C is always high (1).
A
[NET June 2011] (a) B x
A C
B Z
A
(b) B x
C
C
(high) A
The truth table for the circuit can be written as x
(c) B
A B Z C
0 0
A
0 1 x
1 0 (d) B
C
1 1
The entries in the Z column (vertically) are 31. Which of the following gates can be used as a parity
(a) 1011 (b) 0100 checker ? [NET June 2018]
(c) 1111 (d) 1010 (a) an OR gate
29. The output 0, of the given circuit in cases I and II, (b) a NOR gate
where [NET June 2012] (c) an exclusive OR (XOR) gate
(d) an AND gate
Case-I : A, B = 1; C, D = 0; E, F = 1 and G =
32. In the given digital logic circuit, A and B form the
0 input. The output Y is: [GATE 2006]
Case-II : A, B = 0; C, D = 0; E, F = 0 and G = A
B
1 are respectively
Y
A
B
C (a) Y A (b) Y AB
D
(c) Y A + B (d) Y B
33. Let Y denote the output in the following logical cir-
E F G cuit, [NET June 2019]
(a) 1, 0 (b) 0, 1
A
(c) 0, 0 (d) 1, 1
G1
30. For the logic circuit shown in the figure below B
[NET June 2014]
A G2 Y
C
B
x D
C
If Y AB CD , the gates G1 and G2 must, re-
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spectively, be (a) NOR gate (b) NAND gate
(a) OR and NAND (b) NOR and OR
(c) AND gate (d) XOR gate
(c) AND and NAND (d) NAND and OR
34. Which of the given relations between the Boolean 38. The circuit shown below uses only NAND gates.
variables P and Q is NOT correct ? ( In the nota- [TIFR 2019]
tion used here, P denotes NOT P and Q denotes
NOT Q) [GATE 2003]
(a) PQ + PQ = P (b) PQ = P + Q
C
(c) PQ = P + Q (d) PQ + Q = P
A
35. If the output of the logic circuit shown in the figure B
is 1, the input could be [GATE 2000]
A The final output at C is
B (a) A AND B (b) A OR B
Out
(c) A XOR B (d) A NOR B
C 39. In a digital circuit for three input signals (A, B and
D
C the final output (Y) should be such that for in-
(a) A = 1, B = 1, C = 1, D = 0 puts
(b) A = 1, B = 1, C = 0, D = 0
A B C
(c) A = 1, B = 0, C = 1, D = 1
(d) A = 0, B = 1, C = 1, D = 1 0 0 0
0 0 1
36. Identify the function F generated by the logic net-
work shown [GATE 2007] 0 1 0
Z
Y The output (Y) should be low and for all other
F
cases it should be high. Which of the following
digital circuits will give such output ?
X [TIFR 2016]
(a) F = (X + Y)Z (b) F = Z + Y + YX A
Y
(c) F = ZY Y + X (d) F = XYZ (a) B
C
37. The circuit shown in figure below acts as a
[GATE 1997] A
B
(b)
+5V Y
C
output
A
B
(c)
Inputs Y
C
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43. The output (Y) of the following circuit will be
A [TIFR 2017]
Y
(d) AA BB C C
B
C
40. The circuit shown below uses only NAND gates.
Find the final output? [TIFR 2013] Y
(a) A B C (b) A
A (c) B (d) C
B
44. Which digital logic gate is mimicked by the
(a) A XOR B (b) A AND B following diode and silicon transistor circuit ?
(c) A OR B (d) A NOR B. [TIFR 2017]
41. 20. The minimum number of NAND gates re- +5V
+5V
quired to construct an OR gate is :[GATE 2017] R1
(a) 2 (b) 4 R C1 R C2
(c) 5 (d) 3 Vout
42. The truth table for the given circuit is : A
B R3
J R2
Q
45. The digital electronic circuit below (left side) has
K
some problem and is not performing as intended.
The voltage at each pin as a function of time is
Q
shown in the adjacent figures. [TIFR 2011]
J K Q J K
1 1
0 0 1 0 0 2 4
(a) 0 1 0 (b) 0 1 0
A
5
6 9 8 Y
B
1 0 1 1 0 0
1 1 1 1 1
0
J K Q J K Q
0 0 0 0 0 0
(c) 0 1 1 (d) 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
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The problem in the about circuit may be that value and remains 1 otherwise. A common pump
(a) the Pin 6 is shorted to ground is used to raise water from an underground stor-
(b) the input inverter is shorted age tank to these overhead tanks. Of the follow-
(c) the Pin 8 is clamped to +5 ing circuits, which one will turn on (P = 1) the pump
(d) OR gate is used to instead of AND gat only when at least two of the tanks have water
46. A control circuit needs to be designed to save on level below the set value? [TIFR 2015]
power consumption by an air-conditioning unit A
in a windowless room with a single door. The room S1
is fitted with the following devices:
(a) S2
1. Atemperature sensor T, which is enabled (T =
P
1) whenever the temperature falls below a pre-set
S3
value;
2. A humidity sensor H which is enabled (H = 1)
whenever the humidity falls below a certain pre-
set value;
3. A sensor D on the door, which is triggered (D S1
= 1) whenever the door opens. S2
Which of the following logical circuits will turn the
(b) P
air- conditioning unit off (A = 0) whenever the door S3
is opened or when both temperature and humidity
are below their preset values? [TIFR 2014]
D S1
S2
(a) T A S3
(c) P
H
S1
S2
D
S3
A S1
(b) T
H S2
(d) P
D S3
(c)
T A
48. The circuit shown in the figure function as
H [GATE 2006]
+VCC
D
(d) T A
A B
47. A building has three overhead water tanks, each
(a) an OR gate (b) an AND gate
fitted with a sensor S1 , S2 , S3 which goes to 0 (c) a NOR gate (d) a NAND gate
when the water level in the tank falls below a set
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49. The circuit which corresponds to a one bit com- (c) V > 85 km / hr, P < 2 bar, T> 40°, H < 50%
parator is
(d) V > 85 km / hr, P < 2 bar, T > 40°, H > 50%
[NET June 2017]
51. A control circuit needs to be designed to save
X on power consumption by an air-conditioning
Y X<Y unit A in a windowless room with a single door.
(a) The room is fitted with the following devices:
X=Y
[TIFR 2014]
X>Y
(1) A temperature sensor T, which is enabled (T
= 1) whenever the temperature falls below a
X pre-set value;
X>Y
(2) A humidity sensor H, which is enabled (H =
(b) X=Y 1) whenever the humidity falls below a certain
pre-set value:
Y X<Y
(3) A sensor D on the door, which is triggered
(D = 1) whenever the door opens
X
X<Y Which of the following logical circuits will turn
(c) the air-conditioning unit off (A = 0) whenever
X=Y
the door is opened or when the both tempera-
X>Y
ture and humidity are below their pre-set values
Y ?
X
D
X=Y
(a) T A
(d)
X>Y H
X<Y
Y D
50. Four digital outputs V, P, T and H monitor the (b) T A
speed V, tyre pressure P, temperature T and rela-
H
tive humidity H of a car. These outputs switch from
0 to 1 when the values of the parameters exceed D
85 km/hr, 2 bar, 40oC and 50%, respectively. A A
(c) T
logic circuit that is used to switch ON a lamp at
H
the output E is shown below.[NET June 2013]
D
V T A
(d)
P E H
T
H
Which of the following conditions will switch the
lamp ON
(a) V < 85 km / hr, P < 2 bar, T > 40°, H > 50%
(b) P < 85 km / hr, P < 2 bar, T > 40°, H > 50%
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ANSWER KEY
1. (d) 2. (a) 3. (d)
4. (c) 5. (b) 6. (c)
7. (d) 8. (d) 9. (d)
10. (c) 11. (c) 12. (d)
13. (a) 14. (b) 15. (b)
16. (b) 17. (a) 18. (d)
19. (d) 20. (a) 21. (a)
22. (c) 23. (b) 24. (a)
25. (c) 26. (d) 27. (d)
28. (a) 29. (d) 30. (a)
31. (c) 32. (d) 33. (b)
34. (d) 35. (a) 36. (d)
37. (a) 38. (c) 39. (d)
40. (a) 41. (d) 42. (c)
43. (d) 44. (AND gate)
45. (c) 46. (c) 47. (d)
48. (a) 49. (c) 50. (a)
51. (c)
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CSIR-NET/IIT-JAM/GATE PHYSICS
ELECTRONICS
ASSIGNMENT - Op:Amp-3
1. What is the output (Vout ) if a silicon transistor Q 4. If the input to the circuit is a sine wave of peak
and an ideal op amp are used? amplitude 10V and phase difference of 10°.
Then the output is.
15V
Q Input
1k
Output
5V
Vo u t
15V
(a) A full rectified sine wave
(a) 15V (b) 0.7V (b) A half rectified sine wave
(c) 0.7V (d) 15V (c) Triangular wave
2. In the circuit shown below, the output voltage, V0 (d) Square wave
is
5. Positive feedback in an amplitude circuit will_____
10k 4.414k the gain of amplifier.
(a) Increase (b) Decrease
(c) Not alter (d) None of these
V0
1M 6. The condition which is required to get substained
sint
oscillation is.
1F
(a) Barkhausen criteria (b) | A | 1
(c) Phase should be 0 (d) All of the above
7. If Vi 200mV sin(400t ) ,then V0 is___V.
(a) sin t (b) sin t
4 4
35k
35k
(c) sin t (d) cost 10k
Rf
Rf 35k
10k Rf
3. In the circuit shown, Op-amp are ideal. Then, V0 R1 10k
R2
is R3 V0
Vi ~
15V
V0
1V 8. For the given circuit, value of base current ( I b ) of
2R
15V
the n-p-n transistor will be_______ mA.
R
(a) 1.5V (b) –0.5V
(c) 15V (d) 1V
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10V R2
(b) Potential at P is V0 .
R1
1k
5V (c) Amplitude of V0 is 2V.
Ib
(d) Output voltage V0 is in phase with Vi .
12. For an ideal op-amp circuit, the dc gain and the
1k cut-off frequency respectively are.
1k
Vin
1 F V0
2
9. An op-amp is connected in a circuit with a zener
diode. The value of resistance R in k for ob-
10k
taining a regulated output V0 9V is. 1k
1k
R
(a) 1 and 1KHz (b) 1 and 100Hz
1k
V0 (c) 11 and 1KHz (d) 11 and 100Hz
13. What is the voltage at the output of the following
Vin 12V V Z 4.7V operational amplifier circuit?
10k
10. An ideal Op-Amp is connected in a circuit as
shown. The output voltage, V0 is ____V. 1nA
A
2R
RL
R 99k Vo ut
1k
V0
R
1V
R
2V
R (a) 1V (b) 1mV
3V
(c) 1V (d) 1nV
11. In an ideal op-amp circuit, R1 3k and 14. Consider a 741 operational amplifier circuit where
R2 1k . If Vi 0.5sin t V. Which of the fol- VCC VEE 15V and R 2.2k .
lowing are true?
If VI 2mV , what is the value of V0 with respect
Vi
to ground?
V0
R R R
R –VCC
P
R1 V0
R2 +
VI
– +VEE
(a) 1mV (b) 2mV
(a) The current through R1 The current through (c) 3mV (d) None
R2 . 15. Analyse the ideal op-amp circuit in the figure.
Which one of the following statements is/are true
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about the output voltage Vout , when terminal ‘C’ 1
c . The voltage gain and phase of the out-
is connected to point ‘A’ and then to point ‘B’? RC
put voltage relative to the input voltage respec-
R R
tively are
1 1
A (a) and 45° (b) and –45°
Vo ut 2
Vin 2
C 1 1
(c) and –90° (d) and 90°
A
2 2
R B
19. If V1 0.2V , V2 0.8V then find V0 .
(a) Vout Vin and Vout Vin when ‘C’ is con- 10k
nected to ‘A’ and ‘B’ respectively. 1k
(b) Vout Vin and Vout Vin when ‘C’ is con- A
2k
nected to ‘A’ and ‘B’ respectively.
(c) Vout Vin when ‘C’ is connected to either ‘A’ V1
V 2k
V0
2
or ‘B’
(d) Vout Vin when ‘C’ is connected to either ‘A’
or ‘B’
16. In an inverting op-amp, voltage gain is 20dB. 20. For the given circuit, the frequency above which
the gain will decrease by 20dB per decade is
R1 20k , value of feedback resistor R2 will be.
______ KHz.
R2
10k
Vin
R1
Input V0
1000pF
V0
1k
2k
(a) 2M (b) 200k
(c) 20k (d) 2k 21. In order to obtain a solution of the third order dif-
17. For the given circuit, the output voltage V0 is ferential equation, involving voltage V (t ) , an on-
amp circuit would require at least
R R (a) 2 integrators and one adder
Va
R (b) 3 integrators only
Vb (c) 3 differentiators and one adder
(d) 3 integrators and one adder.
R V0
Vc 22. If V0 V1 2V2 3V3 then R1 , R2 and R3 is.
R
Vd
R1 6k
R V 1
R2
–V 2
R3
V 3
V0
(a) Va Vb Vc Vd (b) Va Vb Vc Vd
(c) Va Vb Vc Vd (d) Va Vb Vc Vd
18. A low pass filter is formed by a resistance R and a
capacitance C. At the cut-off angular frequency,
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(a) R1 6k , R2 2k , R3 3k
(b) R1 2k , R2 6k , R3 3k
(c) R1 6k , R2 3k , R3 2k
(d) R1 6k , R2 3k , R3 3k
23. Vi is a sinusoidal input signal of frequency 10Hz
and V0 is output signal. Magnitude of gain is close
to the values
0.01F
10k
1k
Vi
V0
(a) 4 (b) 9
(c) 15 (d) 20
24. In an ideal op-amp, the potential at node A is
25k
5k
A
V0
1V +
–
(a) 1V (b) 0V
(c) 5V (d) 25V
ANSWER KEY
1. (b) 2. (a) 3. (c)
4. (d) 5. (a) 6. (d)
7. (11.03V)
8. (0.1mA)
9. 1.09k
10. (6V) 11. (a,c,d) 12. (c)
13. (b) 14. (d) 15. (a)
16. (b) 17. (c) 18. (b)
19. (c) 20. (15.9kHz )
21. (d) 22. (c) 23. (b)
24. (b)
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CSIR-UGC-NET/IIT-JAM/GATE/TIFR/JEST
ASSIGNMENT - 4 BIPOLAR JUNCTION TRANSISTOR
1. A BJT is said to be operating in the saturation re- ing saturation to cut off switching.
gion if 6. MOSFET can be used as
(a) Both the junctions are reverse biased. (a) current controlled cepacitor.
(b) Base-emitter junction is reverse biased and (b) voltage controlled capacitor.
base-collector function is forward biased. (c) current controlled inductor.
(c) Base-emitter junction is forward biased and (d) voltage controlled inductor.
base-collector function is reverse biased. 7. If for a silicon n-p-n transistor, the base to emitter
(d) Both the functions are forward biased.
2. The early-effect in a BJT is caused by
VBE is 0.7V and the collactor to base voltage
(a) Fast-turn-on VCB is 0.2V , then the transistor is operating in
(b) Fast-turn-off
the
(c) Large collector-base reverse bias
(a) normal active mode.
(d) Large emitter-base forward bias
(b) saturation mode.
3. In a transistor, if it is operating with both of its
(c) inverse active mode.
junctions forward biased, but with the collector
(d) cut-off mode.
base forward bias greater than the emitter base
forward bias, then it is operating in the 8. Consider the following statements S1 and S 2
(a) forward active mode. S1 : of a BJT reduces if the base width is in-
(b) reverse saturation mode.
creased.
(c) reverse active mode.
(d) forward saturation mode. S2 : of a BJT increases if the doping concen-
4. In a bipolar transistor, at room temperture, if the tration in the base is increased. Which one of the
emitter current is doubled, the voltage cross the following is correct?
base-emitter junction (a) S1 is false and S 2 is true.
(a) doubles.
(b) halves. (b) Both S1 and S 2 are true.
(c) increases by about 20mV . (c) Both S1 and S 2 are false.
(d) decreases by about 20mV .
(d) S1 is true and S 2 is false.
5. The phenomenon known as “early effect” in a BJT
refers to a reduction of the effective base width 9. A BJT is biased in forward active mode. Assume
caused by KT
VBE 0.7V , 25 mV and reverse saturation
(a) electron-hole recombination at the base. q
(b) the reverse biasing of the base collector junc-
tion. current I s 1013 mA . The transconductance of
(c) the forward biasing of the emitter base func- BJT (in mA / V ) is_____
tion. 10. A npn BJT having reverse saturation current
(d) the early removal of stored base charge dur-
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I s 1015 A is biased in the forward active re-
Vcc
gion with VBE 700mV . The tnermal voltage
VT is 25mV and the current gain may RL
vary from 50 to 150 due to mancfacturing varia- Rbias
tions. The maximum emitter current (in A ) is___. +
11. A npn BJT is operating in the active region. If the +
reverse bias across the base-collector junction is Vout
increased, then
RE
(a) the effective base width increases and com- – –
mon emitter current gain increases.
(b) the effective base width increases and com-
(a) decrease the voltage gain and decrease the
mon emitter current gain decreases.
input impedance.
(c) the effective base width decreaes and com-
(b) increase the voltage gain and decrease the
mon emitter current gain increases.
input impedance.
(d) the effective base width decreases and com-
(c) decrease the voltage gain and increase the
mon emitter current gain decreases.
input impedance.
12. Which one of the following statements are correct
(d) increase the voltage gain and increase the
for basic transistor amplifier configuration ?
input impededance.
(a) CB amplifiers have low input impedance and
15. Introducing a resistor in the emitter of a common
low curent gain.
emitter amplfier stabilizes the dc operating point
(b) CC amplifiers have law output impedance anda
high current gain. against variations in
(c) CE amplifier has very poor voltage gain but (a) only the temperature.
very high input impedance. (b) only the of the transistor..
(d) The current gain of CB amplifiers is higher than (c) both temperature and .
the current gain of CC amplifiers. (d) None.
13. A transistor having 0.99 and VBE 0.7V is 16. Assume that the transistor is in the active region. It
used in the circuit. The value of the collector cur- has a large and its base-emitter voltage is
rent will be____ (mA).
0.7 V . Value of I C is
+12V
15V
1k
RC
10k
1k IC
10k
5k
430
1k
(a) Indeterminate since RC is not given
14. In the BJT amplifier, mode of operating region is
forward active region. By putting a capacitor (b) 1mA
(c) 5mA
across RE will
(d) 10mA
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17. If the transistor in the figure is in saturation, then
(a) 2V ,2mA (b) 3V , 2mA
C
(c) 4V ,2mA (d) 4V ,1mA
dc denotes
IB dc current gain 21. Assuming VCE , sat 0.2V and 50 , the mini-
mum base current I B required to drive the tran-
B
sistor in the figure to saturation is
3V
E
(a) I c is always equal to dc I B IC
1k
(b) I c is always equal to dc I B IB
(c) I c is greater than or equal to dc I B
(d) I c is less than or equal to dc I B
18. Choose the correct match for input resistance of
various amplifier configurations shown below:
Configuration Input Resistance
(a) 56 A (b) 140 A
CB:Comman Base LO:Low
(c) 60 A (d) 3 A
CC:Common Collector MO:Moderate
22. The cascode amplifier is a multistage configura-
CE:Common Emitter HI :High tion of
(a) CB LO , CC MO, CE HI (a) CC CB (b) CE CB
(b) CB LO , CC HI , CE MO (c) CB CC (d) CE CC
(c) CB MO , CC HI , CE LO 23. The circuit using a BJT with 50 and
(d) CB HI , CC LO, CE MO VBE 0.7V is shown. The base current I B and
19. Generally, the gain of a transistor amplifier falls at collector voltage VC are respectively..
high frequencies due to the
(a) internal capacitances of the device 20V
(b) coupling capacitor at the input +
2k
20. In the amplifier circuit shown, values of R1 and 430k
–
R2 are such that the transistor is operating at
VCE 3V and I c 1.5mA when its is 150. 10F
For a transistor with of 200, the operating point
VCE , IC is_____ 1k
Vcc=6V
R2
R1
(a) 43 A and 11.4V
(b) 40 A and 16V
(c) 45 A and 111V
(d) 50 A and 10V
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24. If DC 60,VBE 0.7V , the capacitance CC (c) collector and emitter respectively are 8V
can be assumed to be infinite and 7.3V
(d) base, emitter and collector respectively are
12V 8V , 7.3V and 5V
1k 27. In the circuit shown, the transistor is biased at
53k
+ 10V
5.3k
CC RL 2.5k
VS V0
40k Si transistor
= 100
–
+ VBE= 0.7 V
Under the DC conditions, the collector to emit- 2.7V
ter voltage drop is –
(a) 4.8V (b) 5.3V
(c) 6V (d) 6.6V (a) 0mA (b) 5mA
25. For the BJT circuit, assume is large and (c) 3.9mA (d)
VBE 0.7V . Mode of operation of BJT is 28. Assertion (A): A self-biased BJT circuit is more
state as compared to a fixed biased one.
Reason (R): A self-biased BJT circuit was more
10k components as compared to a fixed biased one
(a) Both A and R are true
(b) A is true but R is false
(c) A is false but R is true
10V
2V (d) Both A and R are false
1k 29. Consider the following circuit:
5V
(a) Cut-off (b) Saturation 1k
(c) Normal active (d) Reverse active +
26. In the circuit shown, the approximate voltages at 1M
VCE
the transistor
–10V –
2k 2k
4k
What is VCE in the given circuit ?
16k 10
10k (a) V (b) 0V
3
(c) 5V (d) 3V
(a) base and emitter respectively are 8V
30. The transconductance g m of the transistor used
and 7.3V
in the CE amplifier shown in the below circuit,
(b) base and collector respectivley are 8V
operating at the room temperature is
and 5V
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+10V
34. Assume VBE 0.8V and comman base current
3k gain of the transistor is unity..
+18 V
100k
= 100
Vi 4k
44k
3V
(a) 92mA / V (b) 46mA / V
16k
(c) 184mA / V (d) 25mA / V 2k
31. In the circuit shown, the silicon npn transistor Q
has a very high value of . The required value of The value of VCE (in volts) is_____
R2 in k to produce I C 1mA is
35. If VBE 0.7V and VE 0V and DC 99 for
+VCC =3 V
the transistor,then the value of RB is kilo ohms
IC is____ k
R1 =60 k +10V
Q
R2
RE=500
RB
(a) 20 (b) 30
(c) 40 (d) 50
32. In the circuit shown, the PNP transistor has VE = 0 V
VBE 0.7V and 50 . Assume that 1k IE
RB 100k . For V0 5V , value of RC in k –10V
is _____ 36. For the circuit shown, the transistor has
40,VBE 0.7V and the voltage across the
RC
zener diode is 15V . The current (in mA ) through
V0
the zener diode is____
30V
330 100
VEE = 10 V
RB
33. The Ebers-Moll model of a BJT is valid
(a) only in active mode
(b) only in active and saturation modes
(c) only in active and cu-off modes 37. The matched transistors Q1 and Q2 shown in the
(d)in active, saturation and cut-off modes adjoining figure have 100 . Assume the base-
emitter voltage to be 0.7V , the collector-emitter
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voltage V2 of the transistor Q2 is decimal is
VCC = 24 V
+12V +50V
10k 20k 4.7k
+ V0
Q Q Vi
V2 C= 0.1 F = 100
VBC= 0.7 V
–
(a) 33.9V (b) 27.8V
(a) 2.6mA (b) 2.3mA
(c) 16.2V (d) 0.7V
(c) 2.1mA (d) 2mA
38. In the ckt shown, VBE 0.7V . The of the tran- 42. For silicon BJT shown in figure, find RB to estab-
sistor and VCE are respectively lish VCE = 2V assume VBE = 0.7V
10V (a) 283k (b) 107k
200 (c) 200k (d) 242k
4k VCC =12V
+
VCE
RB 5k
– C
6V
530
0.5mA = 50
B
(a) 19 and 2.8V (b) 19 and 4.7V E
(c) 38 and 2.8V (d) 38 and 4.7V
39. The biasing circuit of a silicon transistor is shown
43. The common collector transistor configuration has
below. If 80 , then what is VCE of the transis-
the following property
tor?
(a) High input and low output resistance
VCC=12 V
(b) High input and high output resistance
(c) Low input and low output resistance
RB=100 k
RC=2 k (d)Low input and high output resistance
44. The figure shown below in a common emitter am-
+
plifier. The component_____ us wrongly placed
VCE because____.
– 12V
100k 5k
R1
(a) –6.08V (b) 0.2V V0
(c) 1.2V (d) 6.08V C3
40. If both the functions of a transistor are forward
C1
biased , it will be in
(a) saturation mode (b) active mode 100k R2
C2
(c) cut-off mode (d) inverse active mode 1k
41. A transistor amplifier circuit is shown in the figure.
The quiescent collector current, rounded off to first
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VCC (a) Saturation (b) Active region
45. For the circuit shown, it is given that VCE . (c) Break down region (d) Cut-off region
2
48. If VBE = 0.7V, I C I E and a DC current gain of
The transistor has 29 and VBE = 0.7V when
B – E function is forward biased 100. The value of V0 is
VCC =10V
+10V
4R
C
10k 10k
= 29
B
E
V0
R
10
RB
For this circuit, the value of is
R
(a) 43 (b) 92
(a) 4.65V (b) 5V
(c) 121 (d) 129
(c) 6.3V (d) 7.32V
46. In the given circuit the current gain ' ' of the ideal
49. The transistor is used in the circuit has a of 30
transistor is 10. The operating point of the transis-
and ICB0 is negligible
tor (VCE, IC) is
10k 15k 2.2k
IC
1k
0.5A 40V D
Vz = 5 V
15V
–12V
VBE = 0.7V, VCE(sat) = 0.3V
(a) 40V, 4A (b) 0V, 4A
If the forward voltage drop of diode is 0.7V. Then
(c) 40V, 5A (d) 15V, 4A
the current through collector will be
47. Consider the following circuit shown in the figure.
(a) 168mA (b) 108mA
If the of the transistor is 30 & ICB0 is 20nA and (c) 20.5mA (d) 5.36mA
the input voltage is 5V, then the transistor would 50. The common emitter amplifier shown in the figure
be operating in is biased using a 1mA ideal current source. The
+12V
approximate base current value is
VCC = 5V
2.2k RC = 1k
Vout
15k
Vi
Q
= 100
+
100k Vin 1mA
–
–12V
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(a) 0mA (b) 10mA
(c) 100mA (d) 1000mA +10V
51. Two perfectly material ‘Si’ transistor are connected
as shown. the value of the current I is 1k
+3V
1k I
2.70 k 1k
(a) Saturation region
(b) Cut-off region
(c) Reverse active-region
(d) Forward active region
–5V
55. The transistor in the given circuit should always be
in the active region. Take VCE(sat) = 0.2V,
(a) 0mA (b) 2.3mA VBE = 0.7V. The maximum value of RC in which
(c) 4.3mA (d) 7.3mA can be used is
52. A BJT is used as a power control switch by bias-
ing it in the cut off region (OFF state) or in the
saturation region (ON state). In the On state, for
RC
the BJT
(a) Both base-emitter and Base-collector function RS =2 k
are reverse biased 05V
= 100
(b) The Base-emitter function is reverse biased &
Base-collector function is forward biased 5V
(c) The Base-emitter & Base-Collector function
are forward biased
(d) Both Base-Emitter & Base- Collector func-
tion are forward biased. 56. If 75,VC 9V then the ratio of RB and RC
53. If Vin = 10V. What is the power dissipated in the is____
transistor
+15V
+
RB RC
Vin = 10 V RL = 10 VC
6.6V
– Zener diode
(a) 0.6W (b) 4.2W
(c) 2.4W (d) 5.4W
54. If F 100 , the transistor is operating in
57. A transistor circuit is given below. The Zener di-
ode breakdown voltage is 5.3V. Take VBE = 0.6V,
then value of current gain is____
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+10V +12V
2k
4.7 k 220
V0
h fE = 100
0.5mA 1M 4k
5V
470
What is the output voltage V0 in the above circuit?
(a) 0V (b) 12V
58. A NPN Si transistor is meant for low current au- (c) 9V (d) 5V
dio amplification. Match its following characteris-
tics against their values characteristics
(a) Characteriestics Values
(a) VEB max (P) 0.7V
(b) VCB max (Q) 0.2V ANSWER KEY
(c) VCE sat (R) 6V
(S) 50V 1. (d) 2. (c) 3. (b)
59. In the circuit of figure, value of base current IB will 4. (c) 5. (b) 6. (b)
be 7. (a) 8. (d)
+5V 9. ( g m 5.76 m A / V )
10. 1475 A 11. (c)
5k
12. (a,b) 13. 3.75 mA
= 80 14. (b) 15. (c) 16. (d)
+ 17. (d) 18. (b) 19. (a)
0.7V – 20. (a) 21. (a) 22. (b)
IB
6.3k 23. (b) 24. (c) 25. (b)
RE
26. (a) 27. (c) 28. (a)
–10V 29. (c) 30. (a) 31. (c)
(a) 0mA (b) 18.2mA 32. (1.07k ) 33. (d)
(c) 26.7mA (d) 40mA
34. (6V) 35. ( 93k )
60. In the transistor circuit, collector to ground volt-
36. (41.96mA) 37. (b)
age is +20V. Which of the following is the prob- 38. (a) 39. (b) 40. (a)
able cause of error? 41. (b) 42. (a) 43. (a)
20V
44. Capacitor C is wrongly placed because
it will not isolate dc supply to signal source.
10k So, it should be placed before potential divider
for proper coupling.
47k
+10V
45. (d) 46. (b) 47. (b)
48. (a) 49. (d) 50. (b)
51. (c) 52. (d) 53. (c)
54. (d) 55. ( 22.1 ) 56. (105.13)
(a) Collector emitter terminals shorted
57. 19
(b) Emitter to ground connection open
58. ( A P B R C Q)
(c) 10k resistor open
59. (b) 60. (b) 61. (b)
(d) Collector base terminals shorted
61. Consider the NPN transistor circuit shown be-
low:
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ELECTRONICS: REGISTER
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. A pulses train can be delayed by a finite number
of clocks periods using a
(a) serial in serial out shift register CLK SI 0101
(b) Serial in parallel out shift register
Q D QC Q B Q A
(c) Parallel in serial out shift register
(d) Parallel in parallel out shift register (a) 1001 (b) 0100
(c) 0110 (d) 1010
2. Choose the correct one from among the alterna-
tives a, b, c, d after matching an item from group 4. In the 3-bit register shown below. Q1 Q2 are the
1 with the most appropriate item in group 2.
least and the most significant bits of the outpuit,
respectively,
Group 1 Group 2
P : Shift register 1. Frequency division Q3 Q2 Q1
Q : Counter 2. Addressing in memory Q3 D3 Q2 D 2 Q1 D 1 Din=+ 1
chips
R : Decoder 3. Serial to parallel
data conversion
CLK
(a) P 3, Q 2, R 1
If Q1 , Q2 and Q3 are set to zero initially, then the
(b) P 3, Q 1, R 2 output after the arrival of the second falling clock
(CLK) edge is [NET June 2020]
(c) P 2, Q 1, R 3
(a) 001 (b) 100
(d) P 1, Q 2, R 2
(c) 011 (d) 110
3. The registers QD , QC , QB and QA shown in the 5. The initial contents of the 4 bit serial in serial out,
figure are initially in the state 1010 respectively. right shift, shift register shown in the figure are
An input sequence SI = 0101 is applied. After 0110. After three clock pulses are applied, the
two clock pulses, the state of the shift registers (in contents of the shift register will be
the same sequence QD QC QB QA ) is :
[GATE 2007]
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(a) 0, 0 (b) 0, 1
Clock
Serial in 0 1 1 0 (c) 1, 0 (d) 1, 1
8. What is the value of the register formed from D
flip-flops using Q0 , Q1 and Q2 as output
Q0 , Q1, Q2 after 14 cycles
(a) 0000 (b) 0101
Q0 Q1 Q2
(c) 1010 (d) 1111 D Q D Q D Q
6. The shift register shown in the given figure is ini- Q Q Q
tially loaded with the bit pattern 1010. Subse- Clock
quently the shift register is clocked, and with each
clock pulse th pattern gets shifted by one bit posi- (a) 110 (b) 000
tion to the right with each shift, the bit at the serial
(c) 001 (d) 011
input is pushed to the left most position (MSB).
After how many clock pulses will the content of 9. Consider the shift register
the shift registe become 1010 again? A B
x
Clock
1 0 1 0
2fs
The frequency of signal x is fs the shift register is
clocked at the positive edge of 2fs. The time off-
set between A and B is
(a) 3 (b) 7 1/(2fs) (b) 1/fs
(c) 11 (d) (c) 3/(2fs) (d) 1/(4fs)
7. For the circuit shown, two 4-bit parallel in serial 10. In the schematic figure given below, the initial val-
out shift registers loaded with the data shown are ues of 4 bit shift registers A and B are 1011 and
used to fed the data to full adder, Initially all the 0010 respectively. The values of SOA and SOB
flip-flops are in clear state. After applying two clock after the pulse T2 are respectively.
pulses, the outputs. Sum and carry of the full addr [NET Dec. 2015]
should be___ ___respectively.
Shift Register A Shift Register B
CLOCK CLK SOA SIB CLK SOB
1 0 1 1 D Q A S SHIFT
MSB LSB T0 T1 T2
Shift Register CLOCK
D Q B
Ci Co SHIFT
clk
Q D (a) 1110 and 1001 (b) 1101 and 1001
clk
Clock
(c) 1101 and 1100 (d) 1110 and 1100
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ANSWER KEY
1. (b) 2. (b) 3. (a)
4. (c) 5. (c) 6. (b)
7. (d) 8. (a) 9. (b)
10. (d)
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ELECTRONICS: OP-AMP
CSIR-NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. The circuit of following figure uses an ideal Op-
Amp for small positive values of Vin . The circuit 5k
works as :
1k
+2
V0
+1 +
R 1k
1k
V in
Vo u t
(a) 7V (b) 5 V
(a) an exponential amplifier (c) 5 V (d) 7 V
(b) a half wave rectifier
(c) a logarithmic amplifier 4. An Op-Amp based voltage follower
(d) a differentiator [NET June 2014]
2. Consider the following circuits C-1 and C-2. (a) is useful for converting a low impedance source
into a high impedance source
[TIFR 2018]
(b) in useful for converting a high impedance
+ source into a low impedance source
(c) has infinitely high closed loop output imped-
ance
(d) has infinitely high closed loop gain
C-1
5. The inverting input terminal of an operational am-
plifier (OP-AMP) is shorted with the output ter-
minal apart from being grounded. A voltage signal
+ Vi is applied to the non-inverting input terminal of
the op-amp. Under this configuration, the Op-
C-2
Amp functions as
You can apply the golden rules of an ideal Op- [GATE 2004]
Amp to (a) An open loop inverter
(a) Only C-1 (b) Only C-2 (b) A voltage to current converter.
(c) Both C-1 and C-2 (d) Neither C-1 nor C-2 (c) A voltage follower
3. The output V0 of the ideal Op- Amp circuit shown (d) An oscillator.
in the figure is : [GATE 2005] 6. In an ideal Op-Amp circuit shown below,
R1 3k and R2 1k and Vi 0.5sin t (in
volt). Which of the following statements is (are)
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2
true ? 0.01F
Vi
V0 10k
1k
P Vi
V0
R2 R1 +
The magnitude of the gain and the phase shift, re-
(a) the current through R 1 the current through spectively, are close to the values
R2
(b) the amplitude at of V0 is 2V (a) 5 2 and
2
R2
(c) the amplitude at P is V0
R1 (b) 5 2 and
2
(d) the outuput voltage V0 is in phase with Vi
7. The output of the circuit on the right will be (c) 10 and zero
[GATE 2000]
(d) 10 and
1k
+ 10. In the following circuit, for the output voltage to
Out
1.0V V0 V1 V2 / 2 the ratio R1/ R2 is
100
R
(a) 1V (b) 11V +VCC
(c) -10V (d) 0V R
V1
8. Consider the Op-Amp circuit shown in the figure. V2 V0
+
[NET Dec. 2013] R1
1 F R2 VCC
1k [GATE 2012]
1k
V0
Vi
+ (a) 1/2 (b) 1
If the input is a sinusoidal wave Vi = 5 sin (1000t), (c) 2 (d) 3
then the amplitude of the output V0 is Statement for Linked Answer Q.11 and Q.12
5 Consider the following circuit [GATE 2013]
(a) (b) 5
2
10k
+
(c) 5 2 (d) 5 2 V(in)
V(out)
2 1000pF
1k
9. In the Op-Amp circuit shown in the figure, Vi is a
sinusoidal input signal of frequency 10 Hz and V0 2k
is the output signal. [NET Dec. 2012]
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11. For this circuit the frequency above which the gain 16. Consider a 741 operational amplifier circuit as
will decrease by 20 dB per decade is shown below, where VCC VEE 15V , and
(a) 15.9 kHz (b) 1.2 kHz R 2.2 k . If vi = 2 mV, what is the value of v0
(c) 5.6 kHz (d) 22.5 kHz with respect to the ground ? [JEST 2017]
R
12. At 1.2 kHz the closed loop gain is
(a) 1 (b) 1.5 R R
(c) 3 (d) 0.5 R VCC
v0
13. In the operational amplifier circuit below, the volt-
vi
age at point A is [NET Dec. 2011] VEE
+5V (a) 1 mV (b) 2 mV
1k A
1V (c) 3 mV (d) 4 mV
1V +
1k 17. In one of the following circuits, negative feedback
5V
1k does not operate for a negative input. Which one
is it ? The Op-Amps are running from 15V sup-
plies.
(a) 1.0 V (b) 0.5 V 5.1V
(c) 0 V (d) -5.0 V
14. In the op-amp circuit shown in the figure below,
(a) + (b) +
the input voltage Vi is 1V. The value of the output
V0 is : [NET June 2012]
1k
1k
1k V0 (c) + (d) +
V1 1V
+
1k
18. Analyse the ideal Op-Amp circuit in the figure.
Which one of the following statements is true about
(a) 0.33 V (b) 0.50 V the output voltage Vout , when terminal C is con-
(c) 1.00 V (d) 0.25 V nected to point A and then to point B ?
15. In the following circuit, the resistance R2 is doubled. [JEST 2019]
[TIFR 2014]
R R
Vin
+
Vo u t Vo u t
R1 R2
A R B
It follows that the current through R2.
(a) Vout Vin and Vout Vin when C is con-
(a) remains the same (b) is halved
(c) is doubled (d) is quadrupled. nected to A and B, respectively
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(b) Vout Vin and Vout Vin when C is con- 50k , which of the following statements is true ?
nected to A and B, respectively 1M
(c) Vout Vin when C is connected to either A or R
10k
B
(d) Vout Vin when C is connected to either A or
+A r
+A V0
1
2
B
19. Which one of the following graphs represents the [NET Dec. 2014]
correct variations of v0 with vi ? Here vd is the (a) A1 is required in the circuit because the source
impedance is much greater than r
voltage drop across the diode and the Op-Amp is
(b) A1 is required in the circuit because the source
assumed to be ideal.
impedance is much less than R
vin vd (c) A1 can be eliminated from the circuit without
vout affecting the overall gain
RL (d) A1 is required in the circuit if the output has to
follow the phase of the input signal
21. In an ideal Op-Amp depicted below, the potential
vout
at node A is
25k
1k A +12
(a) vin 5V
0 1V
-12
vout
(a) 1 V
(b) 0 V
(c) 5 V
(b) vin
0 vd (d) 25 V
22. For an ideal Op-Amp circuit given below, the DC
vout
gain and the cut off frequency, respectively are
1k
(d) vin
0 vd
1
vd F
2
vout 10 k
1k
(d) vin
0
(a) 1 and 1 kHz
20. Consider the amplifier circuit comprising of the two (b) 1 and 100 Hz
op-amps A1 and A2 as shown in the figure (c) 11 and 1 kHz
If the input ac signal source has an impedance of (d) 11 and 100 Hz
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23. In the generalized operational amplifier circuit (a) R 1 10 k; R 2 1.3k
shown on the right, the amp. has a very high input
(b) R1 30 k; R 2 1.3k
impedance Z 50M and an open gain of
1000 for the frequency range under consideration. (c) R1 10 k; R 2 1.7 k
Assuming that the op-amp. draws negligible cur-
(d) R1 30 k; R 2 1.7 k
rent, the voltage ratio V2 V1 is approximately
[TIFR 2016] Statement for Linked Answer Q.26 and Q.27
The following circuit contains three operational
amplifiers and resistors. [GATE 2008]
R
500k R
5k
3R
+ Va R
3R
3R V01
Vb
V1
Z V2 Vc R
3R R V02
Va
R
Vb
R
(a) 190 (b) 190 Vc
(c) 90 (d) 80 R
24. In the circuit, find the output voltage V0
26. The output voltage at the end of second opera-
tional amplifier V01 is :
I in
(a) V01 3 Va Vb + Vc
RS RA
1
V0 (b) V01 Va Vb + Vc
RB 3
1
(c) V01 Va Vb + Vc
3
RA RA
(a) R I in RS (b) I in RS 1 R 4
B B (d) V01 Va Vb + Vc
3
RA RB 27. The output V02 (at the end of third OP-AMP) of
(c) R I in RS (d) I in RS 1 R
B A the above circuit is :
25. The low-pass active filter shown in the figure has (a) V02 2 Va Vb + Vc
a cut-off frequency of 2KHz and a pass band
gain of 1.5. The values of the resistors are (b) V02 3 Va Vb + Vc
[GATE 2006] 1
(c) V02 Va Vb + Vc
2
15k (d) Zero
R1
Vout Statement for Linked Q.28 and Q.29
+ Shown in the figure is a circuit to measure light
R2
Vin 0.047
F intensity and convert it to a digital signal. The pho-
todiode P has a responsivity of 0.1A per watt of
incident light intensity. The OP-AMP converts the
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6
induced photocurrent to a voltage which is digi- 31. The input given to be an ideal OP-AMP integra-
tized by the 10-bit A/D converter with a refer- tor circuit is [GATE 2014]
ence voltage of 4V. [GATE 2010] V
1M VRef 4V V0
10 bit A/D t
+
t0
The correct output of the integrator circuit is (in
magnitude form)
28. For a light intensity of 25 W incident on the pho- V
todiode, the voltage output of the OP-AMP is :
(a) V0
(a) 0.25 V (b) 1.0 V
(c) 4.0 V (d) 2.5 V t
t0
29. The range of light intensity which can be measured V
by this set up is :
(b) V0
(a) 100 mW to 100 W
(b) 100 nW to 100 W t0
t
(c) 40 mW to 40 W V
(d) 40 nW to 40 W
(c) V0
30. In the circuit shown below, the gain of the Op-
t
Amp in the middle of its bandwidth is 105 . A sinu- t0
soidal voltage with angular frequency V
100 rad / s is applied to the input of the
Op-Amp. (d) V0
t
R2 = 4k t0
32. If the parameters y and x are related by
C = F
Rf
y log x than the circuit that can be used to
Vin
Vout produce an output voltage V0 varying linearly with
R1 = 2k
x is [NET- DEC- 2015]
The phase difference between the input and the
output voltage is [NET-June 2020] y
V0
5 3 (a)
(a) (b)
4 4
(c) (d)
2
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Vout
(b) (0,0) t
y t
t/2
V0
(b)
Vout t/2 t
(c) (0,0) t
y
V0
(c)
Vout t/2 t
y
V0 (d) (0,0) t
(d)
33. The input Vi to the following circuit is a square 34. For the OP-AMP circuit shown in the figure be-
wave as shown in the following figure: low, which is the correct output waveform?
Which of the waveforms V0 best describes the
output ? [NET June 2018] [NET Dec. 2010]
Vin t/2 t
Vin
(0,0) t 1V
C 33k
Vin
Vout
+ 1k +5V
Vin V0
+ 5V
Vout t/2 t
V0
(a) (0,0) t
(a) 1V
t
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8
V0 0.5V
(b) 1V 0V
t (c)
–1V
V0 1V
(c) 1V t 0V
(d)
V0 –1V
36. In the following operational amplifier circuit
(d) 1V
t Cin 10 nF, Rin 20kΩ, RF 200kΩ
and C F = 100 pF .
35. A sinusoidal signal of amplitude 1V is input to the
following operational amplifier circuit, where the The magnitude of the gain at an input signal fre-
diode is an ideal one. what is the outpt ? quency of 16 kHz is [NET June 2017]
[HCU PhD 2014]
RF
2k CF
1k
Ri Ci
2k Vin
Vin Vout
Vout +
(a) 67 (b) 0.15
(c) 0.3 (d) 3.5
1V
37. Consider the following circuit : [TIFR 2012]
0V R
(a)
–0.5V C
Vin
Vout
+
1V
0V If the waveform given below is fed in at Vin
(b)
–0.3V
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(a) 1V (b) 1mV
Vin (c) 1V (d) 1nV
+VP 39. The voltage gain Av , for the Op-Amp circuit
shown beow, is [HCU PhD 2018]
VP R1
R1
then the waveform at the output Vout will be
vi v0
Vout
R
C
(a)
(a) Av 1 jCR
Vout
1
(b) Av
1 jCR
(b) 1 jCR
(c) Av
1 jCR
Vout 1 jCR
(d) Av
1 jCR
(c) 40. Consider the circuit shown in the figure, where RC
= 1. For an input signal Vi shown below, choose
the correct V0 from the options : [GATE-2015]
Vout
R
(d) C
vi
+ V0
38. What is the voltage at the output of the following R
operational amplifier circuit. [ See in the figure] ?
[JEST 2015]
10M vi
1nA
1
RL Vout
99k t
1k 1 2 3
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V0 42. In the circuit given below, the thermistor has a re-
sistance 3k at 25o C . Its resistance decreases
1 by 150 per °C upon heating. The output volt-
(a) age of the circuit at 30oC is [NET June 2015]
T
t
1 2 3
1k
1 1V
+ Vout
V0
1 (a) 3.75V (b) 2.25V
(b) (c) 2.25V (d) 3.75V
t
1 2 3
1
43. The gain of the circuit given below is .
1 RC
V0 C
0.1
R V
(c) Vin
Vout
1 2 3
t V + b a
0.1 Ground
The modification in the circuit required to intro-
V0
duce a dc feedback is to add a resistor
1 [NET June 2017]
(d)
(a) between a and b
t (b) between positive terminal of the op-amp and
1 2 3 ground
(c) in series with C
41. The input voltage (Vin) to the circuit shown in the (d) parallel to C
figure is 2cos(100t)V . The output voltage (Vout) 44. In the circuit below, the input voltage
Vi is 2V, VCC 16V, R2 2 kΩ
is 2cos 100t V . If R 1k , the value of
2
and RL 10 kΩ .
C in F is, VCC
R
+
+12
R Vin +
Vin Vout R1 RL
R2
R
–12
C
The value of R1 required to deliver 10 mW of
power across RL is [NET Dec. 2016]
(a) 0.1 (b) 1 (a) 12 kΩ (b) 4 kΩ
(c) 10 (d) 100
(c) 8kΩ (d) 14 kΩ
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+5V
Vin
45. The I-V characteristics of the diode D in the cir- +1V
cuit below is given by 0V t
(a)
I IS e qV
k BT
1
10V
Vout
t
Where IS is the reverse saturation current V, is the
10V
voltage across the diode and T is the absolute tem-
+5V
perature Vin
+1V
0V t
D
(b)
10V
R Vout
Vin t
Vout
10V
+5V
Vin
+1V
If the input voltage is Vin, then the output voltage 0V t
Vout is [NET June 2020] (c)
10V
qVin
(a) I S R ln K T 1 Vout
B t
10V
1 q Vin I S R
(b) q K BT ln K BT
+5V
Vin
+1V
1 Vin 0V t
(c) q K BT ln I R 1 (d)
S
10V
Vout
1 Vin
(d) q K BT ln I R 1 t
S 10V
47. In the circuit shown below, the OP-AMP is pow-
46. Consider the following OP-AMP circuit. ered by a bipolar supply of 10 V .
[GATE 2012] [TIFR 2015]
+10V + Vout
Vin +
V = 5 sin(2t)
+5V
Vout
4k
1k 10V
5k
Which one of the following correctly represents
the output V out corresponding to the input Vin?
Which one of the following graphs represents Vout
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12
correctly ?
10 (a)
5
V
(a) out 0
-5
-10
0 1 2 3 4 5 (b)
10
5
V (c)
(b) out 0
-5
-10
0 1 2 3 4 5
(d)
10
5
Vout 0 49. Consider the following circuit [GATE 2011]
(c) -5 1k 4k
-10 +10V
0 1 2 3 4 5
+
Vin Vout
10
10V
5
Which of the following represents the output Vout
Vout 0
(d) corresponding to the input Vin?
-5
+5V
-10
0 1 2 3 4 5 2V
Vin
2V Time
48. The following circuit is fed with an input sine wave 5V
of frequency 50 Hz.
(a) 10V
10 pF
Vout
10 k Time
10 k 10V
Vin Vout
+ +5V
2V
Vin
2V Time
Which of the following graphs (solid line is input 5V
and dashed line is output) best represent the cor-
rect situation? (b) 10V
Vout
Time
10V
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+5V 51. In this circuits, the relation between Vi and V0 is
2V IC
Vin
2V Time
5V I1 RS
(c) V0
10V
Vi
Vout
Time
10V Vi
V0
+5V (a) V V e VT (b) V0 VT ln R I
0 i S S
2V
Vin (c) V0 Vi I C RS (d) None of these
2V Time
52. An input of 1.0 V DC is given to the ideal Op-
5V
(d) Amp circuit depicted below. What will be the out-
10V put voltage ? [TIFR 2013]
L=1mH
Vout C=1F
Time R=90k
10V R=10k
50. Consider the circuit shown on the right, which in- Op-Amp
volves an op-amp and two resistors, with an input + Vout
Vin
voltage marked INPUT. [TIFR 2018]
(a) 10.0 V (b) -9.0 V
(c) 0 V (d) 1.0 V
53. Consider the following
Cf
INPUT
+
Rf
Iin Vout
Which of the following circuit components, when
connected across the input terminals, is most likely
to create a problem in the normal operation of the It is given that C f 100 pF , and I in 50nA ,
circuit ?
(a) A voltage source with a very high Thevenin D.C Vout 1V D.C. Therefore, the bandwidth of
resistance. the above circuit is [TIFR-2019]
(b) A current source with a very high Norton (a) 15.8Hz (b) 79.6Hz
resitstance. (b) 145.3Hz (d) 200.4Hz
(c) A voltage source with a very low Thevenin re- 54. For the circuit and the input sinusodial waveform
sistance. shown in the figures below, which is the correct
(d) A current source with a very low Norton waveform at the output? [NET June 2015]
resitstance.
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5k
55. A signal Vin t 5sin (100 t ) is sent to both the
+
10k circuits sketched below : [TIFR 2018]
1k
Vi +
V0
+A
Vin ( t )
1k
10F
Vdc 1
2 1k
0.10
+
0.05
Vin ( t )
1k 10F
1k
Vdc2
t
Vi
0.00
-0.05
-0.10 In the DC output voltage of the top circuit has a
(The time scales in all the plots are the same). value Vdc1 and the bottom circuit has a value Vdc2
, then which of the following statements about the
1.00
relative value of Vdc1 and Vdc2 is correct ?
0.50
(a) Vdc1 Vdc2
0.00 t
Vi
(a) (b) Vdc1 < Vdc2
-0.50
-1.00 (c) Vdc1 = Vdc2
1.00
(d) It will depend on the slew rate of the op-amp.
0.50
(b) t 56. The Classic three Op-Amp instrumentation am-
V0
0.00
plifier configuration is shown below
-0.50
-1.00
V2
R
1.00
R
0.50
R R V0
(c) t
V0
0.00
R
R R
-0.50
V1
-1.00
1.00 The Op-Amp are ideal and all resistors are of
0.50 equal value R. The gain, defined as the output volt-
(d) t age V0 divided by the differential input voltage
V0
0.00
-0.50 V1 V2 , is equal to [JEST 2012]
-1.00 (a) 2 (b) 3
(c) 4 (d) 6
57. A bistable multivibrator with a saturation voltage
5V is shown in the diagram. The positive and
negative threshold at the inverting terminal for
which the multivibrator will switch to the other state
are [GATE 2003]
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15
2M
o V
R1
+ RL
R2
0.01F 2M
200k
(a) 5 / 11V (b) 10 / 11V
4. For an ideal Op-Amp circuit shown below,
(c) 5V (d) 11V 4k
NAT 2k
+10V
V1
V0
1. The output voltage V0 of the Op-Amp circuit V2
5k +
10V RL
given below is ___________
If V1= 1V and V2 = 2V, the value of V0 is
2R _______ V (up to one decimal place ).
5. For an operational amplifier (ideal) circuit shown
R below. [GATE 2018]
V0 4k
R
1V
2V R 2k +10V
R V1
3V V0
V2
5k –10V RL
2. Consider an ideal Op-Amp as shown in the figure
below with
If V1 1V and V2 2V , the value of V0 is
R 1 5 k, R 2 1k, R L 100 k. . For an ______ V (Up to one decimal place).
applied input voltage V = 10 mV, the current pass- 6. For the input voltage Vi = (200 mV)sin(400t), the
ing through R2 is ______ μA . (up to two decimal amplitude of the output voltage (V0) of thegive Op-
places). Amp circuit is _______ V (Round of to 2 decimal
places) [GATE 2019]
+
35k 35k 35k
R1
R1 Rf Rf Rf
V RL R2 R3
10k V0
R2 10k 10k
Vi
3. Consier an ideal operational amplifier as shown in
the figure below with R1 5k , R2 1k , 7. Analyse the Op-Amp circuit shown in the figure
below. What is the output voltage V0 in milli-
RL 100k / For an applied input voltage
V 10mV , the current passing through R2 is volts if V1 2.5V and V2 2.25V [JEST 2020]
_____ . (Upto two decimal places) [GATE 2017]
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16
+10V
V1
5k
5k
–10V
5k +10V
5 V0
5k –10V
+10V 5k
5k
V2
–10V
ANSWER KEY
1. (c) 2. (a) 3. (a)
4. (b) 5. (c) 6. (a, b, d)
7. (a) 8. (c) 9. (b)
10. (d) 11. (a) 12. (b)
13. (a) 14. (c) 15. (a)
16. (*) 17. (c) 18. (c)
19. (a) 20. (b) 21. (a)
22. (a) 23. (c) 24. (b)
25. (d) 26. (c) 27. (d)
28. (d) 29. (d) 30. (a)
31. (a) 32. (c) 33. (b)
34. (a) 35. (b) 36. (d)
37. (a) 38. (a) 39. (d)
40. (b) 41. (c) 42. (c)
43. (d) 44. (c) 45. (None)
46. (a) 47. (d) 48. (a)
49. (a) 50. (c) 51. (d)
52. (c) 53. (b) 54. (b)
55. (b) 56. (b) 57. (a)
NAT
1. (0) 2. (10) 3. (1)
4. (-3.6) 5. (-3.6)
6. (0.044 to 0.046) 7. (5250)
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1
DIGITAL ELECTRONICS
CSIR-NET-JRF/GATE/TIFR/JEST
ASSIGNMENT-3
1. In the digital circuit shown in the figure below, the
A
output ‘ Y ’ is found to be logical ‘1’ when input A 1
B 2 F
is at logic ‘0’. Values of input B and C are
A (a) A B (b) A B
B (c) A B (d) A.B
C 4. Consider the following Boolean expression for the
Y certain output ‘Y’ of these input variables A, B,
A
and C.
B 1. Y ABC ABC ABC ABC
C 2. Y AB A B C
3. Y AB BC AC
(a) B 1, C 0 (b) B 1, C 1
4. Y AB BC AC
(c) B 0, C 0 or 1 (d) None Which of these above expression satisfied the con-
2. In the logical circuit, Y2 Y1 Y0 will be the i’s comple- dition that - “Output will be HIGH when at least
two inputs are High”
ment of X 2 X 1 X 0 if (a) 1 and 2 (b) only 1
(c) 1, 2 and 3 (d) 2 and 4
5. The logical circuit given in the figure is to be used
X0 to implement of the function,
Y0
Z f X ,Y X Y
I1 I2
X1
Y1
X Z
X2
Y2
Control Signal (P)
What values should be selected for I1 and I 2
for output Z X Y ?
(a) P 1 (b) P 0
(a) I1 0, I 2 Y (b) I1 X , I 2 Y
(c) P X 0 X 1 X 2 (d) P X0 X1 X 2
(c) I1 Y , I 2 1 (d) I1 1, I 2 Y
3. The output F is
6. Which one of the follwoing digital circuits repre-
sents the logic of EX-OR operation?
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2
A
A
B
B
Y
Y
(a)
A
B
A
(b) Y (a) 0 (b) 1
B
(c) AB AB (d) AB . AB
A
(c) Y 10. Minimum number of NAND gates required to
B
implement the Boolean function A AB ABC
A
is equal to
B
(a) 0 (b) 1
Y
(c) 4 (d) 7
(d) 11. The circuit shown below is functionally equivalent
to which one of the following?
A
7. Consider the following gate network.
1
W B
F
A
X 2 4 F
5 B
Y 3 (a) NOR gate (b) OR gate
Z
Which one of the following gates is redundant? (c) EX-OR gate (d) NAND gate
(a) Gate No.1 (b) Gate No.2 12. For the logic circuit given below, what is the sim-
(c) Gate No.3 (d) GateNo. 5 plified Boolean function?
8. Match List I with List II and select the correct
code: A
B X
List I List II
Boolean complement-
A. AND gate 1.
ation C
B. OR gate 2. Boolean addition
(a) X = AB + C (b) X = BC + A
Boolean multiplica- (c) X = AB + AC (d) X = AC + B
C. NOT gate 3.
tion
13. The Boolean expression X P, Q, R 0,5 is
Codes:- to be realised using only two 2 input gates. Which
A B C are these gates?
(a) 3 1 2 (a) AND and OR (b) NAND and OR
(b) 1 2 3 (c) AND and XOR (d) OR and XOR
(c) 3 2 1 14. For the logic circuit shown in the below figure,
(d) 1 3 2 what is the required input condtion (A, B, C) to
9. Find the output Y make output X = 1?
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3
A
(d) an EX-OR or an EX-NOR gate
B 19. Y f A, B M 0,1, 2,3, represents
(a) NOR gate
C X (b) NAND gate
(c) OR gate
(d) a situation where output is independent of in-
(a) 1, 0, 1 (b) 0, 0, 1
put
(c) 1, 1, 1 (d) 0, 1, 1
15. Which of the follwoing logical operations is per- 20. FE36 16 XOR CB1516 is equal to
formed by the digital cricuit shown below? (a) 3320 16 (b) FF 3516
A (c) FF 50 16 (d) 3520 16
21. Which one of the following represents coincidence
logic?
A
B
B
F
(a) NOR (b) NAND (a)
(c) EX-OR (d) OR
16. Find output F.
A
A
B
B
C F
F
(b)
D
E
A
(a) A B C DE (b) A B C D E B
(c) AB C DE (d) AB C D E
F
17. Match list I with list II
(c)
List I List II
A. A B 0 1. A B A
B. A B 0 2. A B B
C. A.B.B 0 3. A 1 or B 1 F
D. A B 1 4. A 1 or B 0 (d)
Codes:
A B C D 22. Which one of the following circuits is the minimized
(a) 3 2 1 4 logic circuit for the circuit shown in the figure be-
(b) 2 3 4 1 low?
(c) 3 2 4 1 A
(d) 2 3 1 4
18. The output of a logic gate is ‘1’ when all its inputs B
are at logic ‘0’, then the gate is either
(a) a NAND or NOR gate C
(b) an AND or an EX-NOR gate
(c) an OR or a NAND gate
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A 29. The Boolean function can be expressed in the
(a) B cannonical SOP (Sum of Products) and POS
C
(Product of Sums) form. For the function,
A
(b) B Y A BC , which are such two forms?
C
(a) Y 1, 2, 6,7 and Y 0, 2, 4
A
(c) B
C
(b) Y 1, 4,5,6,7 and Y 0, 2,3
A (c) Y 1, 2,5,6,7 and Y 0,1,3
(d) B
(d) Y 1, 2, 4,5,6, 7 and Y 0, 2,3, 4
C
23. The circuit shown in the figure realizes the function
30. What does the Boolean expression
A AD ABCD ACD AB ACD AB ,
B
C on minimization results into ?
D
(a) A D (b) AD A
E (c) AD (d) A D
31. If A and B are Boolean variables, then what is
(a) A B C DE (b) A B C DE
A B . A B equal to?
(c) A B C DE (d) A B C DE
(a) B (b) A
24. The minterms for AB + ACD are (c) A B (d) AB
(a) ABCD ABCD ABCD ABCD ABCD 32. Consider the Boolean expression,
(b) ABCD ABCD ABCD ABCD ABCD X ABCD ABCD ABCD ACBD
The simplified form of X is
(c) ABCD ABCD ABCD ABCD ABCD
(a) C D (b) BC
(d) ABCD ABCD ABCD ABCD ABCD (c) CD (d) BA
25.
X A B B C B can be simplified to 33. The Boolean expression
(a) X AB (b) X AB A B A C B C simpliyfies to
(c) X AB (d) X AB (a) A B C (b) A B C
26. Simplified form of the logic expression
(c) A B C (d) A B C
A B C A B C A B C is
34. Find X
(a) AB C (b) A BC
(c) A (d) AB C A
27. Boolean expression B X
A B C A B C A B C ABC
reduces to
C
(a) A (b) B
(c) C (d) A + B + C (a) X AB C (b) X BC A
28. The logic function F x. y x . y is same as (c) X AB AC (d) X AC B
35. Find X
(a) f x y x y
A
(b) x y x y B
C
X
(c) f x. y x . y
D
(a) ABCD (b) A B C D
(d) None of these
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(c) A B C D (d) ABCD with its inputs inverted.
(3) A NAND gate is equivalent to an OR gate
36. Reduce F X X XY Z X Y Z with its output inverted.
(a) X XY (b) X Y Z (4) A NOR gate is equivalent to an AND gate
with its output inverted.
(c) X Y Z (d) X Z
Which of these statements are correct?
37. Reduce F AB D CD B A ACD (a) 1 and 2 (b) 2 and 3
(a) AB (b) B (c) 3 and 4 (d) 1 and 4
(c) A (d) C
38. Reduce F AB CD EF AB CD
(a) A B C D E F
(b) AB C D E F ANSWER KEY-2
1. (c) 2. (b) 3. (b)
(c) AB C D E F 4. (c) 5. (d) 6. (b)
7. (b) 8. (c) 9. (b)
(d) AB C D E F
10. (a) 11. (c) 12. (b)
39. How is inversion achieved using Ex-OR gate? 13. (d) 14. (d) 15. (c)
(a) Giving input signal to the lines of the gate 16. (a) 17. (b) 18. (a)
tied together.
19. (d) 20. (d) 21. (a)
(b) Giving input to one input line and logic zero
to the other line. 22. (b) 23. (a) 24. (b)
(c) Giving input to one input line and logic one 25. (c) 26. (b) 27. (b)
to the other line. 28. (b) 29. (b) 30. (d)
(d) Inversion can not be achieved using Ex-OR 31. (b) 32. (c) 33. (c)
gate. 34. (b) 35. (c) 36. (d)
37. (b) 38. (b) 39. (c)
40. Reduced form of BC AD AB CD is
40. (d) 41. (d) 42. (a)
(a) A (b) B
(c) C (d) 0
41. The logic circuit shown in the given figure can be
minimized to
X
Y
(a) X
X
(b)
Y
X
(c)
Y
(d) X
42. Consider the following statements:
(1) A NAND gate is equivalent to an OR gate
with its inputs inverted.
(2) A NOR gate is equivalent to an AND gate
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DIGITAL ELECTRONICS
CSIR-NET-JRF/TIFR/JEST/GATE
ASSIGNMENT -1
1. A logic circuit implements the Boolean function (d) Complement of the function.
F X Y X Y Z . It us found that the imput 6. The product of all the max-terms of a given Bool-
ean function is equal to
combination X Y 1 can never occur. Taking
(a) Two
this into account, a simplified expression for F is
(b) Complement of the function
given by.
(c) One
(a) X Y Z (b) X Z (d) Zero
(c) X Z (d) Y X Z 7. What is the minimized expression of
2. The product of sum expression of a Boolean func- F XZ Y Z YZ XYZ
tion F (A, B, C) of three variables is given by
(a) XY Z (b) XYZ Z
F ( A, B, C ) ( A B C ) ( A B C )
(c) XY Z (d) Z XY
( A B C ) ( A B C ) 8. What Boolean function does the following circuit
The canonical sum of products expression of represent?
F ( A, B , C ) is given by B D
(a) ABC ABC ABC ABC
A C E
(b) ABC ABC ABC ABC
(c) ABC ABC ABC ABC
F
(d) ABC ABC ABC ABC
(a) A[ F ( B C ) ( D E )]
3. The Boolean function
(b) A BC DE F
f ( w, x, y, z ) m(5, 7,9,11,13,15) is indepen-
(c) A( B C ) A( D E ) F
dent of variables.
(d) None of these
(a) w (b) x
9. The complement of the function
(c) y (d) z and x
F ( A B )(C D )( B C ) is.
4. Let f ( A, B ) A B , simplified expression for
(a) AB CD BC (b) AB CD BC
function f ( f ( x y , y ), z ) is.
(c) AB CD BC (d) AB BC CD
(a) x y z (b) xyz
10. The Boolean expression
(c) xy z (d) 1
5. The sum of all the minterms of a given Boolean (a b c d ) (b c )
function is equal to (a) 1 (b) a b
(a) 0
(b) 1 (c) a b (d) 0
(c) 0 or 1 11. Consider the following sum of products expres-
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sion F ABC ABC ABC ABC ABC (c) AB BC A C (d) AB BC
The equivalent product of sums expression is. 16. Find Y.
(a) F ( A B C )( A B C )( A B C )
A
(b) F ( A B C )( A B C )( A B C ) B
(c) F ( A B C )( A B C )( A B C )
(d) F ( A B C )( A B C )( A B C )
Y
12. A universal logic gate can implement any Boolean
function by connecting sufficient number of them
appropriately. Three gates are shown. C
X X (a) A B C (b) A
Y F1 X Y F2 X Y (c) B (d) 0
Y
17. The number of product terms is the minimized sum
X of product expression obtained through the fol-
F3 XY
lowing k map is (d denotes don’t care)
Y
(a) 2 (b) 3
Which one is true? (c) 4 (d) 5
(a) Gate 1 is a universal gate.
(b) Gate 2 is a universal gate. 1 0 0 1
(c) Gate 3 is a universal gate. 0 d 0 0
(d) None of these shown is a universal gate.
0 0 d 1
13. If X 1 in the logic equation,
1 0 0 1
[ X Z {Y ( Z XY )}]{ X Z ( X Y )} 1 ,
then. 18. Find M 1 .
(a) Y Z (b) Y Z
P
(c) Z 1 (d) Z 0
Q
14. Output of a logic gate is ‘1’ when all its inputs are
at logic ‘o’. The gate is either
M1
(a) A NAND or an EXOR gate.
(b) A NOR or an EXNOR gate.
(c) An OR or an EXNOR gate. R
(d) An AND or an EXOR gate.
15. Find Y. (a) M 1 ( P OR Q) XOR R
(b) M 1 ( P AND Q ) XOR R
(c) M 1 ( P NOR Q ) XOR R
(d) M 1 ( P XOR Q) XOR R
A
19. For the output F to be 1, the input combination
must be.
B Y
(a) ABC (b) A B C
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(a) NOR, OR (b) OR, NAND
A
(c) NAND, OR (d) AND, NAND
B 23. Output Y is.
X
Y
F
(a) 1 (b) 0
C
(c) X (d) X
(a) A 1, B 1, C 0 24. Output Y is.
(b) A 1, B 0, C 0 A
Y
(c) A 0, B 1, C 0
(d) A 0, B 0, C 1
20. Find F. (a) 0 (b) 1
(c) A (d) A
X
25. The logic evaluated by the circuit at the output is.
Y
X
F
Output
Y
(a) F XYZ XYZ (b) F XYZ XYZ
(c) F XYZ XYZ (d) F XYZ XYZ (a) XY YX (b) ( X Y ) XY
21. In the figure, if C 0 , the Y is. (c) XY XY (d) XY XY X Y
26. Output Y is.
C
X
A
B Y Y
A
B
Z
(a) Y AB AB (b) Y A B
(c) Y A B (d) Y AB (a) XY YZ (b) XY YZ
22. In the figure, Y AB CD . The gates a1 and (c) XY YZ (d) XZ Y
27. For the logic circuit shown, write the truth table of
a2 must be. X, Y and Z.
A a1
B
a2 Y
C
D
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X
C
B Y
28. Output Y is.
A
Z
B C
(a) A B C (b) A( B C )
(c) B (C A) (d) C ( A B )
ANSWER KEY
1. (d) 2. (b) 3. (c)
4. (a) 5. (b) 6. (d)
7. (d) 8. (a) 9. (a)
10. (d) 11. (a) 12. (c)
13. (d) 14. (b) 15. (a, b, c, d)
16. (d) 17. (a) 18. (d)
19. (a, b, c) 20. (a) 21. (a)
22. (b) 23. (a) 24. (a)
25. (a) 26. (b)
27. X AC 28. (c)
Y A B
Z AC A B
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ELECTRONICS
BOOLEAN AND NUMBER SYSTEM
PREVIOUS YEARS’ QUESTIONS
1. In Boolean terms, (A + B) (A + C) is equal to (c) 8,3 (d) 8,5
[TIFR 2018] 7. The following Boolean expression
(a) ABC (b) ( A + B + C) (A + B)
Y A B C D A B C D A B C D
(c) A (B + C) (d) A + BC
A B C D A B C D A B C D
2. The solution of the Boolean equation
can be simplified to [GATE 2011]
Y A B AB is (a) A B C A D (b) A B C A D
(a) 1 (b) AB
(c) A B C A D (d) A B C A D
(c) AB (d) A B
3. The logic expression 8. Which statement below best describes a Karnaugh
map?
ABC ABC ABC ABC can be simplified to
(a) A Karnaugh map can be used to replace
[GATE 2018]
Boolean rules
(a) A XOR C (b) A AND C (b) The Karnaugh map eliminates the need for
(c) 0 (d) 1 using NAND and NOR gates
4. Which one of the following is an INCORRECT (c) Variable components can be eliminated by
Boolean expression? using Karnaugh maps
(a) PQ PQ Q (d) Karnaugh maps provide a cookbook ap
proach to simplicity Boolean expression
(b) P Q P Q P
9. Which of the following is an important feature of
(c) P P Q Q the sum of products (SOP) form of expression?
(d) PQR PQR PQR PQR Q (a) All logic circuits are reduced to nothing move
than simple AND and OR gates
5. The Boolen expression ( AB )( A B )( A B ) can (b) The delay lines are greatly reduced over
be simplified to other forms.
(a) A B (b) AB (c) No signal must pass through more than two
(c) A B (d) AB gates, not inclusing.
6. The number of input combinations and the num- (d) The maximum number of gates that any signal
ber of ones in the truth table for the expression must pass through is reduced by a factor of
ABC ABC ABC are respectively,, two.
[HCU PhD 2013]
(a) 1,3 (b) 2,6
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10. The truth table for the SOP expression
AB BC has two manu input combinations ? (a) P Q QR S
(a) 1 (b) 2 (b) P Q QR S
(c) 4 (d) 8 (c) P Q QR S
11. Minimized form of the following Boolean ex-
(d) P Q QR S
pression.
15. Which of the following circuits represent the Bool-
X ABC ABC ABC ABC ean expression
(a) A B C (b) A B C S P QR QP
(c) ABC (d) A BC P
S
(a)
Q
12. Determine the values of A,B,C and D that make
the sum term A B C D equal to zero P
(b) Q S
(a) A 1, B 0, C 0, D 0
P
(b) A 1, B 0, C 1, D 0 (c) Q
S
(c) A 0, B 1, C 0, D 0 R
(d) A 1, B 0, C 1, D 1 (d) none of these
16. Which of the following is a correct and simplest
13. Which of the following circuits does not satisfy expression for the Boolean function (Y) described
the Boolean expression A B A B F . by the Karnaugh map ?
A
B BC BC BC BC
F A
(a) 1 1
A
1 X X
A
B (a) Y = C (b) Y C
(b) F
(c) Y C AB (d) Y BC AC
Statement for Linked Q.17 and Q.18
A
B The Karnaugh map of a logic circuit is shown be-
(c) F low :
A R R
B
(d) F PQ 1 1
PQ 1
14. The logic expression for the output Y of the fol- PQ [GATE 2009]
lowing circuit is :
PQ 1 1
P
Q
Y 17. The minimized logic expression for the above map
R
is :
S
(a) Y = PR + Q (b) Y = [Link]
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(c) Y = Q + PR (d) Y =[Link]
C B A F
18. The corresponding logic implementation using gates
is given as : 0 0 0 d
0 0 1 1
P
R
0 1 0 1
(a) Y
Q 0 1 1 d
1 0 0 0
P 1 0 1 0
R
(b) Y 1 1 0 0
Q
1 1 1 1
P
(c) R Y Where d represents don’t care states. The mini-
Q
mized expresssion for F is
(d) None of the above (a) B.C A.C A.B
19. From the truth table below, determine the stan- (b) A.B C
dard SOP expression (c) A.B.C A.B.C A.B.C
(d) None of these
21. Consider the following truth table:
Input Output The logic expression for F is :
A B C X
0 0 0 0 A B C F
0 0 0 1
0 0 1 1
0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 0 1 1 0
1 0 0 0 1 0 0 1
1 0 1 1
1 0 1 0
1 1 0 1
1 1 0 1 1 1 1 0
1 1 1 0
(a) AB BC CA
(a) X ABC ABC ABC
(b) X ABC ABC ABC (b) AB AC BC
(c) X ABC ABC ABC
(c) C AB AB
(d) X ABC ABC ABC
20. The truth table for implementing a boolean vari-
(d) C A B AB
able F is given by
22. Convert the following SOP expression to an
equivalent POS expression
ABC ABC ABC ABC ABC
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(a) A B C A B C A B C (a) BD + BC (b) BD + BC AB
(b) A B C A B C A B C (c) D + BC (d) CD + BC BCD
27. A 4-variable switching function is given by
(c) A B C A B C A B C f (5, 7,8,10,13,15) d (0,1, 2), where d is
(d) A B C A B C A B C the do-not care condition. The minimized form of
f in sum of products (SOP) form is
23. The Boolean equation [NET Dec. 2013]
ABC ABC ABC ABC is to be (a) AC BD (b) AB CD
implemented using ony two-input NAND gate. (c) AD BC (d) BD BD
The minimum number of gates required is 28. The circuit is formed as shown below. The
[NET June 2020] output S and C implement
(a) 3 (b) 4
B A
(c) 5 (d) 6
24. Simplify Boolean function represented in sum of
product of min-terms
S
F x, y, z 0,2, 4,5,6
(a) Z XY
(b) X Y Z X Y Z X Y Z
A
C
(c) X Y Z X Y Z
B
(d) X Y Y Z Z X
(a) Two bit adder with sum and carry respec
25. The possible Boolean expression for the Karnaugh tively
map shown in figure
(b) Two bit subtractor with sum and borrow
respectively
1 1
1 1 (c) S AB AB , C AB
1 1 1 (d) None of the above
1 1 1
29. The 2’s cpmplement of 1111 1111 is
(a) X BC AC BC CD [JEST 2020]
(a) 0000 0001 (b) 0000 0000
(b) X BC BC AB CD
(c)1111 1111 (d)1000 0000
(c) X BC AC BC BD
(d) (a) and (b) only 30. The decimal equivalent of 368.35 8
26. The simplified Boolean expression for (a) 242.453125 (b) 246
Y m (0, 2, 4,5,8,10) d (6,12,13), is: (c) 242.453125 (d) 422.453125
[DU 2014] 31. A Binary equivalent of CD578 16
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(a) 1100, 1101, 0101, 0110, 1001 (b) Three inputs and two outputs
(c) Two inputs and one output
(b) 1101, 1011, 0101, 0111, 1000
(d) Two input and two outputs.
(c) 1101, 1011, 0101, 0111, 1000
41. For exact calculation and minimum complexity, two
(d) 1100, 1101, 0101, 0111, 1000 four-digit binary numbers can be added with
32. Convert 940 10 to binary system [TIFR 2017]
(a) 1 full adder and 3 half-adders
(a) (1110101101) (b) (110101100)
(b) 2 full adders and 2 half-adders
(c) (1110101100) (d) (1001101011)
(c) 3 full adders and 1 half-adder
33. Which one of the following is the correct binary (d) 4 full adders
equivalent of the hexadecimal F 6C
[GATE 2020]
ANSWER KEY
(a) 0110 11111100
1. (d) 2. (b, d) 3. (a)
(b) 1111 0110 1100 4. (d) 5. (c) 6. (c)
(c) 1100 0110 1111 7. (c) 8. (d) 9. (c)
(d) 0110 1100 0111 10. (d) 11. (b) 12. (b)
13. (d) 14. (a) 15. (b)
34. Convert 2040 10 to octal system
16. (d) 17. (a) 18. (d)
(a) (3770) (b) (3660) 19. (d) 20. (b) 21. (d)
(c) (2370) (d) (4320) 22. (b) 23. (b) 24. (a)
25. (a, b, c) 26. (a) 27. (d)
35. The decimal equivalent of the hexadecimal num- 28. (b) 29.(a) 30. (a)
ber (A 3B) 16 is
31. (d) 32. (c) 33. (b)
(a) (2361)10 (b) (2621)10
34. (a) 35. (c) 36. (a)
(c) (2619)10 (d) (2879)10
37. (b) 38. (b) 39. (b)
36. Octal equivalent of decimal number 47810 is 40. (d) 41. (c)
(a) 7368 (b) 6738
(c) 6378 (d) 3678
37. Octal equivalent of 634.640625 is
(a) 6 (b) 5
(c) 3 (d) 4
38. Decimal equivalent of 0.1358 is
(a) 0.18163107 (b) 0.1816406
(c) 0.1618306 (d) 0.1618407
39. Octal equivalent of 101101010 2
(a) 650 (b) 552
(c) 432 (d) 537
40. A half -adder is a digital circuit with
[GATE 2004]
(a) Three inputs and one output
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ELECTRONICS: MULTIPLEXER AND DEMULTIPLEXER
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. How many select lines are required for 1-to-8 5. The logic function implemented by following 4:1
demultiplexer ? MUX is
(a) 2 (b) 3
(c) 4 (d) 5
2. Following circuit implemets a X I0
Y I1
A0 Z
X I2
0 I3
Y
I0 X(MSB) Y(LSB)
A1
(a) Z = X and Y (b) Z = X or Y
(a) De-Multiplexer (b) Multiplexer
(c) Z = X EX-OR Y (d) Z = X EX-NOR Y
(c) Y I 0 A0 A1 (d) Y I 0 A1 A0 6. In the following circuit Y can be expressed as
3. A 2 4 decoder with an enable input can
function as a [NET June 2017] 0
(a) 4 1 multiplexer 1
4 to 1
(b) 1 4 demultiplexer 0 MUX 0
(c) 4 2 encoder
2 to 1
(d) 4 2 priority encoder 1 MUX
4. The combinational logic circuit in the given figure
has an output Q which is A B
C
C I0
1 I1 Q
(a) Y BC A (b) Y C
1 I2
1 I3 MUX (c) Y AC ' BC (d) Y B
7. Which of the following circuits implements the
A B
Boolean function F A, B, C 1, 2, 4, 6 ?
(a) ABC (b) A+B+C
NET Dec. 2016]
(c) A B C (d) A B C
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C I0 A0
I1
4 1 F (a) C X
(a) I2 MUX
I3
S1 S0 A1
A B A0
(b) C X
C I0
I1
4 1 F A1
(b) I2 MUX
I3
S1 S0 A0
A B (c) X
C
A1
C I0
I1
1 4 1 F A0
I 2 MUX
(c)
I3
(d) C X
S1 S0
A B A1
9. In the given combinational logic, X is given by
0 I0
I1
41 F 0 I0 0
I2 MUX
(d) C I3 1 I1 Y 1 4:1 MUX
4:1 MUX Y X
1 I2 1
S1 S0
0 I3 0
S1 S2 S1 S2
A B
8. In a 2-to-1 multiplexer as shown below, the out- A B C
put X A0 if C = 0, and X A1 if C 1 .
Which one of the following is the correct imple- (a) X ABC ABC ABC ABC
mentation of this multiplexer ? [GATE 2018]
(b) X ABC ABC ABC ABC
C
(c) X AB BC AC
A0
X
A1 (d) X AB BC AC
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10. The 4:1 multiplexer implemented as
0
A
Y
B C
(a) 1,6,3,7 (b) 1,2,5,7
(c) 2,3, 4,5 (d) 1,3, 4,7
ANSWER KEY
1. (b) 2. (b) 3. (b)
4. (b) 5. (c) 6. (d)
7. (b) 8. (a) 9. (a)
10. (a)
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ELECTRONICS: A to D and D to A CONVERTER
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. A 3-bit analog-to-digital converter is designed to mum value of n is _______________
digitize analog signals ranging from 0V to 10V. [GATE 2014]
For this converter, the binary output corre- 7. To measure the voltage in the range 0 5 V
sponding to an input of 6V is [GATE 2019] with a precision of 5 mV, the minimum number
(a) 011 (b) 101 of bits required in a digital voltmeter is
[TIFR 2015]
(c) 100 (d) 010
(a) 9 (b) 10
2. Minimum number of bits required to represent (c) 11 (d) 12
maximum value of given analog signal with 0.1%
accuracy is 8. A 5 bit DAC has a current output. For a digital
input of 10100, an output current of 10m, is
(a) 8 bits (b) 9 bits produced. What will be the output current for a
(c) 10 bits (d) 12 bits digital input of 11101?
3. The number of comparators needed in a 8 bit flash (a) 14.5mA (b) 10mA
type A to D converter is (c) 100mA
(a) 8 (b) 16 (d) Not possible to calculate
(c) 255 (d) 256 9. The largest analog output voltage from a 6-bit digital
4. For a 10-bit digital ramp ADC using 500kHz to analog converter (DAC) which produces 1.0
clock, the maximum conversion time is V output for a digital input of 010100, is :
[GATE 2006]
(a) 2048s (b) 2064s (a) 1.6 V (b) 2.9 V
(c) 3.15 V (d) 5.0 V
(c) 2046s (d) 2084s
10. The full scale of a 3-bit digital-to-analog (DAC)
5. The full scale voltage of an n-bit Digital-to-Ana- converter is 7 V. Which of the following tables
log Converter is V. The resolution that can be represents the output voltage of this 3-bit DAC
achieved in it is [NET Dec 2017] for the given set of input bits ?
V V [NET June 2018]
(a) n (b) n
(2 1) (2 1)
Input bits Output voltage
V V
(c) 2 n (d) 000 0
2 n
001 1
6. In order to measure a maximum of 1V with a reso- (a) 010 2
lution of 1mV using a n-bit A/D converter, work- 011 3
ing under the principle of ladder network, the mini-
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2
Input bits Output voltage
000 0
001 1.25
(b) 010 2.5
011 3.75
Input bits Output voltage
000 1.25
001 2.5
(c) 010 3.75
011 5
Input bits Output voltage
000 1
001 2
(d) 010 3
011 4
ANSWER KEY
1. (c) 2. (c) 3. (c)
4. (c) 5. (a)
6. (0.99 to 10.01) 7. (b)
8. (a) 9. (c) 10. (a)
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ELECTRONICS: RECTIFIER, FILTER, OSCILLATOR
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. One condition for oscillation is : [BHU PhD 2015]
Input HP HP Output
(a) A phase shift around the feedback loop of 180° (A) f HP f LP
(b) A gain around the feedback loop of one third
HP
(c) A phase shift around the feedback loop of 0° f HP
(d) A gain around the feedback loop of less than 1 Input Output
(B)
2. For an oscillator to properly start, the gain around HP
the feedback loop must initially b : f LP
Which of the following statements is correct ?
[BHU PhD 2015]
[NET Dec. 2014]
(a) 1 (b) < 1 (a) For f HP f LP , A acts as a Band Pass filter
(c) > 1 (d) infinite and B acts as a Band Reject filter
3. Ripple factor for a half wave rectifier is___ (b) For f HP f LP , A stops the signal from pass-
(a) 1.65 (b) 1.45 ing through and B passes the signal without filter-
(c) 1 (d) 1.21 ing
4. A circuit constructed using Op-Amp, resistor (c) For f HP f LP , A acts as a Band Pass filter
R1 1k and capacitors C1 1F and and B passes the signal without filtering
C2 0.1F , shown in the figure below, is (d) For f HP f LP , A passes the signal without
filtering and B acts as a B and Reject filter
R1
6. A time varying signal Vin is fed to an Op-Amp
C2 circuit with output signal V0 as shown in the figure
C1 below. The circuit implements a
Vi [NET June 2011]
Vo
10k
1k
(a) high pass filter (b) low pass filter + V0
Vin
1k
(c) band pass filter (d) band reject filter 10k
10k 1F
5. Consider a Low Pass (LP) and a High Pass (HP)
filter with cut-off frequencies f LP and f HP , re-
spectively, connected in series or in parallel con- +
figurations as shown in the Figures A and B be- (a) High pass filter with cutoff frequency 16 Hz.
low.
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(b) High pass filter with cutoff frequency 100 Hz. 10. In the circuit shown below, capacitors C1 and C2
(c) Low pass filter with cutoff frequency 16 Hz. are very large and are shorts at the input frequency
(d) Low pass filter with cutoff frequency 100 Hz. Vi is a small signal input. The gain magnitude
7. Two sinusoidal signals are sent to an analog multi- |V0/Vi| at 10M rad/sec is
plier of scale factor 1V 1 followed by a low pass 5V
filter (LPF).
v1 5 cos(100t ) 10 H 2k
1nF
Multiplier LPF +
f c 5 Hz v out C2
Q1
2.7V 2k
v2 = 20 cos (100t + /3) V0
2k C1
If the roll-off frequency of the LPF is f c 5 Hz ,
Vi
the output voltage Vout is [NET Dec. 2016] –
(a) 5 V (b) 25 V
(c) 100 V (d) 50 V
(a) Maximum (b) Minimum
8. A low pass filter is formed by a resistance R and a
capacitance C. At the cut-off angular frequency (c) Unity (d) Zero
1 ANSWER KEY
c , the voltage gain and the phase of
RC
the output voltage relative to the input voltage re- 1. (c) 2. (c) 3. (d)
spectively, are [GATE 2014] 4. (a) 5. (c) 6. (a)
7. (b) 8. (b) 9. (b)
(a) 0.71 and 45o (b) 0.71 and -45o
10. (a)
(c) 0.5 and -90o (d) 0.5 and 90o
9. What Should be the values of the components R
and R2 such that the frequency of the Wein-Bridge
oscillator is 300Hz
[GATE 2004]
R1 R2
+ V0
C
R
R C
[Given: C = 0.01 μF and R 1 12kΩ]
(a) R 48kΩ and R 2 12kΩ
(b) R 26kΩ and R 2 24kΩ
(c) R 530kΩ and R 2 1MΩ
(d) R 53kΩ and R 2 24kΩ
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ELECTRONICS: FET, JFET & BJT
CSIR - NET - JRF / GATE / JEST / TIFR
PREVIOUS YEARS’ QUESTIONS
1. A field effect transistor is a [GATE 2004] 5. An n-channel FET having Gate-Source switch-
(a) Unipolar device off voltage VGS OFF 2V is used to invert
(b) Special type of bipolar junction transistor.
(c) Unijunction device 0 5V square wave signal as shown. The maxi-
(d) Device with low input impedance mum allowed value of R would be ______ kΩ
(up to two decimal places).
2. A junction field effect transistor behaves as a
[GATE 2005]
+5V
(a) Voltage controlled current source
5 k
(b) Voltage controlled voltage source
(c) Current controlled voltage source
(c) Current controlled current source 5V Vout 5V
V in R
0V
3. The high input impedance of field effect transistor 0V
(FET) amplifier is due to [GATE 2006] 1 k 100
(a) The pinch-off voltage
(b) Its very low gate current. -12V
(c) The source and drain being far apart
(d) The geometry of the FET. [GATE 2018]
6. In the given circuit, the voltage across the source
4. In the circuit shown , the voltage at test point P is
resistor is 1 V. The drain voltage (in V) is _______
12V and the voltage between gate and source is
–12V. The value of R (in k ) is
25V
[GATE 2007]
VDD = 16V P 4k
5 k
2k
2 M 500
R 42k
[GATE 2015]
(a) 42 (b) 48
(c) 56 (d) 70
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7. Refer the figure shown below. The value of IG is, be the value of RC and RB to set the quiescent
+20V
point ( Q point) at I C 10mA and VCE 8V ?
RD = 2k
10V
G
ID = 6 mA
RG = 100M RB RC
RS = 1k
(a) 6 mA (b) 4 mA
(c) 2 mA (d) 0 mA
8. In the n- channel JFET shown in the figure below,
Vi 2V , C 10 pF ,VDD 16V and (a) RC 200, RB 93k
RD 2k (b) RC 2k , RB 100k
VDD (c) RB 83k , RC 100
RD
(d) RC 20, RB 93k
D V0
G C ANSWER KEY
Vi
S 1. (a) 2. (a) 3. (b)
4. (d) 5. (0.70) 6. (15V)
7. (d) 8. (d) 9. (a)
If the drain D, source S, saturation current I DSS is 10. (a)
10mA and the pinch-off voltage V p is –8V, then
the voltage across points D and S is
[NET June 2017]
(a) 11.12V (b) 10.375V
(c) 5.75V (d) 4.75V
9. What is the voltage at gate VGS?
VCC =20V
R1=17k R3
C2
C1
Q1
Vin
Vout
R2 =6k R4 C3
(a) 5.2V (b) 4.2V
(c) 3.2V (d) 2.2V
10. A BJT is having common emitter current gain 100.
Considering 10V supply and VBE 0.7V what will
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ELECTRONICS: A to D and D to A CONVERTER
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. A 3-bit analog-to-digital converter is designed to V V
digitize analog signals ranging from 0V to 10V. (c) (d)
22n n
For this converter, the binary output corre-
sponding to an input of 6V is [GATE 2019] Ans. a
(a) 011 (b) 101 6. In order to measure a maximum of 1V with a reso-
lution of 1mV using a n-bit A/D converter, work-
(c) 100 (d) 010 ing under the principle of ladder network, the mini-
Ans. c mum value of n is _______________
[GATE 2014]
2. Minimum number of bits required to represent Ans. 0.99 to 10.01
maximum value of given analog signal with 0.1%
accuracy is 7. To measure the voltage in the range 0 5 V
(a) 8 bits (b) 9 bits with a precision of 5 mV, the minimum number
of bits required in a digital voltmeter is
(c) 10 bits (d) 12 bits [TIFR 2015]
Ans. c (a) 9 (b) 10
3. The number of comparators needed in a 8 bit flash (c) 11 (d) 12
type A to D converter is Ans. b
(a) 8 (b) 16 8. A 5 bit DAC has a current output. For a digital
(c) 255 (d) 256 input of 10100, an output current of 10m, is
produced. What will be the output current for a
Ans. c digital input of 11101?
4. For a 10-bit digital ramp ADC using 500kHz (a) 14.5mA (b) 10mA
clock, the maximum conversion time is
(c) 100mA
(a) 2048s (b) 2064s
(d) Not possible to calculate
(c) 2046s (d) 2084s Ans. a
Ans. c 9. The largest analog output voltage from a 6-bit digital
to analog converter (DAC) which produces 1.0
5. The full scale voltage of an n-bit Digital-to-Ana-
V output for a digital input of 010100, is :
log Converter is V. The resolution that can be
[GATE 2006]
achieved in it is [NET Dec 2017]
(a) 1.6 V (b) 2.9 V
V V (c) 3.15 V (d) 5.0 V
(a) (b)
(2 1)
n
(2 1)
n
Ans. c
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ELECTRONICS: FEEDBACK AND AMPLIFIER
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. The input impedance of an amplifier increases by 6. In an amplifier the negative feedback is a process
the introduction of feedback. It is due to : where a portion of output signal is fed to the input
(a) Positive feedback of the normal amplifier with the condition that the
(b) current series negative feeeback input signal is :
(c) current shunt negative feedback
(a) in phase (b) 90° out of phase
(d) voltage shunt negative feedback
(c) 180° out of phase (d) any arbitary phase
2. A CE amplifier is preferred over other configura-
7. An amplifier with 10% negative feedback has an
tions (CB and CC) because it has:
open-loop gain of 100. If the open-loop gain
[BHU PhD 2017]
changes by 10%. What would be the correspond-
(a) Current gain but
ing change in gain with feedback ?
(b) No current gain but voltage gain
(a) 9% (b) 0.9%
(c) Current as well as voltage gain
(c) 0.09% (d) 90%
(d) None of these
8. The effect of current shunt feeback in an amplifier
3. The input impedance (Zi) and output impedance
is to
(Z0) of an ideal transconductance (voltage con-
(a) Increase the input resistance and decrease the
trolled current source) amplifier are
output resistance
(a) Z i 0, Z 0 0 (b) Z i , Z 0 0 (b) Increase both input and output resistance
(c) Z i 0, Z 0 (d) Z i , Z 0 (c) Decrease both input and output resistance
(d) Decrease the input resistance and increase the
4. In a RC coupled amplifier, the reduction in voltage
output resistance
gain in the high frequency range results due to :
9. In one of the following circuits, negative feedback
(a) coupling capacitor
does not operate for a negative input. Which one
(b) shunt capacitance in the circuit
is it ? The Op-Amps are running from 15V sup-
(c) series capacitance in the circuit
(d) bypass capacitor in the inner circuit plies. [GATE 2010]
5. A current amplifier is characterised by 5.1V
[GATE 1996]
(a) low input impedance and high output imped- (a) + (b) +
ance
(b) high input impedance and low output imped-
ance.
(c) low impedance at both input and output termi-
(c) + (d) +
nals.
(d) high impedance at both input and output ter-
minals.
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10. The circuit of the figure in an example of feedback plifier using the above amplifier with a feedback
of the following type factor of 0.2 is
1 1
+VCC (a) k (b) k
11 5
V0 (c) 5k (d) 11k
15. An amplifier of gain 1000 is made into a feedback
amplifier by feeding 9.9% of its output voltage in
Vi series with the input opposing. If f L = 20 Hz and
f H = 200 kHz for the amplifier without feedback,
then due to the feedback. [GATE 2009]
(a) Current series (b) Current shunt (a) The gain decreases by 10 times
(c) Voltage series (d) Voltage shunt (b) The output resistance increases by 10 times
11. An amplifier is designed to have a gain of 60 but (c) The fH increases by 100 times
when constructed it shows a gain of 50. What (d) The input resistance decreases by 100 times
should the value of positive feedback increase the 16. In the given circuit, if the open loop gain A = 105,
gain to the desired level ? the feedback configuration and the closed loop
(a) 3.33% (b) 0.33%
gain Af are [GATE 2015]
(c) 33% (d) 30%
12. A feedback amplifier has an open loop gain of
–100 . If 4% of the output is fed back in a V1 + V0
degenerance loop, the closed loop gain of the am-
plifier would be: [DU PhD 2018]
(a) +25 (b) +33
1k k
(c) –30 (d) –20 RL
13. An amplifier with negative feedback has a voltage
gain of 100. It is found that with feedback an input
signal of 0.6 V is required to produce a given out-
(a) series -shunt, A f 9
put whereas without feedback the input signal must
be only 50 mV for the same output. Then the volt- (b) series-series, Af 10
age gain without feedback A and feedback factor
(c) series- shunt, Af 10
are
(d) shunt-shunt, Af 10
9
(a) A 1000,
1000 17. An amplifier has a 40 dB gain. Its gain may change
10 by 100%. Then the value of feedback factor is
(b) A 1100,
1100 (a) 0.1 (b) 10
13 (c) 0.09 (d) 0.001
(c) A 1400,
1200
18. Two signals A1 sin t and A2 cos t are fed
11 into the input and the reference channels, respec-
(d) A 1200,
1200 tively, of a lock-in amplifier. The amplitude of each
14. An amplifier without feedback has a voltage gain signal is 1V. The time constant of the lock-in am-
of 50, input resistance of 1k and output resis- plifier is such that any signal of frequency larger
tance of the current shunt negative feedback am- than is filtered out. The output of the lock-in
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amplifier is [NET June. 2018] (c) 6.99 MHz to 7. 00 MHz
(a) 2V (b) 1 V (d) 6.995 MHz to 7.005 MHz
(c) 0.5 V (d) 0 V
19. An amplifier has a voltage gain of 500 and an in-
ANSWER KEY
put impedance 20 k , without any feedback.
Now a negative feedback with β = 0.1 is applied. 1. (c) 2. (c) 3. (d)
Its gain and input impedance with feedback will 4. (a) 5. (a) 6. (c)
respectively be [GATE 1996] 7. (b) 8. (d) 9. (c)
(a) 9.8 and 392 k ohms 10. (d) 11. (b) 12. (d)
(b) 9.8 and 1020 k ohms 13. (b) 14. (a) 15. (c)
(c) 50 and 1020 k ohms 16. (c) 17. (c) 18. (d)
19. (b) 20. (a) 21. (a)
(d) 50 and 2 k ohms
22. (d)
20. An amplifier has a voltage gain AV 1000 , input
impedance 1k and output impedance 500 .
A fraction V 0.1 of the output voltage is fed
back in the series in opposition to the input volt-
age. The input and output impedance after the feed-
back are given respectively by the approximate
values.
(a) 100k and 5
(b) 1k and 5
(c) 10 and 50
(d) 100 and 100
21. An RC amplifier has mid frequency gain of 100,
lower half-power frequency f1 100 Hz and
upper half-power frequency f 2 30 kHz. If a
negative feedback is introduced in the amplifier
with feedback ratio 0.05 . Than the new fre-
quencies f1 and f 2 are respectively
(a) 16.6 Hz, 180 kHz
(b) 180 kHz, 16.6 Hz
(c) 166 Hz, 18 kHz
(d) 18 kHz, 166 Hz
22. A live music broadcast consists of a radio-wave
of frequency 7 MHz, amplitude-modulated by a
microphone output consisting of signals with a
maximum frequency of 10 kHz. The spectrum of
modulated output will be zero outside the fre-
quency band [NET Dec. 2012]
(a) 7.00 MHz to 7.01 MHz
(b) 6.99 MHz to 7.01 MHz
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ELECTRONICS: TRANSIENT PHENOMENA AND NETWORK THEORY
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. The current i flowing through the following circuit 5
is [TIFR 2018]
38V R L 76V
3
3
3 (a) 48 (b) 52
3
3
(c) 56 (d) 65
i
3 5. The phase difference between input and out-
3V
put voltage for the following circuits (i) and (ii) will
(a) 0.5 A (b) 0.6 A be
(c) 0.75 A (d) 1.0 A
2. The amount of current flowing through the 6 re-
C
sistor in the following network is
[HCU PhD 2019]
vi C v0
3 3
(i)
3 3
3 3
2.4V
3 3
3 3 R
(a) 0.2A (b) 0.4A vi v0
C
(c) 0.8A (d) 2.0A
3. The Thevenin and Norton circuits are
(a) Single frequency equivalent circuits
(ii)
(b) Multi frequency equivalent circuits
(c) Equivalent independent of frequency
(a) 0 and 0
(d) Band frequency equivalent circuits
(b) / 2 and 0 / 2 respectively
4. For the circuit shown, the potential difference (in
Volts) across RL is : [GATE 2007] (c) / 2 and / 2
(d) 0 and 0 / 2 respectively
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6. It is found that when the resistance R indicated in
VA
the figure below is changed from 1 k to 10 k The ratio is
VB
the current flowing the resistance R ' does not
change. What is the value of the resistor R ' ? (a) 0.58 (b) 1.73
[JEST 2016] (c) 1 (d) 2
9. A 10V battery is connected in series to a resistor
10 k R and a capacitor C, as shown in the figure
1k R 1k 47k
R'
5V 10 k V=10V 10F
C
(a) 5 k (b) 100 k
The initial charge on the capacitor is zero. The switch
(c) 10 k (d) 1 k is turned on and the capacitor is allowed to charge
7. What is the charge stored on each capacitor C1 and to its full capacity. The total work done by the bat-
tery in this process is [NET June 2020]
C2 in the circuit shown in the given figure.
(a) 10 3 J (b) 2 10 3 J
[JEST 2020]
(c) 5 104 J (d) 47 10 2 J
6 10. In the circuit shown in the figure the Thevenin volt-
age VTh and Thevenin resistance RTh as seen by
2 F F the load resistance R L 1k are respec-
tively. [GATE 2005]
C1 C2
2k 2k
20V R
L
10V
(a) 6c ,6c (b) 6c,3c
(a) 15V, 1kΩ (b) 30V, 4 kΩ
(c) 3c,6c (d) 3c,3c
8. Two voltmeter A and B with internal resistances (c) 20V, 2 kΩ (d) 10V, 5 kΩ
11. An ac signal of the type as shown inthe figure, is
2M and 0.1k are used to measure the volt-
applied across a resistor R 1
age drops V A and VB , respectively, across the re- [NET June 2019]
sistor R in the circuit shown below. 8
[NET June 2020]
V(Volts) 3
R –2
t
The power dissipated across the resistor is
(a) 12.5W (b) 9W
(c) 25W (d) 21.5W
12. A current source produces a square wave I(t) of
1.0V peak-to-peak voltage and is used to drive
the RC circuit shown below. [TIFR 2017]
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I(t) R
V(t) R C
C
Which of the following represents the correct volt- vi R C v0
age across the capacitor C ?
(a)
1 1
(a) and 0 (b) and 0
2 3
(b) 1 1
(c) and (d) and
2 2 3 2
15. For the circuit depicted on the right, the input volt-
(c) age Vi is a simple sinusoid as shown below, where
the time period is much smaller compared to the
time constant of this circuit. [TIFR 2016]
(d)
R
13. A Capacitor C is connected to a battery V0 through
Vi C V0
three equal resistors R and a switch S as shown
below :
S R R 1
R 0.5
V0 C
0
The capacitor is initially uncharged. At time t = 0, 0.5
the swithch S is closed. The voltage across the 1
capacitor as a function of time ‘t’ for t > 0 is given 0 0.5 1 1.5 2 2.5 3
by [JEST 2012] Time
(a) V0 / 2 1 exp t / 2 RC
The voltage V0 across C is best represented by
(b) V0 / 3 1 exp t / 3 RC
1
(c) V0 / 3 1 exp 3t / 2 RC
0.5
(d) V0 / 2 1 exp 2t / 3 RC (a)
0
14. In the following RC network, for an input signal
0.5
1 v0
frequency f , the voltage gain v and 1
2RC i 0 0.5 1 1.5 2 2.5 3
Time
the phase angle between v0 and vi respec-
tively are
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2
1
1
0.5 0
log I
(b)
0 -1
0.5 (b) -2
1 -3
0 1 2 3
0 0.5 1 1.5 2 2.5 3 aV/T
Time
2
1 1
0.5 0
log I
(c)
0 -1
(c) -2
0.5
-3
1 0 1 2 3
0 0.5 1 1.5 2 2.5 3 aV/T
Time
17. An RC network produces a phase-shift of 30o.
1 How many such RC networks should be cascaded
together and connected to a Common Emitter
0.5 amplifier so that the final circuit behaves as an os-
(d) cillator? [NET June2014]
0
0.5 (a) 6 (b) 12
(c) 9 (d) 3
1
0 0.5 1 1.5 2 2.5 3
Time 4
3
16. The I-V characteristics of a device is 2
1
log I
aV , where T is the tempera-
I I s exp 1 0
T -1
(d)
ture and a and Is are constant independent of T -2
and V. Which one of the following plots is correct -3
0 1 2 3
for a fixed applied voltage V ? aV/T
[NET Dec 2016]
18. An inductor L, a capacitor C and a resistor R are
3
connected in series to an AC source
2
V V0 sin t . If the net current is found to de-
log I
pend only on R, then [NET June 2020]
1 (a) C 0 (b) L 0
(a)
0 1 1 R2
0 1 2 3 (c) (d) 2
aV/T LC LC 4 L
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19. Two LCR circuits (A) and (B) are shown below
where Cc << C. At time t = 0, a charge Q is put
on the capacitor C. [TIFR 2015] (a) (b)
C (c) (d)
R C L C L
R
22. Find the resonance frequency (rad/sec) of the cir-
cuit shown in the figure below [JEST 2014]
(A) (B)
Which of the following statements is correct ?
(a) The charge Q will decay faster in (A)
V 0.25F 2
(b) The charge Q will decay faster in (B)
3
(c) The charge Q will decay at the same rate in
(A) and (B) 2H
(d) The relative decay rates cannot be predicted
without knowing the exact values of L, C, R and (a) 1.41 (b) 1.0
Cc
20. The insulation resistance R of an insulated cable is
measured by connecting it in parallel with a ca- (c) 2.0 (d) 1.73
pacitor C, a voltmeter, and battery B as shown. 23. A realistic voltmeter can be modelled as an ideal
The voltage across the cable dropped from 150V voltmeter with an input resistor in parallel as shown
to 15V, 1000 seconds after the switch S is closed. below.
If the capacitance of the cable is 5 F then its
insulation resistance is approximately
[NET June. 2013]
S
Such a realistic voltmeter, with input resistance
B V R C 1k , gives a reading of 100 mV when connected
to a voltage source with source resistance 50 k .
What will a similar voltmeter, with input resistance
1M , read in mV, when connected to the same
(a) 109 (b) 108
voltage source ? [TIFR 2018]
(c) 107 (d) 106
21. The figure below shows an unknown circuit, with
an input and output voltage signal. ANSWER KEY
[TIFR 2013] 1. (c) 2. (b) 3. (a)
4. (a) 5. (d) 6. (b)
Input OUTPUT 7. (a) 8. (b) 9. (a)
UNKNOWN 10. (a) 11. (d) 12. (d)
CIRCUIT 13. (d) 14. (b) 15. (b)
16. (d) 17. (a) 18. (c)
From the form of the input and output signals, one 19. (a) 20. (b) 21. (b)
can infer that the circuit is likely to be 22. (b) 23. (105)
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DIGITAL ELECTRONICS
CSIR-NET-JRF/GATE/JIFR/JEST
ASSIGNMENT-2
1. For a 3-variable function given that F A, B, C (a) MQ NQ (b) MQ NQ
M 0,1, 2,3, 4,5,6,7 . The minimzed boolean (c) M N Q (d) M N Q
5. In the following circuit, output X is
function is
M
(a) ABC (b) A + B + C N
Q
(c) 0 (d) 1
2. For a 3-variable function given that f A, B, C
X
m 1, 2,3, 4,5,6,7 . The mimimized Boolean
function is
(a) ABC (b) A B C
(a) MN NQ QM (b) MNQ
(c) 0 (d) 1
3. In the figure shown below, the input conditions (c) M N Q (d) MN Q
needed to activate output z is 6. Find the output Z
A
B Z
A
C C
D Z
(a) A = C = 0 and B = D = 1
(b) A = B = C = 1 and D = 0
B
(c) A = B = 0 and C = D = 1
(d) A = B = C = D = 1
(a) AB C (b) AB C
4. In the following circuit, output X is
M (c) A B C (d) A B C
N
Q 7. In the following circuit, the output Z is
A
X
B Z
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(a) A B A B (b) AB BA
(c) AB A (d) A A
8. In the following circuit, output X is: B
A
X
B C
(b)
X
C
(a) A B C (b) A B C
(c) ABC (d) ABC
A
9. Find the output Z B
A
B X
(c)
Z
C
C
(a) A B B C (b) AB AC BC A
(c) AB AC BC (d) AB BC B
10. The output Z is
X
A
B (d)
C
D Z
C
E
(a) A B C DE (b) ABC D E 12. The output X is
(c) ABC DE (d) ABC D E A
11. The logic circuit of boolean expression B
AB AB ABC is
X
A
B
X (a) AB (b) AB
(a) (c) AB (d) AB
13. The output Y is
C
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X
A
B Y
C Y
Z
Y
(a) XY XY Z (b) XY XY Z
D
(c) XY XY Z (d) XY XY Z
E
21. Consider a logic circuit,
(a) A B C DE (b) AB C D E A
Y
(c) A B C D E (d) A B C DE
B
14. Wha does the Boolean expression F on minimiza-
tion result into? For the inputs A, B sequence (0,0), (1,0) and
F AD ABCD ACD AB ACD AB (1,1), the output Y sequence will be
(a) A D (b) AD A
(a) 0,0,0 (b) 1,0,0
(c) AD (d) A D (c) 0,0,1 (d) 1,1,0
15. The boolean expression 22. Consider the following arrangements of logic gates
AB ABC ABCD ABCDE is equivalent to as shown:
(a) AB (b) AB
X
(c) ABC (d) ABC
16. Which of the following is not correct? Z
(a) X XY X (1)
Y
(b) X X Y XY
(c) X XY X
(d) ZX ZXY ZX ZY X
17. Consider the logical function, (2) Z
Y
A AB ABC ABCD ABCDE .... X ,
X
then ‘ X ’ equals to
(3) Y Z
(a) 0 (b) 1
(c) A (d) AB
18. Consider a 4 input NAND gate. How many num-
ber of input conditions are possible, that will produre X
output “High”. Z
(4)
(a) 0 (b) 1 Y
(c) 2 (d) 15
19. If A B , then the value of Boolean expression, Which of these above represents the function of an
OR gate?
A B A B AB AB equal to (a) 1 and 3 (b) 2 and 3
(c) 1,2 and 3 (d) All of the above
(a) 0 (b) 1
(c) A B (d) AB 23. Consider the 2 inputs A,B and data, output Y
20. Find output Y logical gates AND, OR, NAND and NOR Which
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inputs A,B and output Y are assumed as: (a) 0, 2, 4 (b) 1, 2,5,7
Data Input A Logic (c) 2,3,5,7 (d) 0, 2, 4,5
Y (Data Output)
Control/GatingB GATE
input 28. Simplified form of Boolean function,
ABCD ABCD ABC AB C nC is,
Control (Assume n is equal to 2)
Gates : Data Output Y
or (a) AC BA (b) AC AC
AND : A Gating (c) AC AC (d) AC BB
OR : A Input B 29. Find the output Y
NAND: A 0
NOR : A 1
1
For the data output as gives above, which of the
A
following match of Gate with input ‘ B ’ is correct ? 2
(a) AND,1 , OR,0 , NAND,0 , NOR,1 B 5 6 Y
(b) AND,1 , OR,0 , NAND,1 , NOR,0 C
3
(c) AND,0 , OR,1 , NAND,0 , NOR,1 4
(d) AND,0 , OR,0 , NAND,0 , NOR,1
24. Assume 6 variable of inputs are corrected to an Ex- (a) ABC (b) A B C
OR gates, the number of minterms in the Boolean (c) A B C (d) ABC
expression of the output of Ex-OR gate ‘ Y ’will be
30. For the switching circuit shown below, taking open
(a) 16 (b) 32
as ‘0’ and closed as ‘1’, the expression for the cir-
(c) 8 (d) 6
cuit when LED glows is,
25. Which of the following identities for Ex-OR and Ex-
NOR funcitons are NOT true?
(a) A B AB A B
(b) A B AB A B
(c) A A B AB
LED
(d) A A B AB
26. After the simplification of a 3 variable Boolean
funciton, (a) P Q R S
f A, B, C A B AB A C AC we
(b) P QR S
requires
(a) 1- AND and 1-OR gate (c) P QR S
(b) 1-AND and 2-OR gate (d) LED can not glow
(c) 2-AND and 1-OR gate
(d) only 1-AND gate
27. For a Boolean function, Y AB AC , the POS
form is
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5
ANSWER KEY-2
1. (c) 2. (b) 3. (c)
4. (a) 5. (d) 6. (c)
7. (a) 8. (d) 9. (b)
10. (b) 11. (a) 12. (b)
13. (a) 14. (d) 15. (a)
16. (a) 17. (c) 18. (d)
19. (a) 20. (d) 21. (a)
22. (d) 23. (b) 24. (b)
25. (d) 26. (a) 27. (d)
28. (d) 29. (a) 30. (b)
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ELECTRONICS: TRANSISTOR
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. In an n-p-n transistor, the leakage current consists
of [GATE 2001] (c)
(d)
1
1
(a) Electrons moving from the base to the emitter
5. To operate a npn transistor in active region, its
(b) Electrons moving from the collector to the base
(c) Electrons moving from the collector to the emitter-base and collector-base junction respec-
emitter. tively, should be
(d) Electrons moving from the base to the collec- (a) forward biased and reversed biased
tor. (b) forward biased and forward biased
(c) reversed biased and forward biased
2. Which of the following characteristics DOES NOT (d) reversed biased and reversed biased
belong to a common collector transistor amplifer 6. For using a transistor as an amplifier, choose the
? [GATE 1996] correct option regarding the resistance of base-
(a) Low voltage gain emitter RBE and base collector RBC junctions
(b) High current gain.
(a) Both RBE and RBC are very low
(c) High input impedance
(b) Very low RBE and very high RBC
(d) High output impedance
(c) Very high RBE and very low RBC
3. Which of the following statements is correct for a
common emitter amplifier circuit ? (d) Both RBE and RBC are very high
[GATE 2004] 7. The resulting change in the emitter current for
(a) The output is taken from the emitter change in the collector of 2mA with 0.98 is
(b) There is 180o phase shift between input and
[BHU PhD 2017]
output voltages
(a) 1.96ma (b) 2.04mA
(c) There is no phase shift between input and out-
put voltages (c) 2mA (d) 0.98mA
(d) Both p-n junctions are forward biased. 8. Consider the following circuit in which the current
4. A transistor in common base configuration has ra- gain β dc of the transistor is 100. [GATE 2012]
tio of collector current to emitter current and +15 V
ratio of collector current to base current . Which 100 900
of the following is true? [JEST]
(a)
(b)
1
1 100
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Which one of the following correctly represents 10. Consider the circuits shown in Figures (a) and (b)
the load line (collector current IC with respect to below. [NET June. 2015]
collector emitter voltage VCE ) and Q-point of this 2K
circuit ?
10K +
15 mA Q-point 10V
(2V, 13 mA) 10.7V+
(a)
IC (a)
VCC 15V 1K
13 mA Q-point
(2V, 10 mA)
10K +
10V
(b) +
5V
IC
VCC 15V (b)
If the transistors in Figures (a) and (b) have cur-
13 mA rent gain dc of 100 and 10 respectively, then
Q-point they operate in the
(7.5V, 7.5 mA) (a) active region and saturation region respecively
IC
(c) (b) saturation region and active region respectively
VCC 15V (c) saturation region in both cases
(d) active region in both cases
11. The transistor in the given circuit has h fe = 35
13 mA
Q-point and h ie 1000 . If the load resistance
(7.5V, 6.5 mA)
(d) IC R L 1000 , the voltage and current gain are,
respectively. [NET June. 2012]
VCC 15V
V0
9. Calculate the collector voltage (Vc ) of the tran- RL
+
sistor for circuit shown in the figure Vi
(Given 0.96, I CBO 20A,VBE 0.3V ,
RB 100k ,VCC 10V and RC 2.2k )
(a) –35,–35 (b) 35, 35
[GATE 2004]
(c) 35, 0.97 (d) 0.98, 35
VCC 12. The circuit shown below [GATE 2009]
RC
RB VCC
VC R1
C1 T1
C2
V0
R2
R3
(a) 3.78 V (b) 3.82 V
(c) 4.72 V (d) 9.7 V
(a) Is a common-emitter amplifier
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3
(b) Uses a pnp transistor
(c) Is an oscillator
(d) Has a voltage gain less than one Load
R2
13. In the circuit shown be-
7.5V
low, R B = 1k and R C 100 . If the transis-
tor β (h FE ) is 100, the current through RC will be R1 2k
[GATE 2000]
+5V
What will be the ratio of the resistances R2 R1 ,
RB RC
in order to make this circuit function as a source
of constant current, I = 1 mA ?
(a) 4.5 (b) 3.0
(c) 2.5 (d) 2.0
16. For the Silicon transistor shown in the figure be-
(a) 0.43 A low, the value of I B is ?
(b) 50 mA
VEE = –8V
(c) Zero
(d) Oscillating between 0 and 50 mA. RE=2.4k
14. In the following circuit, the value of the common- IE
R B=1.9k
emitter forward current amplification factor for
the transistor is 100 and VBE is 0.7 V. =100
[NET June. 2018] VCC =10V
VC C 20.7V (a) 26.47A (b) 52.94A
(c) 13.235A (d) 30.11A
500k R 1 5 k R 2 17. The operating point (Q) of the npn transistor cir-
Ib Output cuit shown below is consider DC 100 and ne-
Input
glect input resistance at the base)
[HCU PhD 2019}
1K
VCC 10V
The base current IB is R1 10k Rc 1k
(a) 40 A (b) 30 A
(c) 44 A (d) 33 A
R2 5k Re 500k
15. In the transistor circuit shown on the right, assume
that the voltage drop between the base and the
emitter is 0.5V. [TIFR 2016]
(a) 2.11V , 5.26mA (b) 8.20V , 1.20mA
(c) 0.00V , 0.00mA (d) 2.11V , 0.00 mA
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18. What is the DC base current (approximated to (c) VB decrese but Vc increase
nearest integer value in μA ) for the following n -
p - n silicon transistor circuit, given [JEST] (d) VB increases, but Vc decreases
R1 75 , R2 4.0 k , R3 2.1k , 20. All resistors in the circuit on the right have a toler-
R4 2.6 k , R5 6.0 k , ance of 5% . [TIFR 2015]
R6 6.8k , C1 1 F , C2 2 F ,
VC 15 V and β dc 75 +10V
k
C3 R1
300k
R5 C1
R6 R4 R2 k
R3 C2
VC
(a) 20 (b) 24 Assuming a diode drop of 0.7 V, which of the fol-
(c) 16 (d) 32 lowing is the lowest possible value of the collector
19. An n-p-n transistor is connected in a voltage di- voltage ?
vider configuration as shown in the figure below. (a) 3.1 V (b) 4.1 V
[NET June 2019] (c) 4.7 V (d) 5.2 V
21. The circuit depicted on the right has been made
with a silicon n-p-n transistor. [TIFR 2013]
20V
Assuming that there will be a 0.7V drop across a
forward-biased silicon p-n junction, the power
R = 80k
RC = 5k dissipated across the transistor will be, approxi-
C mately,
VCC =15V
=50
B E
R2 = 20k
R L
RE = 1k
V out
Vin 2V
If the resistor R2 is disconnected to the voltage Vg R
at the base and Vc at the collector change as fol-
lows. (a) 53 mW (b) 94 mW
(c) 17 mW (d) 67 mW
(a) both Vg and Vg increse 22. A silicon transistor with built-in voltage 0.7V is
used in the circuit shown, with VBB=9.7V,
(b) both Vb and Vc decrease R B 300k, VCC 12V and R C 2k .
Which of the following figures correctly represents
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5
the load line and the quiescent Q point ?
[NET June. 2013] V CC +9V
RC
V BB R B B
RC
+3V A
+ V
RB CC
VBB + From these measurements it may be inferred that
the
(a) base is open internally
iC (b) emitter is open internally
( A) IB (c) collector resistor is open
32 A
(a) A
(d) base resistor is open
A
Q 24. Common emitter DC current gain of the transistor
is 100. the current through the 10V ener diode
0 9.7 VCE (V)
(assuming VBE of the transistor is 0.7V ) is
iC 20V
(mA) IB
6 A
(b) A
A
Q 10V 10
0 12 VCE (V)
iC (a) 10.7mA (b) 19.3mA
(mA) IB
6 (c) 20mA (d) 40mA
A
A 25. Calculate the collector current and determine
(c) Q A whether or nt the transistor in figure shown below
0 12 VCE (V) is in saturation. Assume VCE sat 0.2V
[JEST 2020]
iC
( A) IB RC = 1k
32 A
Q A RB
(d)
A VCC
10k
VBB OC = 50 10V
0 9.7 VCE (V)
2V
23. In the circuit below the voltages VBB and VCC are
kept fixed, the voltage measured at B is a con- (a) 6.5mA not in saturation
stant, but that measured at A fluctuates between (b) 11.5mA in saturation
(c) 11.5mA not in saturation
a few V to a few mV. [NET Dec. 2017]
(d) 6.5mA in saturation
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26. Analyse the common emitter transistor circuit given NAT
figure. If the current gain increases by 50%, 1. For the transistor amplifier circuit shown below
with
the relative change in collector current I c is ap-
R 1 10kΩ, R 2 10kΩ, R 3 1kΩ, and β = 99 .
proximately [JEST 2020] Negalecting the emitter diode resistance, the input
impedance of the amplifier looking into the base
VCC for small ac signal is ____ kΩ . (up to decimal
places). [GATE 2017]
VCC
IB IC
R1
C
1k B
Vin
Vout
E
(a) 5% (b) 15% R2 R3
(c) 20% (d) 25%
27. A large MOS transistor consists of N individual 2. The current gain of the transistor in the following
transistors connected in parallel. If the only form circuit is β d c 100 . The value of collector current
of noise in each transistor is 1/f noise, then the
IC is _________mA. [GATE 2014]
equivalent voltage noise spectral density for the
MOS transistor is [NET Dec. 2014]
12V
(a) 1 / N times that of a single transistor 3k
F
(b) 1/ N2 times that of a single transistor
V0
150k
(c) N times that of a single transistor i
(d) N2 times that of a single transistor Vi
F
28. You are given the following circuit and two instru-
3k
ments : a voltmeter and an ammeter both with
0.001% accuracy in their readings. 3. The value of emitter current in the given circuit is
[TIFR 2015]
__ A . (Round off to 1 decimal place)
A 10 0.001 B 100 1 C
5V +V CC = 10V
2 4k
Which of the following methods will result in the
most accurate reading for the current without in-
terrupting the current in the circuit ?
C
(a) Use voltmenter to measure voltage across B
points B and C E
0.3V
(b) Use the ammeter to measure current at point +
C
B 2k – E
(c) Use voltmeter to measure voltage across points
A and B
(d) Use voltmeter to measure voltage across points
A and C
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4. For the following circuit, the collector voltage with 7. For the transistor shown in the figure, assume
respect to ground will be ____________V. VBE 0.7V and β dc 100. If Vin 5V, Vout (in
(Emitter diode voltage is 0.7V and DC of the Volts) is _______. (Give your answer upto one
transistor is large) decimal place). [GATE 2016]
(Specify your answer in volts upto one digits after
the decimal point)
10V
10V
3k 3k
Vin
Vout
3k
200k
1k
1k
3V
5. In the circuit given below, the collector to emitter
voltage VCE is ________________ V. (Neglect
VBE , take 100 )
8. In the simple current source shown in the figure,
Q1 and Q2 are identical transistors with current
gain 100 and VBE 0.7V [GATE 2015]
Vcc = +10V
VCC = 30V
5k 5k
5k
I0
VCE
Q1 Q2
5k 10k
The current I0 (in mA is _______(upto two deci-
6. In the given circuit, VCC 10V and 100 for mal places)
the n-p-n transistor. The collector voltage VC (in 9. Consider a saw tooth waveform which rises lin-
volts) is ________________ early from 0 Volt to 1 Volt in 10 ns and then de-
cays linearly to 0V over a period of 100 ns. Find
VCC the r.m.s. Votage in units of milliVolt?
[TIFR 2016]
1K 10. A signal is to be sent from a coaxial cable with
VC impedance 40 into a second coaxial cable with
100K
impedance 60 . We can prevent reflection at
50V the joint between the cables, by adding an imped-
ance in parallel to the second cable. what should
be the value, in units of Ohms , of that im-
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pedance ? [TIFR 2017] ANSWER KEY
11. Conisder the transistor circuit shown in the figure. 1. (a) 2. (d) 3. (d)
4. (a) 5. (a) 6. (b)
Assume VBEQ 0.7V , VBB 6V and the leakage
7. (d) 8. (a) 9. (b)
current is negligible. What is the required value of 10. (b) 11. (a) 12. (d)
RB in kilo-ohms if the base current is to be 4 A 13. (b) 14. (d) 15. (d)
16. (d) 17. (a) 18. (c)
[JEST 2108] 19. (d) 20. (c) 21. (b)
22. (b) 23. (d) 24. (a)
iC 25. (a) 26. (b) 27. (a)
28. (c)
RC
C + NAT
– V CC
RB B
V CE 1. (4.75 to 5.01) 2. (1.4 to 1.7)
3. (443 to 445)
iB
+
V
4. (3.0 to 3.2) 5. (2 to 3)
– BB 6. (5.5 to 5.9)
E
iE 7. (5.5 to 5.9) 8. (5.6 to 5.9)
9. (approx 600)
10. (120) 11. (1325)
12. The circuit shown below contains an unknown 12. (11 to 13)
device X.
100
100
I 2V
The current voltage characteristic of the device X
were determined and are shown in the plot given
below.
20
15
mA
10
0
0 0.5 1.0 1.5 2.0
Volts
Determine the current I (in mA) flowing through
the device X. [TIFR 2016]
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1
ELECTRONICS: DIODE AND ZENER DIODE
CSIR NET-JRF/ GATE/ JEST/ TIFR
PREVIOUS YEARS’ QUESTIONS
1. Which one is true for a p-n junction ? Vin Vout
1k
[BHU PhD 2014]
(a) Junction field is from n to p-side, holes move
3V
from p to n in forward bias, no mobile carriers in
the depletion region
5V
(b) Junction field is from p to n-side, joles, flow
from p to n side in forward bias, no mobile carier (a)
5V
in the depletion region.
(c) Junction field is from p to n-side, holes flow
from n to p side in forward bias, mobile carriers in
5V
the depletion region.
(b)
(d) Junction field is from n to p-side, holes flow
3V
from n to p side in forward bias, immobile carriers
in te depletion region.
2. A p-n junction was formed with a heavily doped
3V
1018
cm 3
p-region and lightly doped (c)
3V
1014
cm 3
n-region. Which of the following
statement(s) is(are) correct ?
(a) the width of the depletion layer will be more in 3V
(d)
n-side of the juncion
(b) the width of the depletion layer will be more in 5V
the p-side of the function
(c) the width of the depletion layer will be same 4. The peak to peak voltage for the following circuit
on both sides of the juncion. containing a Si-based diode is
(d) if the pn juncion is reverse biased, then the [HCU PhD 2019]
2.2k
width of the dipletion region increases.
30V
3. A Sine wave of 5V amplitude is applied at the
input of the circuit shown in the figure. Which of 0V
Vin Vout
the following waveforms represents the output most –30V
12V
closely?
(a) 17.3V (b) 29.3V
(c) 42.7V (d) 47.0V
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5. When an input voltage Vi , of the form shown, is 7. In the following circuit, D1 and D2 are identical
applied to the circuit given below, the output volt- diodes with forward voltage drop of 0.6 Volt and
age V0 is of the form (Si = 0.7V) reverse Breakdown voltage of 5 Volts.
[GATE 2007] [IISc-2011]
R1 D1
+12V 10k
+
12V R2 D2
–
-12V 1k
The current through resistor R2 is approximately
R (a) zero (b) 0.2 mA
Vi V0 (c) 0.7 mA (d) 5 mA
3V 8. Consider the circuit shown in the figure where
Si diode R1 2.07 k and R2 1.93 k . Current
source I delivers 10 mA current. The potential
across the diode D is 0.7 V. What is the potential
12V
at A ? [JEST]
(a) D
A
0V
I R R
12V
(b) 3V
0V
(a) 10.35V (b) 9.65V
12V (c) 19.30V (d) 4.83V
(c) 2.3V 9. In the following silicon diode circuit VB 0.7V ,
0V determine the output voltage waveform Vout for
0V the given input wave. [JEST 2017]
0 /
/
3.5 3.5
(d)
Vin
2.8 2.8
2.1 2.1
-12V 1.4 1.4
0.7 0.7
0.0 0.0
6. In the following circuit, the voltage drop across 0.7 0.7
1.4 1.4
the ideal diode in forward bias condition is 0.7 V. 2.1 2.1
2.8 2.8
The current passing through the diode is 3.5 3.5
0 / /
[GATE 2012] t
0 / /
Vout
3.5 3.5
2.8 2.8
12k 2.1 2.1
1.4 1.4
24V
+ (a) 0.7
0.0
0.7
0.0
0.7 0.7
1.4 1.4
6k 3.3k 2.1 2.1
2.8 2.8
3.5 3.5
0 /
/
t
(a) 0.5 mA (b) 1.0 mA
(c) 1.5 mA (d) 2.0 mA
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3
0 /
/
VPQ
3.5 3.5
Vout
2.8 2.8
2.1 2.1
1.4 1.4
0.7 0.7
0.0 0.0
(b) 0.7 0.7 (a)
1.4 1.4
2.1 2.1
2.8 2.8 t
3.5 3.5
0 /
/
t
VPQ
0 /
/
3.5 3.5
Vo ut
2.8 2.8
2.1 2.1
1.4 1.4 (b)
0.7 0.7
0.0 0.0
(c) 0.7 0.7
1.4 t
1.4
2.1 2.1
2.8 2.8
3.5 3.5
0 /
/
t VPQ
0 /
/
3.5 3.5 (c)
Vo ut
2.8 2.8
2.1 2.1
1.4 1.4
0.7
t
0.7
0.0 0.0
0.7 0.7
(d) 1.4 1.4
2.1 2.1 VPQ
2.8 2.8
3.5 3.5
0 /
/
t
(d)
10. Consider the following circuit with two indentical
Silicon diodes. The input AC voltage waveform t
has the peak voltage VP 2 V as shown
11. Consider the circuit given in the figure. Let the
formed voltage drop across each diode be 0.7V.
Vin The current I (in mA) through the resistor is ____
[GATE 2020]
2V
+10.1V
t 1k
I
R
P
~ R 12. A circuit and the signal applied at its input termi-
Q
nals Vt are shown in figure below. Which one
of the options correctly describes the output wave-
The voltage waveform across PQ will be repre-
sented by form V0 . (Assume all the devices used are ideal)
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4
2V 0
0 C
t Vinput D Voutput –Vm
2V
(c)
–2Vm
2V
2Vm
0 t
(a) Vm
2 V
(d)
0
14. A diode D as shown in the circuit as an i v rela-
0 t tion which can be proximated by
(b)
2 V
v D 2v D , for v D 0
2
iD
0, for v D 0
4V
(c) 1
0 t iD
10V
+
D VD
0 t
(d)
The value of vD in the circuit is:
-4V
[NET Dec. 2012]
13. The signal shown on the left side of the figure be-
low is fed into the circuit shown on the right side.
(a) 1 11 V (b) 8V
Vm (c) 5V (d) 2V
C
A
0 Vin Vin
15. The I-V characteristics of the diode in the circuit is
R
B given by [NET Dec. 2014]
–Vm
(V 0.7) / 500 for V 0.7
If the signal has time period S and teh circuit has I
0 for V 0.7
a natural frequency RC then, in the case when where V is measured in volts and I
S RC ,the steady-state output will resemble. is measured in amperes.
The current I in the circuit is
Vm 1k I
0
(a) 10V
Vm (a) 10.0 mA (b) 9.3 mA
(c) 6.2 mA (d) 6.7 mA
0
(b)
–Vm
16. In the circuit below, D1 and D2 are two silicon
diodes with the same characteristics. If the for-
ward voltage drop of a silicon diode is 0.7 V, then
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5
the value of the current I1 I D1 , is
[NET Dec. 2017]
Input Output
C R L Voltage
Voltage
I1 1k
ID1 I D2
10V D1 D2 V0 Assuming ideal diodes, the peak value of the out-
put voltage across the load resistor RL, is
(a) V p (b) V p 2
(a) 18.6 mA (b) 9.3 mA (c) 2V p (d) 2V p
(c) 13.95 mA (d) 14.65 mA 20. A sinusidal input voltage vin of frequency iis
17. L et I0 be the saturation current, the ideality
fed to the circuit shown in the figure, where C1 >>
factor vF and vR the forward and reverse poten- C2. If vin is the peak value of the input voltage,
then output voltage (vout) is : [GATE 2006]
tials, respectively, for a diode. The ratio RR / RF
of its reverse and forward resistances RR and RF C1
respectively, varies as (In the following kB is C2
Vin Vout
the Boltzmann constant, T is the absolute tem-
perature and q is the charge).
[NET June. 2017] (a) 2vin (b) 2v0 sin ωt
vin
(a) vR exp qvF (b) vF exp qvF (c) 2vin (d) sin ωt
2
vF k BT vR k BT
21. For the rectifier circuit shown in the figure, the
v qv sinusoidal voltage (V1 or V2) at the output of the
(c) vR exp qvF (d) F exp F
transformer has a maximum value of 10V. The
vF k BT vR k BT
load resistance RL is 1kΩ . If Iav is the averge
18. If the reverse bias voltage of a silicon varactor is current through the resistor RL the circuit corre-
increased by a factor of 2, the corresponding tran- sponds to a. [GATE 2005]
sition capacitance [NET Dec. 2015]
V1
(a) increases by a factor of 2
(b) increases by a factor of 2 RL
Vin Vout
(c) decreases by a factor of 2
(d) decreases by a factor of 2
V2
19. A sinusoidal signal with a peak voltage Vp and
average value zero, is an input to the following cir-
cuit. [NET June. 2018] (a) Full wave rectifier with Iav 20 / mA
VP (b) Half wave rectifier with Iav 20 / mA
t
(c) Half wave rectifier with Iav 10 / mA
(d) Full wave rectifier with Iav 10 / mA
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6
22. In the figure given below, the input to the primary
of the transformer is a voltage varying sinusoidally
10
with time. The resistor R is connected to the cen-
tre tap of the secondary. Which one of the follow- 5
ing plots represents the voltage across the resistor
(a) 0
V
R as a function of time? [GATE 2017]
5
10
C 0 1 2 3 4 5
Time (t)
R
10
V
5
(a) 0
(b) 0
V
t
5
V
10
(b) 0 0 1 2 3 4 5
Time (t)
t
V
10
(c) 0
5
t
(c) 0
V
V 5
(d) 0 10
0 1 2 3 4 5
t Time (t)
23. Consider the following circuit [TIFR 2014]
1k
+5V 10
V = 10 sin (2 t)
Vout 5
(d) 0
V
5
Which of the graphs given below is a correct rep- 10
0 1 2 3 4 5
resentation of Vout ? Time (t)
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7
24. A Germainum diode is operated at a temperature
R
of 27°C. The diode terminal voltage is 0.3 V when
the forward current is 10 mA. What is the for-
ward current (in mA) if the terminal voltage is 0.4
RL
V? [JEST]
(a) 477.3 (b) 577.3
(c) 47.73 (d) 57.73
25. Pick the correct statement based on the below (a) 320, 10mA (b) 400, 15mA
circuit. [GATE 2009]
(c) 400, 10mA (d) 320, 15mA
28. Drawing power from a 12V car battery, a
I R S 1k IL 9Vstabilized DC voltage is required to power a
car stereo system, attached to the terminals A and
Vin B as shownin the figure.
15-25V VZ =10V RL
I f a zener di ode i t h r at i ngs V z = 9Vand
IZ Pmax 0.27W , is connected as shown in the fig-
ure, for the above purpose the minimum seires
(a) The maximum Zener current, resistance RS must be
I Z max , when R L 10kΩ is 15mA
(b) The minimum Zener current, RS
A
I Z min , when R L 10kΩ is 5mA 12V RL
Vz = 9V B
(c) With Vin = 20V, I L = I Z , when R L 2kΩ
(d) The power dissipated across the Zener when
R L 10kΩ and Vin = 20Vis 100 mW (a) 111 (b) 103
26. A Zener regulator has an input voltage in the range (c) 100 (d) 97
15V 20V and a load current in the range of 29. Two identical Zener diodes are placed back to
5mA 20mA. If the Zener voltage is 6.8V, the back in series and are connected to a variable DC
value of the series resistor should be power supply. The best representation of the 1-V
characteristics of the circuit is
R2 [NET Dec. 2013]
V0
I
15-20 V 6.8 V
(a) V
(a) 390 (b) 420
(c) 440 (d) 460
27. A 24V 600mW, zener diode is to be used for pro- I
viding a 24V stabilized supply to a variable load.
Assume that for proper zener action, a minimum
V
of 10mA must flow through the zener. If the input (b)
voltage is 32V, what would be the value of R and
the maximum load current
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8
I 12
10
8
i(m A)
V 6
(c) 4
(a) 2
0
0 1 2 3 4 5 6 78
t(s)
I
12
10
8
i(m A)
V
(d) 6
4
(b) 2
0
0 1 2 3 4 5 6 78
t(s)
30. A Zener diode with an operating voltage of 10 V
at 25°C has a positive temperature co-efficient of
0.07% per°C of the operating voltage. The oper- 12
10
ating voltage of this Zener diode at 125 oC is 8
i(m A)
[NET Dec 2017] 6
4
(a) 12.0 V (b) 11.7 V (c) 2
0
0 1 2 3 4 5 6 78
(c) 10.7 V (d) 9.3 V t(s)
31. The figure below shows a voltage regulator utiliz-
ing a Zener diode of breakdown voltage 5V and 12
positive triangular wave input of amplitude 10V. 10
8
i(m A)
[NET Dec. 2011] 6
4
(d) 2
0
0 1 2 3 4 5 6 78
Vi t(s)
i
1K 32. The voltage regulator circuit shown in the figure
has been made with a Zener diode rated at 15V,
200mW. It is required that the circuit should dissi-
12 pate 150 mW power across the fixed load resis-
10 tor RL
8
V i(V)
6
4
2
0
0 1 2 3 4 5 6 78 Vi RL V0
t(s)
For Vi > 5V, the Zener regulates the output volt- For stable operation of this circuit, the input volt-
age by channeling the excess current through it- age Vi must have a range [TIFR 2012]
self. Which of the following wave forms shows (a) 17.5 V to 20.5 V
the current ‘i’ passing through the Zener diode? (b) 15.5 V to 20.5 V
(c) 15.5 V to 22.5 V
(d) 17.5 V to 22.5 V
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33. The figure on the right shows the current-voltage ANSWER KEY
characteristics of a diode over a range of voltage
and current where it is safe to operate the diode. 1. (a) 2. (a, d) 3. (d)
[TIFR 2013] 4. (a) 5. (c) 6. (b)
7. (a) 8. (b) 9. (b)
10. (c) 11. (8) 12. (c)
40 13. (d) 14. (d) 15. (c)
16. (c) 17. (a) 18. (c)
Current (mA)
20
19. (c) 20. (a) 21. (a)
0 22. (a) 23. (b) 24. (a)
25. (c) 26. (a) 27. (d)
-20
28. (c) 29. (c) 30. (c)
-40 31. (a) 32. (a) 33. (b)
10 9 8 7 1 2 3 4
Voltage (V) 34. (9)
15V
When this diode is used in the circuit on the ex-
treme right, the approximate current, in mA,
through the diode will be
(a) 0 (b) 8.3
(c) 16.7 (d) 25
34. A variable power supply (5V 20V) is connected
to a Zener diode specified by a breakdown volt-
age of 10 V (see figure). The ratio of the maxi-
mum power to the minimum power dissipated
across the load resistor is .........
500
5V-20V 1K
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