Unit 4

Microprogrammed Control

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Contents
• Control memory
• Address sequencing
• Computer configuration
• Microinstruction format
• Symbolic microinstructions
• Symbolic micro programs
• Control unit operation
• Design of control unit

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Introduction
1. Control Memory
• The function of the control unit in a digital computer is to initiate
sequences of micro-operations.
• Micro-operations-Series of steps involving processor registers (the
functional or atomic operations of a processor).
• Two ways to generate signals from Control Unit:
1. Hardwired CU: use of conventional logic design techniques
2. Microprogrammed CU: use of microprogram, binary control variables
• In a bus-organized systems, the control signals that specify micro-
operations are groups of bits that select the paths in multiplexers,
decoders, and arithmetic logic units.

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 Fig: Constituent Elements of a Program Execution

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 • A memory that is part of a control unit is referred to as a control
memory.
• Each word of Control Memory or set of micro-operations
occurring at a time –Micro-instruction
• Sequence of micro-instruction- Microprogram (strings of 0's
and 1's)
• Control Memory- ROM or Dynamic
• Reading the contents of one location of control memory at any
instance is nothing but a microinstruction.
• Each output line (data line) of microprogram memory
corresponds to one control signal.
• If the content of the memory cell is 0, no signal and if it is 1,
signal is generated at that instant of time.
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• Computer that employs a microprogrammed control unit will have
two separate memories:
✓ A main memory
✓ A control memory
• The control memory is assumed to be a ROM, within which all
control information is permanently stored.
• The control address register specifies the address of the microinstruction.
• The control data register holds the microinstruction read from memory.
• Microinstruction contains bits for:
1. initiating micro-operations in the processor and
2. determining the address sequence for the control memory.

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Microprogram Sequencer

Fig3.1: Microprogrammed control organization

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Sequencer

• Some times called next address generator-determines the address

sequence that is read from control memory.
• Typical functions:
1. Incrementing the control address register by one
2. Loading an address into the control address register from control memory
3. Transferring an external address
4. Loading an initial address to start the control operations

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Pipeline Register

• Data register sometimes called pipeline register.

• Allow simultaneously:
1. The execution of the micro-operations specified by the control word
2. The generation of the next microinstruction.
• This configuration requires a two-phase clock
• The system can operate by applying a single-phase clock to the address register.
• Without the control data register
• Thus, the control word and next-address information are taken directly from
the control memory.

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• Address sequencer must have capabilities of finding address of next
microinstruction in following situations:
➢In-line Sequencing
➢Unconditional Branch
➢Conditional Branch
➢Subroutine call and return
➢Looping
➢Mapping from instruction op-code to address in control memory.

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2. Address Sequencing
• Microinstructions are stored in control memory in groups, with each
group specifying a routine.
• Process of finding address of next micro-instruction to be executed is
called address sequencing.
• Each computer instruction has its own microprogram routine in
control memory to generate the micro-operations that execute the
instruction.

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 Instruction code

Mapping logic

Status Branch MUX Multiplexers

bits logic Select
Subroutine
register
Control address register (SBR )
(CAR)

Incrementer

Control memory (ROM)

select a status bit

Micro-operations
Branch address

Fig3.2: Selection of address for control memory

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Process of sequencing:
• When power turned on, initial address is loaded into the CAR.
• This address is usually the address of the first microinstruction that activates
the instruction fetch routine.
• The control memory next must go through the routine that determines the
effective address of the operand.
• The next step is to generate the micro-operations that execute the instruction
fetched from memory.
• Mapping process-The transformation from the instruction code bits to
an address in control memory where the routine is located.
• The microinstruction in control memory contains:
➢ a set of bits to initiate micro-operations in computer registers.
➢ Other bits to specify the method by which the next address is obtained.

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• The address sequencing capabilities required in a control memory
are:
a) Incrementing of the control address register.
b) Unconditional branch or conditional branch, depending on
status bit conditions.
c) A mapping process from the bits of the instruction to an address
for control memory.
d) A facility for subroutine call and return.

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Conditional Branch:

• If Condition is true, set the appropriate field of status register to 1.

• Conditions are tested for O (overflow), N (negative), Z (zero), C
(carry), etc.
• Then test the value of that field, if the value is 1 take branch address
from the next address field of the current microinstruction, otherwise
simply increment the address.

Unconditional Branch:
• Fix the value of one status bit at the input of the multiplexer to 1. So
that always branching is done.

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Mapping:
• The transformation of the instruction code bits to an address in control
memory where the routine is located is referred to as a mapping
process.
• A mapping procedure is a rule that transforms the instruction code into
a control memory address.
• Direct mapping:
• Directly use opcode as address of Control memory.

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 Address
OP -codes of Instructions 0000 ADD Routine
ADD 0001 AND Routine
0000
0010 LDA Routine
AND 0001 . 0011 STA Routine
LDA 0010 .. 0100 BUN Routine
STA 0011
BUN 0100 Control
Storage
Another approach of mapping:
• Modify Opcode to use it as an address of control memory.

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 Mapping function implemented by ROM or PLA:
• The opcode is used to address the ROM address where control address is
located and finally the microinstruction address of control memory is
generated through mapping process.
• Mapping generally uses AND operation followed by OR operation.
OP-Code

Mapping memory
( ROM or PLA )

Control address register (CAR)

Control Memory

Fig 3.3: Mapping Function Implemented by ROM and PLD

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Subroutines:
• Subroutines are programs that are used by other routines to accomplish
a particular task.
• Can be called from any point within the main body of the
microprogram.
• Designed/written to ease the program flow and for better
understanding.
• Help in reducing the repetitive coding.
• Microprograms that use subroutines must have a provision for storing
the return address during a subroutine call and restoring that address
during return.
• Organize the registers in a last-in, first-out (LIFO) stack.
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3. Computer Configuration
• The designer generates the microcode for the control memory.
• This code generation is called microprogramming and similar to
conventional machine language programming.
• To illustrate microprogramming we use the block diagram of the
computer as shown below. It consists of two memory units:
➢a main memory for storing instructions and data, and
➢a control memory for storing microprograms
• Four registers are associated with the processor unit and two with the
control unit.

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 Fig 3.4: Computer hardware configuration
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• The processor registers are: • The control unit has:
1. Program counter (PC), 1. Control address register (CAR)
and
2. Address register (AR),
2. Subroutine register (SBR).
3. Data register (DR), and
4. Accumulator register (AC).

• The transfer of information among the registers in the processor is done through
multiplexers rather than a common bus.
• DR can receive information from AC, PC, or memory.
• AR can receive information from PC or DR.
• PC can receive information only from AR.

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• The arithmetic, logic, and shift unit performs microoperations with
data from AC and DR and places the result in AC.
• Memory receives its address from AR.
• Input data written to memory come from DR, and data read from
memory can go only to DR.
• The computer instruction format is depicted in Table1. It consists of
three fields:
a. A 1-bit field for indirect addressing symbolized by I,
b. A 4-bit operation code (opcode),
c. And an 11-bit address field.

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 Fig: Machine instruction format

Table1: Simple Instruction format

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4. Microinstruction format
• The 20 bits of the microinstruction.
• Divided into four functional parts.
• The three fields F1, F2, and F3
specify microoperations for the
computer.
• The CD field selects status bit
conditions.
• The BR field specifies the type of
branch to be used.
• The AD field contains a branch
address.
• The address field is seven bits wide,
since the control memory has 128 =
2^7 words.

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Description of F1, F2, F3

Table2: Description of microoperation fields

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Description of CD

• Description of BR

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5. Symbolic Microinstruction
• The Symbolic Microinstruction are the symbols used in microinstructions as in
assembly language.
• A symbolic microprogram can be translated into its binary equivalent by means
of an assembler.
• Format of Microinstruction:
➢Contains five fields: label; micro-ops; CD; BR; AD
➢Label: may be empty or may specify a symbolic address terminated with a colon (:)
➢Micro-ops: consists of one, two, or three symbols separated by commas
➢CD: one of {U, I, S, Z}, where U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
➢BR: one of {JMP, CALL, RET, MAP}
➢AD: one of {Symbolic address, NEXT, empty (in case of MAP and RET)}
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The Fetch Routine
• The control memory has 128 words, and each word contains 20 bits.
• To microprogram the control memory, it is necessary to determine the
bit values of each of the 128 words.
• The first 64 words (addresses 0 to 63) are to be occupied by the
routines for the 16 instructions.
• The last 64 words may be used for any other purpose.
• A convenient starting location for the fetch routine is address 64.

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The Fetch Routine (cont.)
• Sequence of microoperations in the fetch cycle:
1. AR PC
2. DR  M[AR], PC  PC + 1
3. AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6) 0
• The fetch routine needs three microinstructions, which are placed in
control memory at addresses 64, 65, and 66.
• Symbolic microprogram for the fetch cycle:
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

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The Fetch Routine (cont.)
• Binary equivalents translated by an assembler

Table3: Binary word generation

Binary Address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000

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6. Symbolic microprogram
• The execution of the microinstruction in the fetch routine with branch
results to address OxxxxOO, where xxxx are the four bits of the
operation code.
• For example, if the instruction is an ADD instruction whose operation
code is 0000, the microinstruction will transfer to CAR the address
0000000, which is the start address for the ADD routine in control
memory.
• The first address for the BRANCH and STORE routines are 0 0001 00
(decimal 4) and 0 0010 00 (decimal 8), respectively.
• The first address for the other 13 routines are at address values 12, 16,
20, ... , 60.
• This gives four words in control memory for each routine.

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• In each routine we must
provide microinstructions
for evaluating the
effective address and for
executing the instruction.

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Binary Microinstruction

• The symbolic microprogram is a convenient form for writing

microprograms in a way that people can read and understand.
• But this is not the way that the microprogram is stored in memory.
• The symbolic microprogram must be translated to binary either by
means of an assembler program or by the user if the microprogram is
simple enough as in this example.

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7. Design of Control Unit
• The bits of the microinstruction are usually divided into fields, with
each field defining a distinct, separate function.
• The various fields encountered in instruction formats provide:
✓Control bits to initiate microoperations in the system
✓Special bits to specify the way that the next address is to be evaluated
✓An address field for branching .
• The number of control bits that initiate microoperations can be
reduced by grouping mutually exclusive variables into fields by
encoding the k bits in each field to provide 2k microoperations.

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• Each field requires a decoder to produce the corresponding control
signals.
o Reduces the size of the microinstruction bits.
o Requires additional hardware external to the control memory.
o Increases the delay time of the control signals.

F Field Decoding
• Three microoperation fields need 3 decoders.
• Each of the three fields of the microinstruction presently available in the
output of control memory are decoded with a 3 x 8 decoder to provide eight
outputs.
• Each of these outputs must be connected to the proper circuit to initiate the
corresponding microoperation.

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12/18/2025 Fig 3.9: Decoding of microoperation fields
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• For example, when F1 = 101 (binary 5), the next clock pulse transition
transfers the content of DR (0-10) to AR (symbolized by DRTAR in Table2.
• Similarly, when F1 = 110 (binary 6) there is a transfer from PC to AR
(symbolized by PCTAR).
• Outputs 5 and 6 of decoder F1 are connected to the load input of AR so that
when either one of these outputs is active, information from the
multiplexers is transferred to AR.
• The multiplexers select the information from DR when output 5 is active
and from PC when output 5 is inactive.
• The transfer into AR occurs with a clock pulse transition only when output
5 or output 6 of the decoder are active.
• The other outputs of the decoders that initiate transfers between registers
must be connected in a similar fashion.
• The other outputs of the decoders that are associated with an AC operation
must also be connected to the arithmetic logic shift unit in a similar fashion.

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Microprogram Sequencer

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• The basic components of a microprogrammed control unit are the
control memory and the circuits that select the next address.
• The address selection part is called a microprogram sequencer.
• A microprogram sequencer can be constructed with digital functions to
suit a particular application.
• To guarantee a wide range of acceptability, an integrated circuit
sequencer must provide an internal organization that can be adapted to
a wide range of application.
• The purpose of a microprogram sequencer is to present an address to
the control memory so that a microinstruction may be read and
executed.

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 1

Fig 3.10: Micro program Sequencer

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Components and Working:
• The control memory is included to show the interaction between the
sequencer and the different units attached to it.
• Two multiplexers:
1. MuX1-selects an address from one of the four sources and routes to CAR,
• In-Line Sequencing  CAR + 1
• Branch, Subroutine Call  Take address from AD field
• Return from Subroutine  Output of SBR
• New Machine instruction  MAP

2. Mux2-tests the value of the selected status bit and result is applied to an input
logic circuit.

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 • MUX-2 Controls the condition and branching as below:

Design of Input Logic:

• The input logic in a particular sequencer will determine the type of
operations that are available in the unit.
• Typical sequencer operations are: increment, branch or jump, call and
return from subroutine, load an external address, push or pop the stack,
and other address sequencing operations.

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• Based on the function listed in each entry, the truth table for the input logic circuit
is shown in Table below.
Table5: Input logic truth table for microprogram sequencer

• The bit values for S1 and S0 are determined from the stated function and the path
in the multiplexer that establishes the required transfer.
• Note that the incrementer circuit in the sequencer of Fig.4.10 is not a counter
constructed with flip-flops but rather a combinational circuit constructed with
gates.
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