I.
Foundational Concepts and History
A microprocessor (MP) is the central processing unit (CPU) of a computer, built on a single integrated circuit
(IC) chip. It acts as the "brain of the computer," performing basic operations such as arithmetic (addition,
subtraction), logic (AND, OR), data transfer, and control functions.
Historical Context
Computing evolved through several eras:
Mechanical Age (Before 1940s): Used devices like the Abacus and Pascal’s Calculator (1642). Charles
Babbage’s Analytical Engine (1837) introduced the concept of input, memory ("store"), processing unit
("mill"), and output. These systems were slow and bulky.
Electrical Age (1940s–1960s): Utilized electrical circuits and vacuum tubes, leading to machines like ENIAC
(1945). Transistors (1947) later replaced tubes, making computers faster, smaller, and more reliable.
Microprocessor Age (1970s–Present): Began with the invention of the Intel 4004 (1971), placing the entire
CPU on a single chip. This led to the growth of cost-effective personal computers (PCs).
Early processors included the 4-bit 4004/4040, the 8-bit 8008/8080/8085, and the 16-bit 8086/8088.
Computer Architecture and Execution
Most modern computers follow the Von Neumann Architecture, which defines the system components: the
Central Processing Unit (CPU), Memory Unit, Input Unit, Output Unit, and System Bus (Data, Address, Control).
The fundamental operation of the CPU is the Fetch-Decode-Execute Cycle:
1. Fetch: Instruction is retrieved from memory.
2. Decode: The Control Unit interprets the instruction.
3. Execute: The ALU/Registers perform the required operation.
4. Store: The result is written back to memory or output.
CPU Design Types:
Feature CISC (Complex Instruction Set RISC (Reduced Instruction Set
Computer) Computer)
Instruction Set Large & complex (e.g., Intel x86) Small & simple (e.g., ARM, MIPS)
Instruction Variable Fixed
Length
Execution Time Multiple cycles Usually 1 cycle
Pipelining is a technique used in processors where instruction execution is divided into stages, allowing
multiple instructions to be processed simultaneously to improve performance.
II. 8086 Microprocessor Architecture and Registers
The Intel 8086 is a 16-bit processor with a 16-bit internal ALU and registers. It uses a 16-bit data bus and a
20-bit address bus, allowing it to address up to 2²⁰ = 1 MB of memory. The internal architecture is divided into
two main, independently operating units:
1. Bus Interface Unit (BIU): Handles all communication with memory and I/O.
Responsibilities: Fetches instructions, reads/writes data, queues instructions, and generates 20-bit
physical addresses.
Components: Instruction Queue (for pipelining), Segment Registers (CS, DS, SS, ES), Instruction Pointer
(IP), and Address Adder.
2. Execution Unit (EU): Responsible for decoding and executing the instructions.
Responsibilities: Decodes fetched instructions and executes them using the ALU. It does not access
memory directly.
Components: ALU, General-purpose registers, Pointer and Index registers, and the Flag Register.
8086 Register Organization (16-bit)
Register Group Registers Function/Role
General AX (Accumulator): AL (low Arithmetic, logic, I/O operations.
Purpose byte), AH (high byte)
BX (Base): BL, BH Memory addressing (base addressing).
CX (Count): CL, CH Used for loops, shifts, and rotations.
DX (Data): DL, DH Used in multiplication/division and I/O
operations.
Segment CS (Code Segment) Holds the base address of the program
Registers codes/instructions.
DS (Data Segment) Holds the base address of variables and
arrays.
SS (Stack Segment) Holds the base address of the stack
(temporary data).
ES (Extra Segment) Used for storing extra data, often for
string operations.
Pointer/Index SP (Stack Pointer) Used with SS; points to the top of the
stack.
BP (Base Pointer) Used with SS; often accesses
parameters/variables on the stack.
SI (Source Index) Used with DS; holds the source address
for string operations.
DI (Destination Index) Used with ES; holds the destination
address for string operations.
Special Purpose IP (Instruction Pointer) Always used by the BIU to address the
offset of the next instruction.
The Flag Register
The 16-bit Flag Register holds two types of flags:
1. Conditional (Status) Flags: Reflect the outcome of arithmetic or logical operations:
CF (Carry Flag): Set (1) if the result overflows from the Most Significant Bit (MSB, D7 or D15).
PF (Parity Flag): Set (1) if the lower byte of the result contains an even number of ones.
AF (Auxiliary Carry Flag): Set (1) if a carry occurs from bit D3 to bit D4, typically used in BCD
arithmetic.
ZF (Zero Flag): Set (1) if the total result of the operation is zero.
SF (Sign Flag): Set (1) if the MSB (D7 or D15) of the result is 1, indicating a negative number in signed
magnitude format.
OF (Overflow Flag): Set (1) to detect errors in signed number arithmetic, such as when the result
overflows into the sign bit (D15).
2. Control Flags: Control the operations of the execution unit:
TF (Trap Flag): If TF = 1, the processor enters Single-Step mode, executing only one instruction at a
time, which is used for debugging.
IF (Interrupt Flag): Used to enable (IF=1) or disable (IF=0) interrupts that the processor can choose to
ignore or accept.
DF (Direction Flag): Controls string operations. If DF=0, index registers (SI/DI) are incremented (lower
address to higher). If DF=1, index registers are decremented (higher address to lower).
III. Memory Segmentation
Segmentation was designed to allow the 16-bit 8086 processor to access the full 1 MB (2²⁰) of memory, despite
its 16-bit register limitation (which can only address 64 KB, or 2¹⁶).
Physical Address Calculation: The 20-bit Physical Address (PA) is generated by combining a 16-bit Segment
Register value with a 16-bit Offset Register value.
Physical Address = (Segment Register × 16) + Of f set
The segment register value is multiplied by 16 (or shifted left by 4 bits) to convert the 16-bit base address
into a 20-bit address, defining the start of a 64 KB memory block.
The offset register gives the exact location within that 64 KB block.
IV. Addressing Modes
An addressing mode defines the method an instruction uses to identify the location of its data (operands).
Operands must have similar widths (byte or word). Importantly, the 8086 does not allow memory-to-memory
operations.
The 8086 addressing modes are categorized into three main types:
1. Register Addressing Mode: Both the source and destination operands are located inside internal registers
(reg16, reg8, or Sreg).
Rule: The Code Segment (CS) register cannot be specified as a destination operand. Data transfer
between segment registers must be performed via a general-purpose register (e.g., MOV AX, CS then
MOV DS, AX ).
2. Immediate Addressing Mode: The data (operand) is given directly within the instruction itself as a constant
value.
Format: MOV destination, immediate_data .
Rule: Segment registers cannot receive immediate data directly; they must receive data from general-
purpose registers.
3. Memory Addressing Mode: The operand (data) is stored in memory. Access requires calculating the
Physical Address (PA) using the Segment Base Address (SBA) and the Effective Address (EA):
PA = SBA + EA
The Effective Address (EA) is the offset (distance) from the start of the memory segment. The EA is often
calculated using a formula that accommodates simple variables, arrays, and tables:
EA = Base (BX or BP) + Index (SI or DI) + Displacement (Constant)
Direct Addressing Mode is a specific form of Memory Addressing where the Effective Address (EA) is given
explicitly as a constant displacement directly in the instruction.
The complexity of the 8086 memory system and its flags can be visualized like a highly organized library card
catalog. The Segment Register is like the main index card identifying the specific 64 KB section of the library
(Code, Data, Stack), while the Offset Register (EA) is the exact book call number, telling you precisely where
the data (the word or byte) is located within that section. The Flag Register acts like a small digital scoreboard,
instantly reporting the success, failure, or characteristics (zero result, negative sign, memory overflow) of the
last operation performed by the processor.