3–1 DATA ADDRESSING MODES
• MOV instruction is a common and flexible
instruction.
– provides a basis for explanation of data-
addressing modes
• Figure 3–1 illustrates the MOV instruction and
defines the direction of data flow.
• Source is to the right and destination the left,
next to the opcode MOV.
– an opcode, or operation code, tells the
microprocessor which operation to perform
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Figure 3–1 The MOV instruction showing the source,
destination, and direction of data flow.
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Figure 3–2 8086–Core2 data-addressing modes.
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Register Addressing
• The most common form of data addressing.
– once register names learned, easiest to apply.
• The microprocessor contains these 8-bit
register names used with register addressing:
AH, AL, BH, BL, CH, CL, DH, and DL.
• 16-bit register names: AX, BX, CX, DX, SP,
BP, SI, and DI.
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Figure 3–3 The effect of executing the MOV BX, CX instruction at the point
just before the BX register changes. Note that only the rightmost 16 bits of
register EBX change.
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Immediate Addressing
• Term immediate implies that data immediately
follow the hexadecimal opcode in the memory.
– immediate data are constant data
– data transferred from a register or memory
location are variable data
• Immediate addressing operates upon a byte or
word of data.
• Figure 3–4 shows the operation of a MOV
EAX,13456H instruction.
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Figure 3–4 The operation of the MOV EAX,13456H instruction.
This instruction copies the immediate data (13456H) into EAX.
• As with the MOV instruction illustrated in
Figure 3–3, the source data overwrites the
destination data.
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Direct Data Addressing
• Applied to many instructions in a typical
program.
• Two basic forms of direct data addressing:
– direct addressing, which applies to a MOV
between a memory location and AL, AX, or EAX
– displacement addressing, which applies to almost
any instruction in the instruction set
• Address is formed by adding the displacement
to the default data segment address or an
alternate segment address.
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Direct Addressing
• Direct addressing with a MOV instruction
transfers data between a memory location,
located within the data segment, and the AL
(8-bit), AX (16-bit), or EAX (32-bit) register.
– usually a 3-byte long instruction
• MOV AL,DATA loads AL from the data
segment memory location DATA (1234H).
– DATA is a symbolic memory location, while
1234H is the actual hexadecimal location
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Figure 3–5 The operation of the MOV AL,[1234H] instruction when
DS=1000H .
• This instruction transfers a copy contents of
memory location 11234H into AL.
– the effective address is formed by adding
1234H (the offset address) and 10000H
(the data segment address of 1000H times
10H) in a system operating in the real mode
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Displacement Addressing
• Almost identical to direct addressing, except
the instruction is 4 bytes wide instead of 3.
• In 80386 through Pentium 4, this instruction
can be up to 7 bytes wide if a 32-bit register
and a 32-bit displacement are specified.
• This type of direct data addressing is much
more flexible because most instructions use it.
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Register Indirect Addressing
• Allows data to be addressed at any memory
location through an offset address held in any
of the following registers: BP, BX, DI, and SI.
• In addition, 80386 and above allow register
indirect addressing with any extended register
except ESP.
• In the 64-bit mode, the segment registers
serve no purpose in addressing a location
in the flat model.
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Figure 3–6 The operation of the MOV AX, [BX] instruction when BX = 1000H and DS
= 0100H. Note that this instruction is shown after the contents of memory are
transferred to AX.
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Base-Plus-Index (索引、註標)
Addressing
• Similar to indirect addressing because it
indirectly addresses memory data.
• The base register often holds the beginning
location of a memory array.
– the index register holds the relative position
of an element in the array
– whenever BP addresses memory data, both the
stack segment register and BP generate the
effective address
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Locating Data with Base-Plus-Index
Addressing
• Figure 3–8 shows how data are addressed by
the MOV DX, [BX + DI] instruction when the
microprocessor operates in the real mode.
• The Intel assembler requires this addressing
mode appear as [BX][DI] instead of [BX + DI].
• The MOV DX, [BX + DI] instruction is MOV
DX,[BX][DI] for a program written for the Intel
ASM assembler.
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Figure 3–8 An example showing how the base-plus-index addressing mode
functions for the MOV DX, [BX + DI] instruction. Notice that memory address
02010H is accessed because DS=0100H, BX=1000H and DI=0010H.
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Register Relative Addressing
• Similar to base-plus-index addressing and
displacement addressing.
– data in a segment of memory are addressed by
adding the displacement to the contents of a base
or an index register (BP, BX, DI, or SI)
• Figure 3–10 shows the operation of the MOV
AX,[BX+1000H] instruction.
• A real mode segment is 64K bytes long.
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Figure 3–10 The operation of the MOV AX, [BX+1000H]
instruction, when BX=0100H and DS=0200H .
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Base Relative-Plus-Index
Addressing
• Similar to base-plus-index addressing.
– adds a displacement
– uses a base register and an index register to
form the memory address
• This type of addressing mode often addresses
a two-dimensional array of memory data.
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Addressing Data with Base
Relative-Plus-Index
• Least-used addressing mode.
• Figure 3–12 shows how data are referenced if
the instruction executed by the microprocessor
is MOV AX, [BX + SI + 100H].
– displacement of 100H adds to BX and SI to form
the offset address within the data segment
• This addressing mode is too complex for
frequent use in programming.
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Figure 3–12 An example of base relative-plus-index addressing using a MOV
AX,[BX+SI+0100H] instruction. Note: DS=1000H,BX=0020H,SI=0010H
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Scaled-Index Addressing
• Unique to 80386 - Core2 microprocessors.
– uses two 32-bit registers (a base register and
an index register) to access the memory
• The second register (index) is multiplied by a scaling factor.
– the scaling factor can be 1x(For Byte Size data), 2x(For
Word data), 4x(Double Word data), 8x(Quad Word or 64
bit data)
• A scaling factor of 1x is implied and need not be included in
the assembly language instruction (MOV AL, [EBX + ECX]).
OR (MOV AL, [EBX + 1x ECX]) is equal meaning but first is
written for programming instruction.
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RISC Architecture:
• Simplified Instructions: Uses a small, highly
optimized set of simple instructions.
• Fixed-Length Instructions: Instructions are
of uniform length, simplifying decoding.
• Load-Store Architecture: Only load and
store instructions access memory;
arithmetic/logic operations use registers.
• Hardwired Control Unit: Uses hardwired
logic for instruction execution, improving
speed.
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RISC Architecture
• Pipelining Friendly: Simple instructions allow
efficient pipelining, enhancing performance.
• More Registers: Typically has a larger
number of registers to reduce memory access.
• Single-Cycle Execution: Most instructions
execute in a single clock cycle.
• Compiler-Dependent: Relies on compilers to
optimize instruction sequences.
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CISC Architecture:
• Complex Instructions: Supports a large set
of complex, multi-step instructions.
• Variable-Length Instructions: Instructions
vary in length, allowing compact code.
• Memory-Based Operations: Permits
arithmetic/logic operations directly on memory
(not just registers).
• Microprogrammed Control Unit: Uses
microcode to interpret complex instructions,
adding flexibility.
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CISC Architecture:
• Less Pipelining Friendly: Complex
instructions can hinder efficient pipelining.
• Fewer Registers: Typically has fewer
registers, relying more on memory access.
• Multi-Cycle Execution: Many instructions
require multiple clock cycles.
• Hardware-Dependent: Hardware handles
complexity, reducing burden on compilers.
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Key Differences:
• RISC prioritizes speed and simplicity,
while CISC focuses on reducing code size and
hardware complexity.
• RISC is common in modern processors (e.g.,
ARM, MIPS), whereas CISC is traditional
(e.g., x86).
• Hybrid designs (e.g., x86-64) now incorporate
RISC-like features for performance.
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