What is Static Timing Analysis?

Static Timing Analysis (also referred as STA) is one of the many techniques available
to verify the timing of a digital design. An alternate approach used to verify the timing is
the timing simulation which can verify the functionality as well as the timing of the design.
The term timing analysis is used to refer to either of these two methods - static timing
analysis, or the timing simulation. Thus, timing analysis simply refers to the analysis of
the design for timing issues.
The STA is static since the analysis of the design is carried out statically and does not
depend upon the data values being applied at the input pins. This is in contrast to
simulation based timing analysis where a stimulus is applied on input signals, resulting
behavior is observed and verified, then time is advanced with new input stimulus applied,
and the new behavior is observed and verified and so on.

Why Static Timing Analysis?

Static timing analysis is a complete and exhaustive verification of all timing checks of a
design. Other timing analysis methods such as simulation can only verify the portions of
the design that get exercised by stimulus. Verification through timing simulation is only
as exhaustive as the test vectors used. To simulate and verify all timing conditions of a
design with 10-100 million gates is very slow and the timing cannot be verified
completely. Thus, it is very difficult to do exhaustive verification through simulation.
Static timing analysis on the other hand provides a faster and simpler way of checking
and analyzing all the timing paths in a design for any timing violations. Given the
complexity of present day ASICs4, which may contain 10 to 100 million gates, the static
timing analysis has become a necessity to exhaustively verify the timing of a design.
Crosstalk and Noise The design functionality and its performance can be limited by noise.
The noise occurs due to crosstalk with other signals or due to noise on primary inputs or
the power supply. The noise impact can limit the frequency of

Timing Arcs and Unateness

Every cell has multiple timing arcs. For example, a combinational logic cell, such as and,
or, nand, nor, adder cell, has timing arcs from each input to each output of the cell.
Sequential cells such as flip-flops have timing arcs from the clock to the outputs and
timing constraints for the data pins with respect to the clock. Each timing arc has a timing
sense, that is, how the output changes for different types of transitions on input. The
timing arc is positive unate if a rising transition on an input causes the output to rise (or
not to change) and a falling transition on an input causes the output to fall (or not to
change). For example, the timing arcs for and and or type cells are positive unate. See
Figure 2-17(a).
A negative unate timing arc is one where a rising transition on an input causes the output
to have a falling transition (or not to change) and a fall- ing transition on an input causes
the output to have a rising transition (or not to change). For example, the timing arcs for
nand and nor type cells are negative unate. See Figure 2-17(b). In a non-unate timing arc,
the output transition cannot be determined solely from the direction of change of an input
but also depends upon the state of the other inputs. For example, the timing arcs in an xor
cell (exclusive-or) are non-unate.1 See Figure 2-17(c). Unateness is important for timing
as it specifies how the edges (transitions) can propagate through a cell and how they
appear at the output of the cell. One can take advantage of the non-unateness property of
a timing arc, such as when an xor cell is used, to invert the polarity of a clock. See the
example in Figure 2-18. If input POLCTRL is a logic-0, the clock DDRCLK on output of the
cell UXOR0 has the same polarity as the input clock MEMCLK. If POLCTRL is a logic-1, the
clock on the output of the cell UXOR0 has the opposite polarity as the input clock MEMCLK.

Min and Max Timing Paths

The total delay for the logic to propagate through a logic path is referred to as the path
delay. This corresponds to the sum of the delays through the various logic cells and nets
along the path. In general, there are multiple paths through which the logic can propagate
to the required destination point. The actual path taken depends upon the state of the
other inputs along the logic path. An example is illustrated in Figure 2-19. Since there are
multiple paths to the destination, the maximum and minimum timing to the destination
points can be obtained. The paths corresponding to the maximum timing and minimum
timing are referred to as the max path and min path respectively. A max path between
two end points is the path with the largest delay (also referred to as the longest path).
Similarly, a min path is the path with the smallest delay (also referred to as the shortest
path).
Note that the longest and shortest refer to the cumulative delay of the path, not to the
number of cells in the path. Figure 2-19 shows an example of a data path between flip-
flops. A max path between flip-flops UFF1 and UFF3 is assumed to be the one that goes
through UNAND0, UBUF2, UOR2 and UNAND6 cells. A min path between the flip-flops
UFF1 and UFF3 is assumed to be the one that goes through the UOR4 and UNAND6 cells.
Note that in this example, the max and min are with reference to the destination point
which is the D pin of the flip-flop UFF3. A max path is often called a late path, while a min
path is often called an early path.

one of the flip-flops launches the data and the other flip-flop captures the data. In this
case, since UFF1 launches the data, UFF1 is referred to as the launch flip-flop. And since
UFF3 captures the data, UFF3 is referred to as the capture flip-flop. Notice that the launch
and capture terminology are always with reference to a flip-flop-to-flip-flop path. For
example, UFF3 would become a launch flip-flop for the path to whatever flip-flop captures
the data produced by UFF3.
Clock Domains

In synchronous logic design, a periodic clock signal latches the new data computed into
the flip-flops. The new data inputs are based upon the flipflop values from a previous
clock cycle. The latched data thus gets used for computing the data for the next clock
cycle. A clock typically feeds a number of flip-flops. The set of flip-flops being fed by one
clock is called its clock domain. In a typical design, there may be more than one clock
domain. For example, 200 flip-flopsmay be clocked by USBCLK and 1000 flip-flops may
be fed by clock MEMCLK. Figure 2-20 depicts the flip-flops along with the clocks. In this
example, we say that there are two clock domains.

A question of interest is whether the clock domains are related or independent of each
other. The answer depends on whether there are any data paths that start from one clock
domain and end in the other clock domain. If there are no such paths, we can safely say
that the two clock domains are independent of each other. This means that there is no
timing path that starts from one clock domain and ends in the other clock domain.

If indeed there are data paths that cross between clock domains (see Figure 2-21), a
decision has to be made as to whether the paths are real or not. An example of a real path
is a flip-flop with a 2x speed clock driving into a flipflop with a 1x speed clock. An example
of a false path is where the designer has explicitly placed clock synchronizer logic
between the two clock domains. In this case, even though there appears to be a timing
path from one clock domain to the next, it is not a real timing path since the data is not
constrained to propagate through the synchronizer logic in one clock cycle.
Such a path is referred to as a false path - not real - because the clock synchronizer
ensures that the data passes correctly from one domain to the next. False paths between
clock domains can be specified using the set_false_path specification, such as:
set_false_path -from [get_clocks USBCLK] \
-to [get_clocks MEMCLK]
Even though it is not depicted in Figure 2-21, a clock domain crossing can occur both
ways, from USBCLK clock domain to MEMCLK clock domain, and from MEMCLK clock
domain to USBCLK clock domain. Both scenarios need to be understood and handled
properly in STA. What is the reason to discuss paths between clock domains? Typically a
design has a large number of clocks and there can be a myriad number of paths between
the clock domains. Identifying which clock domain crossings are real and which clock
crossings are not real is an important part of the timing verification effort. This enables
the designer to focus on validating only the real timing paths. Figure 2-22 shows another
example of clock domains. A multiplexer selects a clock source - it is either one or the
other depending on the mode of operation of the design. There is only one clock domain,
but two clocks, and these two clocks are said to be mutually-exclusive, as only one clock
is active at one time. Thus, in this example, it is important to note that there can never be
a path between the two clock domains for USBCLK and USBCLKx2 (assuming that the
multiplexer control is static and that such paths do not exist elsewhere in the design).
PROBLEM:
1. Consider the following circuit

What is the Unateness of output pin Y with respect to the input pin B?

Case – 1: keep A = 0, C = 0 and B is changing from 0 → 1. You see no change in the

output y from truth table.
Case – 2: keep A = 0, C = 0 and B is changing from 1 → 0. You see no change in the
output y from truth table.
Case – 3: keep A = 0, C = 1 and B is changing from 0 → 1. You see 0 → 1 in the
output y from truth table.
Case – 4: keep A = 0, C = 1 and B is changing from 1 → 0. You see 1 → 0 in the
output y from truth table.
Similarly, you can check for four other cases and find that output pin Y is of positive
unate with respect to pin B.

2. Consider the given logic circuit. Find the rise and fall delays of the timing path from
input to output.

The rise and fall delays of the gates are as follows

Solution:
trise = trise(inv) + tfall(nor) + trise(nand) = 2 + 3 + 5 = 10ns
tfall = tfall(inv) + trise(nor) + tfall(nand) = 2 + 2 + 4 = 8ns
3. Consider the following logic circuit. Delays of logic gates are tnor = 1.5ns, tinv = 1ns,
tor = 2ns, tand = 1.5ns and tmux = 2.5ns.

Solution:

X = (𝐷̅+𝐶).𝐶 = 𝐶𝐷̅+𝐶 = 𝐶(𝐷̅+1) = C.

The value at point x in the circuit does not depend on D, So the inverter doesn’t need
to be considered in the critical path delay.
Tcritical = tor + tand + tinv + tmux + tnor + tmux = 2 + 1.5 + 1.5 + 2.5 + 1.5 + 2.5 =
11.5ns