Module - 5.
Verlog Sehavieral deseriptior:
Foct s:
ibe
Descvibe the system by shoulng how the outpot
bèlave
aecovding to c hanger the inpfs in
In this descrip tion we do hot need t kno
the logie diagan of the system ; what must
be knoun tr the Lo ootrut behaver in
responce to change in the fnpot
VHDL, aer
ProcesS,
behavteral statenet is
I, Verlog,
- metr
aior bet aviere derertion state
re aways and stial
styuctur of vertl.g beavtsral dercriptton:
medule baf-add
input T, I2j
outpot l, 2;
Yeq l, o2j
Siyc e O,O2 ave eutputt, they
shod be dec lared
decared
always CI, T)
begin
Os t, BI, ;I| stateet 2
above tw stateentr are Signaf
ssignment statementr onitr defaja
is the Verilog behavioval stateme
all verileg statemnents fnstde alayr are
treated as Contur ret.
ay sign al that deelared ootpot
should alro be detared Yeg.
Variable
tsegnent stateet:
Varb : Procesr Cti)
Variable terni, temp : bit ;
(This ir a Variable
Wariable declaratton statement)
begon
sts : tenp1: ti;
st4 temp 2:= het tenp 1;
vartalle asstqomet statement)
sts S1 2= tenp
StG S2
23 temp 2j
end
Pyocess;
The assigoet statement operator is :
if ti acquires Value of 1 t Ti,
then ometarily tep I |
For stateme sts ond sts, Si aCqores
the value of tenp & S2 a cures the
Vadoe of tenp 2.
2 Sequental statements:
t There Qe Several stateroetr drrociated
rth behavtoral desertption S.s. Tere statement
have to appear in side alays or înttial in
Verog
) statement :
s a sequeatia! statement that appeas
in sode always or initial o veriloq.
Versbg TE Fovmat:
f (Boolean expression)
begin
statemet 1;
s tateent 2j
end
else
begin
ctatement aj
stateent b;
statersent c;
End
The exeotion of it ir contlled by the
boolean exprer ston . Df the Boolean exp resston
is true, then statergents 4, 2, 3 --- a r e execut
tf the esprecen. is fa•se,, statement a, b, c
exeeuted.
if (clk = )
temp = Si
elre
if dk
temp
ir bigh Cy. then the Valoe of s &s
ck
aSsigned to vetiable teP, otherJise ,S
is asstg ned to vartable tenp.
temf
The else statemet Can be eliminat ed,
in thrs Case the it stafeent Simoater
Lateh.
Exeeution of c£ qs lateh :
Ver:log :
f Cclk = )
begin
end
Df dk ë bigh, they the value of s is
ir not high, tep
arsiqmed to tenp. [Link] is
retainr itr curent Yalue, thor Sigulating
fatch
Ey eotion ot
of F as ELSE -LF:
Verileg :
if ( Boolean esprerrod)
beginstatement 1; statement 2;
end
else f (Boolean esprerslon 2)
begin
continoed
statemeat 1; statement1;
end
efre
begh
statement a; statenent b;
end
if Csgnof l = )
temp Si;
elre if C signal2 = )=)
tengp S2;
else
temp S3;
Signal 1 Signay 2 temp =
S3
S2
S
Table. votput siqnals (temp) for else -if
stateret
Verdeg Behovio vad desrption f Muutelexers:
2:1 MUx;
Gar
2:1 MUX
Sel
modue CA, B, Sel, GLar, y);
inpot A, B, Sel, Gbari
Butput
Teg y
aloyr (se A,6, Gbar)
begtn
(Glar
e<se
begin
else
eadedole
4 1 MUX
4 1
MUX
So
yodole Ca, b, , So, si, y))
input a, b, <, di
inpot So, Sj
eg yj
alway s e Ca,b, c, d, So
so, Si)
begiy
case C so) S)
2'Llo
2'b
end Ceye
enamodule
Leop state ment: that har te
Stqvent: <tatement
or inbi
intide alwayr oy vertlog.
Lap is wred to ree eat the execution ef
statementr Jritten nside 1rbody.
The lbop allows code t be shortened.
For loop:
Gyenta format s
for lower inden valse y <upper tnden valuey
statementr 1;: stateme 2 ; stotement 3 --
Lstep?
x Lf the Value of index is betueen lower
and pPer , alu staterentr wtten tnside the
body ef the loop are exeete.
the Vaoe f index is not bteen the
lower and wpper vefoes, the loop is termnf
Ex;
[Link] Ctenp
CiJ=)
begin
resot = rcrutt 2*i:
end
end
statemeut 1j stateme a
dhie loop:
Ghural fornat
while Ccondition)
stateent +j
staterent 2;
As long conditin is tre, allstateme
wrtten before thr end f the doop are
exe<uted,
the loop.
otherwise the gTaro eastr
whife Cie)
begin
en
Verilog Rep eat :
rep eat C32)
begtn
end
Verlog forever:
ioitiaf
begs i
clk 1'bo
forever clk ekk;
en
O verilog detriptions of moatrple«ers ;
medole (a, 8, sEL, Gbar, y);
inrot t,8,SEL, GLar;
output
(se4, t&, Gbar)
begin if Gbar = )
elre
begin
elre
end
end
enduodole
To 2 1 MUx there are only to tnputr
je Ao, A, 11 seledtion line ie So and Sigle
output
Enale
a:1 Input outpot
MUx
’output So
() A.
A,
Seleet (s)
Fig. Bloc diagran Fig Tuth Table
The loqial eprerrion of the term y ir ar
followr
41 Mustirlexer :
Ln 4;L Mux, there is a total of foor
inputr e Ao, A, A2, Az,
As 22 sel eetton Jtaer
i,e so and Si and single ootput.
block diaqram and the trutt talle
of the 4 x| rutiplerer gives belo
A2 4 x4
Si
Cig. Block diagram
Tnputr outpot
So
* The logica! expression of the ter y ir
follows;
y S,'so to t S, SA, t S,So'At S, Sts
Vertlog code:
module mox (to,tA,A, Sel, g);
inpot o, t,, ta, A3
iopot Cio] sel;
outpot Y;
alvays @(t, or t,, or t or Ay)
begin
if ( sel :2'bbe)
efse if ( sel = 2'b oy
else if se= 2'bie)
end
endvoodule
8:1 mutiplexer
In the S:1 mutplexer, there are total eight
inputs ie i ic, is, i4, i3, i2, i, io, 3 Seleel ion
and Single otp ot
S2)
on the basis of the combinaton of inpotr
that are prrent et the seletion |nes
So, S, and S2. of these & nputr
Ore conneted to the output.
iç
i3 MUx
i2
S S, So
Slet sner
Fig. Blo ek DiagYam
Lnpotc Output
i3
is
is
1( i
Fig, TrotL Table
Verleg Code:
modole 8- Ci sel, y);
inpot T:Ji;
fnput C2:] sl;
output 9;
alays @ Cj se)
begta
Case ('sel)
3'o0o:y= icoJ;
3'Lo:y = iC3;
3Llooiy iic47;
3!: