DATA SHEET

[Link]

Fixed Frequency Current MARKING

DIAGRAM
Mode Controller for Flyback 8
Converters 46XXfff
ALYWX
SOIC−7 G
CASE 751U 1
NCP1246
46XXfff = Specific Device Code
The NCP1246 is a new fixed−frequency current−mode controller XX = A, B or AL
featuring the Dynamic Self−Supply. This function greatly simplifies fff = 065 or 100
the design of the auxiliary supply and the VCC capacitor by activating A = Assembly Location
L = Wafer Lot
the internal startup current source to supply the controller during
Y = Year
start−up, transients, latch, stand−by etc. This device contains a special W = Work Week
HV detector which detect the application unplug from the AC input G = Pb−Free Package
line and triggers the X2 discharge current. This HV structure allows
the brown−out detection as well. PIN CONNECTIONS
It features a timer−based fault detection that ensures the detection of
overload and an adjustable compensation to help keep the maximum Latch 1 8 HV
power independent of the input voltage. FB 2
Due to frequency foldback, the controller exhibits excellent VCC
CS 3 6
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp GND 4 5 DRV
compensation, and a versatile latch input make this controller an (Top View)
excellent candidate for the robust power supply designs.
A dedicated Off mode allows to reach the extremely low no load
ORDERING INFORMATION
input power consumption via “sleeping” whole device and thus See detailed ordering and shipping information on page 38 of
minimize the power consumption of the control circuitry. this data sheet.

Features
 Fixed−Frequency Current−Mode Operation (65 kHz  500/800 mA Source/Sink Drive Peak Current
and 100 kHz frequency options) Capability
 Frequency Foldback then Skip Mode for Maximized  10 ms Soft−Start, 4 ms Soft−Start (AL/BL Versions)
Performance in Light Load and Standby Conditions  Internal Thermal Shutdown
 Timer−Based Overload Protection with Latched  No−Load Standby Power < 30 mW
(Option A) or Auto−Recovery (Option B) Operation  X2 Capacitor in EMI Filter Discharging Feature
 High−voltage Current Source with Brown−Out  These Devices are Pb−Free, Halogen Free/BFR Free
Detection and Dynamic Self−Supply, Simplifying the and are RoHS Compliant
Design of the VCC Circuitry
 Frequency Modulation for Softened EMI Signature Typical Applications
 Adjustable Overpower Protection Dependant on the  AC−DC Adapters for Notebooks, LCD, and Printers
Bulk Voltage  Offline Battery Chargers
 Latch−off Input Combined with the Overpower  Consumer Electronic Power Supplies
Protection Sensing Input  Auxiliary/Housekeeping Power Supplies
 VCC Operation up to 28 V, With Overvoltage Detection  Offline Adapters for Notebooks

 Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

January, 2024 − Rev. 8 NCP1246/D
 NCP1246

TYPICAL APPLICATION EXAMPLE

Figure 1. Flyback Converter Application Using the NCP1246

PIN FUNCTION DESCRIPTION

Pin No Pin Name Function Pin Description
1 LATCH Latch−Off Input Pull the pin up or down to latch−off the controller. An internal current source
allows the direct connection of an NTC for over temperature detection.

2 FB Feedback + Shutdown pin An optocoupler collector to ground controls the output regulation. The part
goes to the low consumption Off mode if the FB input pin is pulled to GND.

3 CS Current Sense This Input senses the Primary Current for current−mode operation, and
offers an overpower compensation adjustment.

4 GND − The controller ground

5 DRV Drive output Drives external MOSFET
6 VCC VCC input This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is
connected to an external auxiliary voltage. It is not allowed to connect
another circuit to this pin to keep low input power consumption.
8 HV High−voltage pin Connects to the rectified AC line to perform the functions of Start−up
Current Source, Self−Supply, brown−out detection and X2 capacitor
discharge function and the HV sensing for the overpower protection
purposes. It is not allowed to connect this pin to DC voltage.

[Link]
2
 NCP1246

SIMPLIFIED INTERNAL BLOCK SCHEMATIC

LATCH

ON_CMP

Figure 2. Simplified Internal Block Schematic

[Link]
3
 NCP1246

MAXIMUM RATINGS
Rating Symbol Value Unit
DRV Maximum voltage on DRV pin –0.3 to 20 V
(pin 5) (Dc−Current self−limited if operated within the allowed range) (Note 1) 1000 (peak) mA

VCC VCCPower Supply voltage, VCC pin, continuous voltage –0.3 to 28 V

(pin 6) Power Supply voltage, VCC pin, continuous voltage (Note 1) 30 (peak) mA

HV Maximum voltage on HV pin –0.3 to 500 V

(pin 8) (Dc−Current self−limited if operated within the allowed range) 20 mA

Vmax Maximum voltage on low power pins (except pin 5, pin 6 and pin 8) –0.3 to 10 V
(Dc−Current self−limited if operated within the allowed range) (Note 1) 10 (peak) mA

RqJ−A Thermal Resistance SOIC−7 C/W

Junction-to-Air, low conductivity PCB (Note 2) 162
Junction-to-Air, medium conductivity PCB (Note 3) 147
Junction-to-Air, high conductivity PCB (Note 4) 115
RqJ−C Thermal Resistance Junction−to−Case 73 C/W
TJMAX Operating Junction Temperature −40 to +150 C
TSTRGMAX Storage Temperature Range −60 to +150 C
ESD Capability, HBM model (All pins except HV) per JEDEC Standard JESD22, Method A114E > 2000 V
ESD Capability, HBM model (HV pin) per JEDEC Standard JESD22, Method A114E > 1000 V
ESD Capability, Machine Model per JEDEC Standard JESD22, Method A115A > 200 V
ESD Capability, Charged Device Model per JEDEC Standard JESD22−C101D > 1000 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
2. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.

[Link]
4
 NCP1246

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = −40C to +125C, VHV = 125 V,
VCC = 11 V unless otherwise noted)

Characteristics Test Condition Symbol Min Typ Max Unit

HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source VHV(min) − 30 40 V
operation

Current flowing out of VCC pin VCC = 0 V Istart1 0.2 0.5 0.8 mA
VCC = VCC(on) − 0.5 V Istart2 5 8 11

Off−state leakage current VHV = 500 V, VCC = 15 V Istart(off) 10 25 50 mA

Off−mode HV supply current VHV = 141 V, IHV(off) − 45 60 mA
VHV = 325 V, − 50 70
VCC loaded by 4.7 mF cap
SUPPLY
HV current source regulation threshold VCC(reg) 8 11 − V
Turn−on threshold level, VCC going up VCC(on) 11.0 12.0 13.0 V
HV current source stop threshold
HV current source restart threshold VCC(min) 9.5 10.5 11.5 V
Turn−off threshold VCC(off) 8.5 8.9 9.3 V
Overvoltage threshold VCC(ovp) 25 26.5 28 V
Blanking duration on VCC(off) and VCC(ovp) tVCC(blank) − 10 − ms
detection

VCC decreasing level at which the internal VCC(reset) 4.8 7.0 7.7 V
logic resets

VCC level for ISTART1 to ISTART2 transition VCC(inhibit) 0.2 0.8 1.25 V
Internal current consumption (Note 5) DRV open, VFB = 3 V, 65 kHz ICC1 1.3 1.85 2.2 mA
DRV open, VFB = 3 V, 100 kHz ICC1 1.3 1.85 2.2

Cdrv = 1 nF, VFB = 3 V, 65 kHz ICC2 1.8 2.6 3.0

Cdrv = 1 nF, VFB = 3 V, 100 kHz ICC2 2.3 2.9 3.5

ICC3 0.67 0.9 1.13

Off mode (skip or before start−up)
ICC4 0.3 0.6 0.9
Fault mode (fault or latch)

BROWN−OUT
Brown−Out thresholds VHV going up VHV(start) 102 111 120 V
VHV going down VHV(stop) 94 103 112

Brown−Out thresholds (AL/BL Versions) VHV going up VHV(start) 92 101 110 V

VHV going down VHV(stop) 84 93 102

Timer duration for line cycle drop−out tHV 43 − 86 ms

X2 DISCHARGE
Comparator hysteresis observed at HV pin VHV(hyst) 1.5 3.5 5 V
HV signal sampling period Tsample − 1.0 − ms
Timer duration for no line detection tDET 21 32 43 ms
Discharge timer duration tDIS 21 32 43 ms
OSCILLATOR
Oscillator frequency fOSC 58 65 72 kHz
87 100 109

Maximum on time for TJ = 25C to +125C fOSC = 65 kHz tONmax(65kHz) 11.5 12.3 13.1 ms
only fOSC = 100 kHz tONmax(100kHz) 7.5 8.0 8.5
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.

[Link]
5
 NCP1246

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = −40C to +125C, VHV = 125 V,
VCC = 11 V unless otherwise noted)

Characteristics Test Condition Symbol Min Typ Max Unit

OSCILLATOR
Maximum on time fOSC = 65 kHz tONmax(65kHz) 11.3 12.3 13.1 ms
fOSC = 100 kHz tONmax(100kHz) 7.4 8.0 8.5

Maximum duty cycle (corresponding to fOSC = 65 kHz DMAX − 80 − %

maximum on time at maximum switching fOSC = 100 kHz
frequency)
Frequency jittering amplitude, in percentage Ajitter 4 6 8 %
of FOSC

Frequency jittering modulation frequency Fjitter 85 125 165 Hz

FREQUENCY FOLDBACK
Feedback voltage threshold below which VFB(foldS) 1.8 2.0 2.2 V
frequency foldback starts

Feedback voltage threshold below which VFB(foldE) 0.8 0.9 1.0 V

frequency foldback is complete

Minimum switching frequency VFB = Vskip(in) + 0.1 fOSC(min) 23 27 32 kHz

OUTPUT DRIVER
Rise time, 10 to 90% of VCC VCC = VCC(min) + 0.2 V, trise − 40 70 ns
CDRV = 1 nF

Fall time, 90 to 10% of VCC VCC = VCC(min) + 0.2 V, tfall − 40 70 ns

CDRV = 1 nF

Current capability VCC = VCC(min) + 0.2 V, mA

CDRV = 1 nF
DRV high, VDRV = 0 V IDRV(source) − 500 −
DRV low, VDRV = VCC IDRV(sink) − 800 −
Clamping voltage (maximum gate voltage) VCC = VCCmax – 0.2 V, DRV high, VDRV(clamp) 11 13.5 16 V
RDRV = 33 kW, Cload = 220 pF
High−state voltage drop VCC = VCC(min) + 0.2 V, VDRV(drop) − − 1 V
RDRV = 33 kW, DRV high
CURRENT SENSE
Input Pull−up Current VCS = 0.7 V Ibias − 1 − mA
Maximum internal current setpoint VFB > 3.5 V VILIM 0.66 0.70 0.74 V
Propagation delay from VIlimit detection to VCS = VILIM tdelay − 80 110 ns
DRV off

Leading Edge Blanking Duration for VILIM tLEB 200 250 320 ns
Threshold for immediate fault protection VCS(stop) 0.95 1.05 1.15 V
activation

Leading Edge Blanking Duration for VCS(stop) tBCS 90 120 150 ns

(Note 6)

Soft−start duration From 1st pulse to VCS = VILIM tSSTART 8 11 14 ms

AL/BL Versions 2.8 4.0 5.2

Frozen current setpoint VI(freeze) 275 300 325 mV

INTERNAL SLOPE COMPENSATION
Slope of the compensation ramp Scomp(65kHz) − −32.5 − mV /
Scomp(100kHz) − −50 − ms
FEEDBACK
Internal pull−up resistor TJ = 25C RFB(up) 15 20 25 kW
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.

[Link]
6
 NCP1246

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = −40C to +125C, VHV = 125 V,
VCC = 11 V unless otherwise noted)

Characteristics Test Condition Symbol Min Typ Max Unit

FEEDBACK
VFB to internal current setpoint division ratio KFB 4.7 5 5.3 −
Internal pull−up voltage on the FB pin VFB(ref) 4.5 5 5.5 V
(Note 6)

Feedback voltage below which the peak VFB(freeze) 1.35 1.5 1.65 V
current is frozen

SKIP CYCLE MODE

Feedback voltage thresholds for skip mode VFB going down Vskip(in) 0.63 0.70 0.77 V
VFB going up Vskip(out) 0.72 0.80 0.88

REMOTE CONTROL ON FB PIN

The voltage above which the part enters the VCC > VCC(off), VHV = 60 V VON − 2.2 − V
on mode

The voltage below which the part enters the VCC > VCC(off) VOFF 0.35 0.40 0.45 V
off mode

Minimum hysteresis between the VON and VCC > VCC(off), VHV = 60 V VHYST 500 − − mV
VOFF

Pull−up current in off mode VCC > VCC(off) IOFF − 5 − mA

Go To Off mode timer VCC > VCC(off) tGTOM 100 150 300 ms
OVERLOAD PROTECTION
Fault timer duration tfault 108 128 178 ms
Autorecovery mode latch−off time duration tautorec 0.85 1.00 1.35 s
OVERPOWER PROTECTION
VHV to IOPC conversion ratio KOPC − 0.54 − mA / V
Current flowing out of CS pin (Note 7) VHV = 125 V IOPC(125) − 0 − mA
VHV = 162 V IOPC(162) − 20 −
VHV = 325 V IOPC(325) − 110 −
VHV = 365 V IOPC(365) 105 130 150
FB voltage above which IOPC is applied VHV = 365 V VFB(OPCF) 2.12 2.35 2.58 V
FB voltage below which is no IOPC applied VHV = 365 V VFB(OPCE) − 2.15 − V
LATCH−OFF INPUT
High threshold VLatch going up VOVP 2.35 2.5 2.65 V
Low threshold VLatch going down VOTP 0.76 0.8 0.84 V
Current source for direct NTC connection VLatch = 0 V mA
During normal operation INTC 65 95 105
During soft−start INTC(SSTART) 130 190 210
Blanking duration on high latch detection 65 kHz version tLatch(OVP) 35 50 70 ms
100 kHz version 20 35 50

Blanking duration on low latch detection tLatch(OTP) − 350 − ms

Clamping voltage ILatch = 0 mA Vclamp0(Latch) 1.0 1.2 1.4 V
ILatch = 1 mA Vclamp1(Latch) 1.8 2.4 3.0

TEMPERATURE SHUTDOWN
Temperature shutdown TJ going up TTSD − 150 − C
Temperature shutdown hysteresis TJ going down TTSD(HYS) − 30 − C
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

[Link]
7
 NCP1246

TYPICAL CHARACTERISTIC

40 32
38
30
36
34
28

Istart(off) (mA)
VHV(min) (V)

32
30 26
28
24
26
24
22
22
20 20
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 3. Minimum Current Source Operation Figure 4. Off−State Leakage Current Istart(off)
VHV(min)

50 8.8

45 8.7
IHV(off) @ VHV = 325 V
8.6
40
IHV(off) (mA)

Istart2 (mA)

8.5
35 IHV(off) @ VHV = 141 V
8.4
30
8.3

25
8.2

20 8.1
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 5. Off−Mode HV Supply Current IHV(off) Figure 6. High Voltage Startup Current
Flowing Out of VCC Pin Istart2
120 120
118 118
116 116
114 114
VHV(start) (V)

VHV(stop) (V)

112 112
110 110
108 108
106 106
104 104
102 102
100 100
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 7. Brown−out Device Start Threshold Figure 8. Brown−out Device Stop Threshold
VHV(start) VHV(stop)

[Link]
8
 NCP1246

TYPICAL CHARACTERISTIC

0.75 310
0.74 308
0.73 306
0.72 304

VI(freeze) (mV)
0.71 302
VILIM (V)

0.70 300
0.69 298
0.68 296
0.67 294
0.66 292
0.65 290
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 9. Maximum Internal Current Setpoint Figure 10. Frozen Current Setpoint VI(freeze) for
VILIM the Light Load Operation
1.15 110
1.13
100
1.11
1.09 90
VCS(stop) (V)

1.07
tdelay (ns)

80
1.05
70
1.03
1.01 60
0.99
50
0.97
0.95 40
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 11. Threshold for Immediate Fault Figure 12. Propagation Delay tdelay
Protection Activation VCS(stop)

300 130
290
125
280
270
120
IOPC(365) (mA)

260
tLEB (ns)

250 115
240
110
230
220
105
210
200 100
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 13. Leading Edge Blanking Duaration Figure 14. Maximum Overpower
tLEB Compensating Current IOPC(365) Flowing Out
of CS Pin

[Link]
9
 NCP1246

TYPICAL CHARACTERISTIC

24 5.20

23 5.15

22 5.10
5.05
21
RFB(up) (kW)

5.00

VFB(ref) (V)
20
4.95
19
4.90
18
4.85
17 4.80
16 4.75
15 4.70
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 15. FB Pin Internal Pull−up Resistor Figure 16. FB Pin Open Voltage VFB(ref)
RFB(up)

2.65 0.85
0.84
2.60
0.83
0.82
2.55
0.81
VOVP (V)

VOTP (V)

2.50 0.80
0.79
2.45
0.78
0.77
2.40
0.76
2.35 0.75
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 17. Latch Pin High Threshold VOVP Figure 18. Latch Pin Low Threshold VOTP

110 220

105 210

100 200
INTC(SSTART) (mA)

95 190
INTC (mA)

90 180

85 170

80 160

75 150

70 140
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 19. Current INTC Sourced from the Figure 20. Current INTC(SSTART) Sourced from
Latch Pin, Allowing Direct NTC Connection the Latch Pin, During Soft−Start

[Link]
10
 NCP1246

TYPICAL CHARACTERISTIC

70 100
69 99
68 98
67 97
66 96
fOSC (kHz)

fOSC (kHz)
65 95
64 94
63 93
62 92
61 91
60 90
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 21. Oscillator fOSC for the 65 kHz Figure 22. Oscillator fOSC for the 100 kHz
Version Version
12.8 8.4
12.7
8.3
12.6
12.5 8.2
tONmax (ms)

tONmax (ms)

12.4
8.1
12.3

12.2 8.0
12.1
7.9
12.0

11.9 7.8
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 23. Maximum ON Time tONmax for the Figure 24. Maximum ON Time tONmax for the
65 kHz Version 100 kHz Version

85 30
84
29
83
28
82
fOSC(min) (ms)

81 27
DMAX (%)

80 26
79
25
78
24
77
76 23

75 22
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)

Figure 25. Maximum Duty Ratio DMAX Figure 26. Minimum Switching Frequency
fOSC(min)

[Link]
11
 NCP1246

TYPICAL CHARACTERISTIC

2.20 1.00

2.15 0.98
0.96
2.10
0.94
2.05
VFB(foldS) (V)

VFB(foldE) (V)
0.92
2.00 0.90

1.95 0.88
0.86
1.90
0.84
1.85 0.82
1.80 0.80
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 27. FB Pin Voltage Below Which Figure 28. FB Pin Voltage Below Which
Frequency Foldback Starts VFB(foldS) Frequency Foldback Complete VFB(foldE)

0.77 0.88

0.75 0.86

0.84
0.73
0.82
Vskip(on) (V)
Vskip(in) (V)

0.71
0.80
0.69
0.78
0.67
0.76
0.65 0.74

0.63 0.72
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 29. FB Pin Skip−In Level Vskip(in) Figure 30. FB Pin Skip−Out Level Vskip(out)

2.60 2.40
2.55 2.35
2.50 2.30
2.45 2.25
VFB(OPCE) (V)
VFB(OPCF) (V)

2.40 2.20
2.35 2.15
2.30 2.10
2.25 2.05
2.20 2.00
2.15 1.95
2.10 1.90
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 31. FB Pin Level VFB(OPCF) Above Figure 32. FB Pin Level VFB(OPCE) Below
Which is the Overpower Compensation Which is No Overpower Compensation
Applied Applied

[Link]
12
 NCP1246

TYPICAL CHARACTERISTIC

13.0 11.5
12.8 11.3
12.6 11.1
12.4 10.9

VCC(min) (V)
12.2 10.7
VCC(on) (V)

12.0 10.5
11.8 10.3
11.6 10.1
11.4 9.9
11.2 9.7
11.0 9.5
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 33. VCC Turn−on Threshold Level, VCC Figure 34. HV Current Source Restart
Going Up HV Current Source Stop Threshold Threshold VCC(min)
VCC(on)

9.4 7.3
7.2
9.2
7.1
9.0
7.0
VCC(reset) (V)
VCC(off) (V)

8.8 6.9

8.6 6.8

6.7
8.4
6.6
8.2 6.5

8.0 6.4
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 35. VCC Turn−off Threshold (UVLO) Figure 36. VCC Decreasing Level at Which the
VCC(off) Internal Logic Resets VCC(reset)
2.0 3.2

ICC1(100kHz) ICC2(100kHz)
1.9 3.0

1.9 2.8
ICC1 (mA)

ICC2 (mA)

ICC1(65kHz)
1.8 2.6 ICC2(65kHz)

1.8 2.4

1.7 2.2

1.7 2.0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 37. Internal Current Consumption when Figure 38. Internal Current Consumption when
DRV Pin is Unloaded DRV Pin is Loaded by 1 nF

[Link]
13
 NCP1246

TYPICAL CHARACTERISTIC

4.0 1.10

3.9 1.08
1.06
3.8
1.04
3.7
VHV(hyst) (V)

Tsample (ms)
1.02
3.6 1.00

3.5 0.98
0.96
3.4
0.94
3.3 0.92
3.2 0.90
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 39. X2 Discharge Comparator Figure 40. HV Signal Sampling Period Tsample
Hysteresis Observed at HV Pin VHV(hyst)

2.6 0.45

2.6 0.44
0.43
2.5
0.42
2.5 0.41
VOFF (V)
VON (V)

2.4 0.40

2.4 0.39
0.38
2.3
0.37
2.3 0.36
2.2 0.35
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 41. FB Pin Voltage Level Above Which Figure 42. FB Pin Voltage Level Below Which
is Entered On Mode VON is Entered Off Mode VOFF

150 300
280
145
260
240
140
220
tGTOM (ms)
tfault (ms)

135 200
180
130
160
140
125
120
120 100
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TEMPERATURE (C) TEMPERATURE (C)
Figure 43. Fault Timer Duration tfault Figure 44. Go To Off Mode Timer Duration
tGTOM

[Link]
14
 NCP1246

APPLICATION INFORMATION

Functional Description For loads that are between approximately 32% and 10%
The NCP1246 includes all necessary features to build a of full rated power, the converter operates in frequency
safe and efficient power supply based on a fixed−frequency foldback mode (FFM). If the feedback pin voltage is lower
flyback converter. The NCP1246 is a multimode controller than 1.5 V the peak switch current is kept constant and the
as illustrated in Figure 45. The mode of operation depends output voltage is regulated by modulating the switching
upon line and load condition. Under all modes of operation, frequency for a given and fixed input voltage VHV.
the NCP1246 terminates the DRV signal based on the switch Effectively, operation in FFM results in the application of
current. Thus, the NCP1246 always operates in current constant volt−seconds to the flyback transformer each
mode control so that the power MOSFET current is always switching cycle. Voltage regulation in FFM is achieved by
limited. varying the switching frequency in the range from 65 kHz
Under normal operating conditions, the FB pin commands (or 100 kHz) to 27 kHz. For extremely light loads (below
the operating mode of the NCP1246 at the voltage approximately 6% full rated power), the converter is
thresholds shown in Figure 45. At normal rated operating controlled using bursts of 27 kHz pulses. This mode is called
loads (from 100% to approximately 33% full rated power) as skip mode. The FFM, keeping constant peak current and
the NCP1246 controls the converter in fixed frequency skip mode allows design of the power supplies with
PWM mode. It can operate in the continuous conduction increased efficiency under the light loading conditions.
mode (CCM) or discontinuous conduction mode (DCM) Keep in mind that the aforementioned boundaries of
depending upon the input voltage and loading conditions. If steady−state operation are approximate because they are
the controller is used in CCM with a wide input voltage subject to converter design parameters.
range, the duty−ratio may increase up to 50%. The build−in
slope compensation prevents the appearance of
sub−harmonic oscillations in this operating area.

Low consumption off mode

ON

OFF Fixed Ipeak

Skip mode
FFM PWM at fOSC

0V 0.4 V 0.7 V 1.1 V 1.5V 2.0 V 2.2 V 3.5 V VFB

0.8 V
Figure 45. Mode Control with FB pin voltage

There was implemented the low consumption off mode decreases below the 0.4 V the controller will enter the low
allowing to reach extremely low no load input power. This consumption off mode. The controller can start if the FB pin
mode is controlled by the FB pin and allows the remote voltage increases above the 2.2 V level.
control (or secondary side control) of the power supply See the detailed status diagrams for the both versions fully
shut−down. Most of the device internal circuitry is unbiased latched A and the autorecovery B on the following figures.
in the low consumption off mode. Only the FB pin control The basic status of the device after wake–up by the VCC is
circuitry and X2 cap discharging circuitry is operating in the the off mode and mode is used for the overheating protection
low consumption off mode. If the voltage at feedback pin mode if the thermal shutdown protection is activated.

[Link]
15
 Figure 46. Operating Status Diagram for the Fully Latched Version A of the Device
Extra Low Consumption Efficient operating mode
(VFB < VOFF) * GTOMtimer*(VCC > VCCoff)
BO+TSD
BO+TSD
No AC
VHV > VHV(NOAC)

[Link]
X2 cap SSend
NCP1246

Reset (VCC > VCCon)*BO

Off Mode (VFB > VON)*Latch
Soft
Discharge Stop Running
Latch=0 Start
AC present Latch=X
Latch=0

16
+
discharged

(VFB > VON)*Latch

(VILIM +MaxDC)*tfault
VCC > VCCreset

BO
Skip in Skip out
VCC > VCCreset
Power On Latch
(VCC < VCCoff
VCC > VCCoff VCC Skip
Reset BO
Latch=1 fault mode
Latch=0
Regulated Self−Supply Dynamic Self−Supply
OVP+OTP+VCCovp+VCSstop
(VCC < VCCoff
(if not enoughgh auxiliary voltage is
present)
 Figure 47. Operating Status Diagram for the Autorecovery Version B of the Device
Extra Low Consumption Efficient operating mode
(VFB < VOFF) * GTOMtimer*(VCC > VCCoff)
BO+TSD
BO+TSD
No AC
VHV > V
HV(NOAC)
X2 cap Off Mode Reset (VCC > VCCon)*BO

[Link]
Discharge (VFB > VON)*Latch*AutoRec
Latch=0 Soft SSend
NCP1246

Latch=0 Stop Start Running

AutoRec=0 AC present
Latch=X AutoRec=0
+
AutoRec=X

(VILIM + MaxDC)*tfault

17
discharged
(VFB > VON)*Latch

BO+tautorec
VCC > VCCreset

BO
BO
Skip in Skip out
Power On Autorecovery
VCC < VCCreset Reset Latch Latch
VCC > VCCoff VCC < VCCoff
Skip
Latch=0 BO VCC
AutoRec=0 Latch=1 fault mode
AutoRec=1
OVP+OTP+VCCovp VCSstop Dynamic Self−Supply
Regulated Self−Supply VCC < VCCoff (if not enough auxiliary voltage is
present)
(VFB > VON)*AutoRec
 NCP1246

The information about the fault (permanent Latch or Even though the Dynamic Self−Supply is able to maintain
Autorecovery) is kept during the low consumption off mode the VCC voltage between VCC(on) and VCC(min) by turning
due the safety reason. The reason is not to allow unlatch the the HV start−up current source on and off, it can only be used
device by the remote control being in off mode. in light load condition, otherwise the power dissipation on
the die would be too much. As a result, an auxiliary voltage
Start−up of the Controller source is needed to supply VCC during normal operation.
At start−up, the current source turns on when the voltage The Dynamic Self−Supply is useful to keep the controller
on the HV pin is higher than VHV(min), and turns off when alive when no switching pulses are delivered, e.g. in
VCC reaches VCC(on), then turns on again when VCC reaches brown−out condition, or to prevent the controller from
VCC(min), until the input voltage is high enough to ensure a stopping during load transients when the VCC might drop.
proper start−up, i.e. when VHV reaches VHV(start). The The NCP1246 accepts a supply voltage as high as 28 V, with
controller actually starts the next time VCC reaches VCC(on). an overvoltage threshold VCC(ovp) that latches the controller
The controller then delivers pulses, starting with a soft−start off.
period tSSTART during which the peak current linearly
increases before the current−mode control takes over.

VHV

V HV(start)

V HV(min) Waits next VCC(on)

before starting

time
VCC
V CC(on)

V CC(min)
HV current
HV current
source = I start1
source = Istart2

V CC(inhibit)

time

DRV

Figure 48. VCC Start−up Timing Diagram

time

[Link]
18
 NCP1246

For safety reasons, the start−up current is lowered when threshold and an autorecovery brown−out protection; both
VCC is below VCC(inhibit), to reduce the power dissipation in of them independent of the ripple on the input voltage. It is
case the VCC pin is shorted to GND (in case of VCC capacitor allowed only to work with an unfiltered, rectified ac input to
failure, or external pull−down on VCC to disable the ensure the X2 capacitor discharge function as well, which is
controller). There is only one condition for which the current described in following. The brown−out protection
source doesn’t turn on when VCC reaches VCC(inhibit): the thresholds are fixed, but they are designed to fit most of the
voltage on HV pin is too low (below VHV(min)). standard ac−dc conversion applications.
When the input voltage goes below VHV(stop), a
HV Sensing of Rectified AC Voltage brown−out condition is detected, and the controller stops.
The NCP1246 features on its HV pin a true ac line The HV current source maintains VCC at VCC(min) level until
monitoring circuitry. It includes a minimum start−up the input voltage is back above VHV(start).

HV timer elapsed
VHV

VHV(start)
VHV(stop)

time
HV stop

Brown-out
tHV detected

Waits next time

VccON before
VCC starting
VCC(on)

VCC(min)

Brown-out
time
DRV condition
resets the
Internal Latch

time
Figure 49. Ac Line Drop−out Timing Diagram

When VHV crosses the VHV(start) threshold, the controller a timer of duration tHV, this ensures that the controller
can start immediately. When it crosses VHV(stop), it triggers doesn’t stop in case of line cycle drop−out.

[Link]
19
 NCP1246

X2 Cap Discharge Feature In case of the dc signal presence on the high voltage input,
The X2 capacitor discharging feature is offered by usage the direct sample of the high voltage obtained via the high
of the NCP1246. This feature save approx. 16 mW – 25 mW voltage sensing structure and the delayed sample of the high
input power depending on the EMI filter X2 capacitors voltage are equivalent and the comparator produces the low
volume and it saves the external components count as well. level signal during the presence of this signal. No edges are
The discharge feature is ensured via the start−up current present at the output of the comparator, that’s why the
source with a dedicated control circuitry for this function. detection timer is not reset and dc detect signal appears.
The X2 capacitors are being discharged by current defined The minimum detectable slope by this ac detector is given
as Istart2 when this need is detected. by the ration between the maximum hysteresis observed at
There is used a dedicated structure called ac line unplug HV pin VHV(hyst),max and the sampling time:
detector inside the X2 capacitor discharge control circuitry. V HV(hyst),max
See the Figure 50 for the block diagram for this structure and S min + (eq. 1)
Figures 51, 52, 53 and 54 for the timing diagrams. The basic T sample
idea of ac line unplug detector lies in comparison of the Than it can be derived the relationship between the
direct sample of the high voltage obtained via the high minimum detectable slope and the amplitude and frequency
voltage sensing structure with the delayed sample of the high of the sinusoidal input voltage:
voltage. The delayed signal is created by the sample & hold
V HV(hyst),max
structure. 5
V max + +
The comparator used for the comparison of these signals 2 @ p @ f @ T sample 2 @ p @ 35 @ 1 @ 10 −3 (eq. 2)
is without hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the + 22.7 V
sampling time TSAMPLE and additional internal offset NOS. The minimum detectable AC RMS voltage is 16 V at
These parameters ensure the noise immunity as well. The frequency 35 Hz, if the maximum hysteresis is 5 V and
additional offset is added to the picture of the sampled HV sampling time is 1 ms.
signal and its analog sum is stored in the C1 storage The X2 capacitor discharge feature is available in any
capacitor. If the voltage level of the HV sensing structure controller operation mode to ensure this safety feature. The
output crosses this level the comparator CMP output signal detection timer is reused for the time limiting of the
resets the detection timer and no dc signal is detected. The discharge phase, to protect the device against overheating.
additional offset NOS can be measured as the VHV(hyst) on The discharging process is cyclic and continues until the ac
the HV pin. If the comparator output produces pulses it line is detected again or the voltage across the X2 capacitor
means that the slope of input signal is higher than set is lower than VHV(min). This feature ensures to discharge
resolution level and the slope is positive. If the comparator quite big X2 capacitors used in the input line filter to the safe
output produces the low level it means that the slope of input level. It is important to note that it is not allowed to
signal is lower than set resolution level or the slope is connect HV pin to any dc voltage due this feature. e.g.
negative. There is used the detection timer which is reset by directly to bulk capacitor.
any edge of the comparator output. It means if no edge During the HV sensing or X2 cap discharging the VCC net
comes before the timer elapses there is present only dc signal is kept above the VCC(off) voltage by the Self−Supply in any
or signal with the small ac ripple at the HV pin. This type of mode of device operation to supply the control circuitry.
the ac detector detects only the positive slope, which fulfils During the discharge sequence is not allowed to start−up the
the requirements for the ac line presence detection. device.

[Link]
20
 NCP1246

Figure 50. The ac Line Unplug Detector Structure Used for X2 Capacitor Discharge System

Figure 51. The ac Line Unplug Detector Timing Diagram

[Link]
21
 NCP1246

Figure 52. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects

[Link]
22
 NCP1246

Figure 53. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under Extremely Low Line Condition

[Link]
23
 NCP1246

Figure 54. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under High Line Condition

The Low Consumption Off Mode Only the X2 cap discharge and Self−Supply features is
There was implemented the low consumption off mode enabled in the low consumption off mode. The X2 cap
allowing to reach extremely low no load input power as discharging feature is enable due the safety reasons and the
described in previous chapters. If the voltage at feedback pin Self−Supply is enabled to keep the VCC supply, but only
decreases below the 0.4 V the controller enters the off mode. very low VCC consumption appears in this mode. Any other
The internal VCC is turned−off, the IC consumes extremely features are disabled in this mode.
low VCC current and only the voltage at external VCC The information about the latch status of the device is kept
capacitor is maintained by the Self−Supply circuit. The in the low consumption off mode and this mode is used for
Self−Supply circuit keeps the VCC voltage at the VCC(reg) the TSD protection as well. The protection timer
level. The supply for the FB pin watch dog circuitry and FB GoToOffMode tGTOM is used to protect the application
pin bias is provided via the low consumption current sources against the false activation of the low consumption off mode
from the external VCC capacitor. The controller can only by the fast drop outs of the FB pin voltage below the 0.4 V
start, if the FB pin voltage increases above the 2.2 V level. level. E.g. in case when is present high FB pin voltage ripple
See Figure 55 for timing diagrams. during the skip mode.

[Link]
24
 NCP1246

Figure 55. Start−up, Shutdown and AC Line Unplug Time Diagram

Oscillator with Maximum On Time and Frequency

Jittering
The NCP1246 includes an oscillator that sets the
switching frequency 65 kHz or 100 kHz depending on the
version. The maximum on time is 12.3 ms (for 65 kHz
version) or 8 ms (for 100 kHz version) with an accuracy of
7%. The maximum on time corresponds to maximum duty
cycle of the DRV pin is 80% at full switching frequency. In
order to improve the EMI signature, the switching frequency
jitters 6 % around its nominal value, with a triangle−wave
shape and at a frequency of 125 Hz. This frequency jittering
is active even when the frequency is decreased to improve
Figure 56. Frequency Modulation of the Maximum
the efficiency in light load condition.
Switching Frequency

[Link]
25
 NCP1246

Low Load Operation Modes: Frequency Foldback frequency foldback mode to provide the natural transformer
Mode (FFM) and Skip Mode core anti−saturation protection. The frequency jittering is
In order to improve the efficiency in light load conditions, still active while the oscillator frequency decreases as well.
the frequency of the internal oscillator is linearly reduced The current setpoint is fixed to 300 mV in the frequency
from its nominal value down to fOSC(min). This frequency foldback mode if the feedback voltage decreases below the
foldback starts when the voltage on FB pin goes below VFB(freeze) level. This feature increases efficiency under the
VFB(foldS), and is complete when VFB reaches VFB(foldE). light loads conditions as well.
The maximum on−time duration control is kept during the

Figure 57. Frequency Foldback Mode Characteristic

Figure 58. Current Setpoint Dependency on the Feedback Pin Voltage

When the FB voltage reaches Vskip(in) while decreasing, below Vskip(out), the controller remains in this state; but as
skip mode is activated: the driver stops, and the internal soon as VFB crosses the skip out threshold, the DRV pin
consumption of the controller is decreased. While VFB is starts to pulse again.

[Link]
26
 NCP1246

Figure 59. Skip Mode Timing Diagram

Clamped Driver resulting voltage is applied to the CS pin. It is applied to one

The supply voltage for the NCP1246 can be as high as input of the PWM comparator through a 250 ns LEB block.
28 V, but most of the MOSFETs that will be connected to the On the other input the FB voltage divided by 5 sets the
DRV pin cannot accept more than 20 V on their gate. The threshold: when the voltage ramp reaches this threshold, the
driver pin is therefore clamped safely below 16 V. This output driver is turned off. The maximum value for the
driver has a typical capability of 500 mA for source current current sense is 0.7 V, and it is set by a dedicated comparator.
and 800 mA for sink current. Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when VCC reaches VCC(on), a
Current−Mode Control With Slope Compensation and
soft−start is applied: the current sense setpoint is increased
Soft−Start
by 15 discrete steps from 0 (the minimum level can be
NCP1246 is a current−mode controller, which means that
higher than 0 because of the LEB and propagation delay)
the FB voltage sets the peak current flowing in the
until it reaches VILIM (after a duration of tSSTART), or until
inductance and the MOSFET. This is done through a PWM
the FB loop imposes a setpoint lower than the one imposed
comparator: the current is sensed across a resistor and the
by the soft−start (the two comparators outputs are OR’ed).

[Link]
27
 NCP1246

Figure 60. Soft−Start Feature

Under some conditions, like a winding short−circuit for In order to allow the NCP1246 to operate in CCM with a
instance, not all the energy stored during the on time is duty cycle above 50%, the fixed slope compensation is
transferred to the output during the off time, even if the on internally applied to the current−mode control. The slope
time duration is at its minimum (imposed by the propagation appearing on the internal voltage setpoint for the PWM
delay of the detector added to the LEB duration). As a result, comparator is −32.5 mV/ms typical for the 65 kHz version,
the current sense voltage keeps on increasing above VILIM, and −50 mV/ms for the 100 kHz version. The slope
because the controller is blind during the LEB blanking compensation can be observable as a value of the peak
time. Dangerously high current can grow in the system if current at CS pin.
nothing is done to stop the controller. That’s what the The internal slope compensation circuitry uses a sawtooth
additional comparator, that senses when the current sense signal synchronized with the internal oscillator is subtracted
voltage on CS pin reaches VCS(stop) ( = 1.5 x VILIM ), does: from the FB voltage divided by KFB.
as soon as this comparator toggles, the controller
immediately enters the protection mode.

[Link]
28
 NCP1246

Figure 61. Slope Compensation Block Diagram

Figure 62. Slope Compensation Timing Diagram

Internal Overpower Protection Unfortunately, due to the inherent propagation delay of

The power delivered by a flyback power supply is the logic, the actual peak current is higher at high input
proportional to the square of the peak current in voltage than at low input voltage, leading to a significant
discontinuous conduction mode: difference in the maximum output power delivered by the
1 2
power supply.
P OUT + @ h @ L P @ F SW @ I P (eq. 3)
2

[Link]
29
 NCP1246

Figure 63. Needs for Line Compensation For True Overpower Protection

To compensate this and have an accurate overpower would be in the same order of magnitude. Therefore the
protection, an offset proportional to the input voltage is compensation current is only added when the FB voltage is
added on the CS signal by turning on an internal current higher than VFB(OPCE). However, because the HV pin is
source: by adding an external resistor in series between the being connected to ac voltage, there is needed an additional
sense resistor and the CS pin, a voltage offset is created circuitry to read or at least closely estimate the actual voltage
across it by the current. The compensation can be adjusted on the bulk capacitor.
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it

Figure 64. Overpower Protection Current Relation to Feedback Voltage

[Link]
30
 NCP1246

Figure 65. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage

Figure 66. Block Schematic of Overpower Protection Circuit

A 3 bit A/D converter with the peak detector senses the ac line unplug detector. The sensed HV pin voltage peak value
input, and its output is periodically sampled and reset, in is validated when no HV edges from comparator are present
order to follow closely the input voltage variations. The after last falling edge during two sample clocks. See
sample and reset events are given by the output from the ac Figure 67 for details.

[Link]
31
 NCP1246

Overcurrent Protection with Fault timer release are the brown−out condition or the VCC power on
The overload protection depends only on the current reset. The timer is reset when the CS setpoint goes back
sensing signal, making it able to work with any transformer, below VILIM before the timer elapses. The fault timer is also
even with very poor coupling or high leakage inductance. started if the driver signal is reset by the maximum on time.
When an overcurrent occurs on the output of the power The controller also enters the same protection mode if the
supply, the FB loop asks for more power than the controller voltage on the CS pin reaches 1.5 times the maximum
can deliver, and the CS setpoint reaches VILIM. When this internal setpoint VCS(stop) (allows to detect winding
event occurs, an internal tfault timer is started: once the timer short−circuits) or there appears low VCC supply. See
times out, DRV pulses are stopped and the controller is either Figures 68 and 69 for the timing diagram.
latched off (latched protection, option A) or this latch can be In autorecovery mode if the fault has gone, the supply
released in autorecovery mode (option B), the controller resumes operation; if not, the system starts a new burst cycle.
tries to restart after tautorec. Other possibilities of the latch

[Link]
32
 NCP1246

VHVSAMPLE TSAMPLE

VHV(hyst)

time
Comparator 1st HV edge
resets the watch
Output
dog and starts
the peak
detection of HV
pin signal

time
Sample clock

time
2nd sample clock
2nd sample clock
Watch dog pulse after last
pulse after last
HV edge initiates
signal the watch dog
HV edge initiates
the watch dog
signal
signal

Peak detector time

Reset
Reset

Sample time
Sample

IOPC

time
Figure 67. Overpower Compensation Timing Diagram

[Link]
33
 NCP1246

PROTECTION MODES AND THE LATCH MODE RELEASES

Event Timer Protection Next Device Status Release to Normal Operation Mode
Overcurrent Fault timer Latch Autorecovery – B version
VILIM > 0.7 V Brown−out
VCC < VCC(reset)
Maximum on time Fault timer Latch Autorecovery – B version
Brown−out
VCC < VCC(reset)
Winding short Immediate reaction Latch Autorecovery – B version
Vsense > VCS(stop) Brown−out
VCC < VCC(reset)
Low supply 10 ms timer Latch Autorecovery – B version
VCC < VCC(off) Brown−out
VCC < VCC(reset)
External OTP, OVP 55 ms (35 ms at 100 kHz) Latch Brown−out
VCC < VCC(reset)

High supply 10 ms timer Latch Brown−out

VCC > VCC(ovp) VCC < VCC(reset)

Brown−out HV timer Device stops (VHV > VHV(start))&( VCC > VCC(on))
VHV < VHV(stop)

Internal TSD 10 ms timer Device stops, HV start−up (VHV > VHV(start)) & ( VCC > VCC(on)) &
current source stops TSDb

Off mode 150 ms timer Device stops and internal (VHV > VHV(start)) & ( VCC > VCC(on)) &
VFB < VOFF VCC is turned off ( VFB > VON)

[Link]
34
 NCP1246

VCC(on)

VCC(min)

Figure 68. Latched Timer−Based Overcurrent Protection (Option A)

[Link]
35
 NCP1246

VCC(on)

VCC(min)

Figure 69. Timer−Based Protection Mode with Autorecovery Release from Latch−off (Option B)

[Link]
36
 NCP1246

Latch−Off Input

Figure 70. Latch Detection Schematic

The Latch pin is dedicated to the latch−off function: it Reset occurs when a brown−out condition is detected or
includes two levels of detection that define a working the VCC is cycled down to a reset voltage, which in a real
window, between a high latch and a low latch: within these application can only happen if the power supply is
two thresholds, the controller is allowed to run, but as soon unplugged from the ac line.
as either the low or the high threshold is crossed, the Upon startup, the internal references take some time
controller is latched off. The lower threshold is intended to before being at their nominal values; so one of the
be used with an NTC thermistor, thanks to an internal current comparators could toggle even if it should not. Therefore the
source INTC. internal logic does not take the latch signal into account
An active clamp prevents the voltage from reaching the before the controller is ready to start: once VCC reaches
high threshold if it is only pulled up by the INTC current. To VCC(on), the latch pin High latch state is taken into account
reach the high threshold, the pull−up current has to be higher and the DRV switching starts only if it is allowed; whereas
than the pull−down capability of the clamp (typically the Low latch (typically sensing an over temperature) is
1.5 mA at VOVP). taken into account only after the soft−start is finished. In
To avoid any false triggering, spikes shorter than 50 ms addition, the NTC current is doubled to INTC(SSTART) during
(for the high latch and 65 kHz version) or 350 ms (for the low the soft−start period, to speed up the charging of the Latch
latch) are blanked and only longer signals can actually latch pin capacitor. The maximum value of Latch pin capacitor is
the controller. given by the following formula (The standard start−up
condition is considered and the NTC current is neglected):
t SSTART min @ I NTC(SSTART) min 8.0 @ 10 −3 @ 130 @ 10 −6
C LATCH max + + F + 1.04 mF (eq. 4)
V clamp0 min 1.0

+ 364 nF(ALVersion)

[Link]
37
 NCP1246

VCC(on)

VCC(min)

Figure 71. Latch Timing Diagram

Temperature Shutdown low power consumption. There is kept the VCC supply to
The NCP1246 includes a temperature shutdown keep the TSD information. When the temperature falls
protection with a trip point typically at 150C and the typical below the low threshold, the start−up of the device is enabled
hysteresis of 30C. When the temperature rises above the again, and a regular start−up sequence takes place. See the
high threshold, the controller stops switching status diagrams at the Figures 46 and 47.
instantaneously, and goes to the off mode with extremely

ORDERING INFORMATION 5
Ordering Part No. Overload Protection Switching Frequency Package Shipping†
NCP1246AD065R2G Latched 65 kHz
NCP1246BD065R2G Autorecovery 65 kHz
NCP1246ALD065R2G Latched 65 kHz
NCP1246BLD065R2G Autorecovery 65 kHz SOIC−7
2500 / Tape & Reel
NCP1246AD100R2G Latched 100 kHz (Pb−Free)

NCP1246BD100R2G Autorecovery 100 kHz

NCP1246ALD100R2G Latched 100 kHz
NCP1246BLD100R2G Autorecovery 100 kHz
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

[Link]
38
 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−7
CASE 751U
ISSUE E
SCALE 1:1 DATE 20 OCT 2009

−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
8 5 3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
−B− S 0.25 (0.010) M B M 4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
1 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
4 PER SIDE.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C R X 45 _ C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
J H 0.10 0.25 0.004 0.010
−T− SEATING J 0.19 0.25 0.007 0.010
PLANE K 0.40 1.27 0.016 0.050
K M 0_ 8_ 0_ 8_
H M
D 7 PL N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M T B S A S

GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
XXXXX
1.52 ALYWX
0.060 G
1

XXX = Specific Device Code

7.0 4.0 A = Assembly Location
0.275 0.155 L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.
0.6 1.270 Pb−Free indicator, “G” or microdot “G”, may
0.024 0.050 or may not be present. Some products may
not follow the Generic Marking.
SCALE 6:1 ǒinches
mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON12199D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−7 PAGE 1 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2002 [Link]

 SOIC−7
CASE 751U
ISSUE E
DATE 20 OCT 2009

STYLE 1: STYLE 2: STYLE 3:

PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2
5. EMITTER 5. BASE, #2 5. GATE, #2
6. 6. EMITTER, #2 6. SOURCE, #2
7. NOT USED 7. NOT USED 7. NOT USED
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1

STYLE 4: STYLE 5: STYLE 6:

PIN 1. ANODE PIN 1. DRAIN PIN 1. SOURCE
2. ANODE 2. DRAIN 2. DRAIN
3. ANODE 3. DRAIN 3. DRAIN
4. ANODE 4. DRAIN 4. SOURCE
5. ANODE 5. 5. SOURCE
6. ANODE 6. 6.
7. NOT USED 7. NOT USED 7. NOT USED
8. COMMON CATHODE 8. SOURCE 8. SOURCE

STYLE 7: STYLE 8: STYLE 9:

PIN 1. INPUT PIN 1. COLLECTOR (DIE 1) PIN 1. EMITTER (COMMON)
2. EXTERNAL BYPASS 2. BASE (DIE 1) 2. COLLECTOR (DIE 1)
3. THIRD STAGE SOURCE 3. BASE (DIE 2) 3. COLLECTOR (DIE 2)
4. GROUND 4. COLLECTOR (DIE 2) 4. EMITTER (COMMON)
5. DRAIN 5. COLLECTOR (DIE 2) 5. EMITTER (COMMON)
6. GATE 3 6. EMITTER (DIE 2) 6. BASE (DIE 2)
7. NOT USED 7. NOT USED 7. NOT USED
8. FIRST STAGE Vd 8. COLLECTOR (DIE 1) 8. EMITTER (COMMON)

STYLE 10: STYLE 11:

PIN 1. GROUND PIN 1. SOURCE (DIE 1)
2. BIAS 1 2. GATE (DIE 1)
3. OUTPUT 3. SOURCE (DIE 2)
4. GROUND 4. GATE (DIE 2)
5. GROUND 5. DRAIN (DIE 2)
6. BIAS 2 6. DRAIN (DIE 2)
7. NOT USED 7. NOT USED
8. GROUND 8. DRAIN (DIE 1)

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON12199D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−7 PAGE 2 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

[Link]
2
© Semiconductor Components Industries, LLC, 2002 [Link]
 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at [Link]/site/pdf/Patent−[Link]. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS: ONLINE SUPPORT: [Link]/support
Technical Library: [Link]/design/resources/technical−documentation For additional information, please contact your local Sales Representative at
onsemi Website: [Link] [Link]/support/sales