SOLUTION BANK

BCA 505T MICROPROCESSOR & ASSEMBLY LANGUAGE

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 BCA505T : MICROPROCESSOR AND ASSEMBLY LAGUAGE

Total Teaching Hours : 60 No of Hours / Week : 04

Unit - I
Architecture and Operation: Introduction to 8085, Microprocessor organization/ architecture
& its operation Microprocessor based system, memory interfacing , basic interfacing
concepts ,interfacing I/O devices
[ 12 Hours ]
Unit - II
Programming the 8085: Programming model, instruction classification , Instruction format,
addressing modes, writing assembly level programs-overview of instruction set, timing
diagrams data transfer, Arithmetic, Logic branch operations.
[ 12 Hours ]
Unit - III
Programming techniques- Looping Counting and Indexing , 16 bit arithmetic operations ,
logic operations Compare and rotate operations . Counters and Time delays , Generation of
pulse waveforms. Stacks and subroutines- conditional CALL and RETURN instructions.
Advanced subroutine concepts. BCD to Binary and Binary to BCD conversions, BCD to 7
segment conversion , Binary to ASCII and ASCII to Binary code conversion, BCD addition
and subtraction , multiplication and division.
[ 12 Hours ]
Unit – IV
Memory Interface: Memory and I/O mapping and interfacing concepts. Interrupts : 8085
vectored interrupts , Restart as Software instructions, additional I/O concepts and processes.
[ 12 Hours ]
Unit – V
Interfacing of peripherals (I/Os) and applications: Interfacing Keyboard (linear and matrix)
and 7 segment display including multiplexes, 8279 programmable keyboard
/display interface, 8255 PPI , 8259 PIC , DMA and 8257 DMA controller , Serial
communication using 8251, D to A converters and interfacing, RS323
serial communication standard.

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 Suggested Question Pattern
V BCA
(Y2K14 – CBCS)
Bangalore University
BCA 505T –MP
Unit Chapter Part A Part B Total
Marks
2Marks 5 Marks Question
Question
(Part of 10 Marks
Question of Part B)
Unit - I Architecture and Operation 3 2 26

Unit - II Programming the 8085 3 1 16

Unit - III 2 3 34
Programming techniques

Unit - IV Memory Interface 2 2 24

Unit - V Interfacing of peripherals 2 1 14

(I/Os) and applications

Total 12 11 104

SECTION – A ( 2 Marks)
UNIT-I

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[ Nov / Dec 2016 ]
01. Draw the flag register mentioning the flag status?
[ Nov / Dec 2017]
01. What is Microprocessor? Give the word length of 8085 Microprocessor.
[Link] Program Counter and Stack Pointer.
03. Explain SID and SOD pins of 8085.
[ Nov / Dec 2018]
01. What is a microprocessor?
02. Explain briefly about the different types of buses in 8085.
03. Name the flags of 8085.
04. Define the terms machine cycle and instruction cycle.
05. What is memory interfacing?
[ TMAQ - important tutor mark assignment questions ]
[Link] T- state, Machine Cycle and Instruction Cycle.
02. What is address bus and data bus.
03. What is the use of ALE.
UNIT-II
[ Nov / Dec 2016]
01. What is the function of instruction register and decoder?
02. What is Immediate addressing? Mention an example.
03. Write any two instructions to clear the contents of accumulator register.
04. Find the contents of accumulator after executing the following block of program segment.
Content of B register is 3EH. Initially.
MOV A,B
RLC
RLC
HLT
05. Explain DAA instruction
06. Two consecutive memory locations store 3EH and 2FH data respectively. Find the content of
accumulator after executing following segment of program.
LXI H 2050H
MOV A,M
INX H
SUB M
INX H
MOV M, A
[ Nov / Dec 2017]
01. Write any two examples for 3 byte Instructions.
02. Explain Instruction DAD D.
03. Find the number of bytes required to store the following instructions:
I. CPI FFH.
II. LXI D, 8500.

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[ Nov / Dec 2018]
01. Mention any two instructions which clear the contents of accumulator.
02.. Explain any two data transfer instructions of 8085.
03. Compare SUB reg and CMP reg instructions.
04. Write an assembly language program to find the 2’s complement of an 8-bit number.
UNIT-II
[ Nov / Dec 2016]
01. Draw the flowchart to generate delay loop using register.
[ Nov / Dec 2017]
[Link] is Subroutine?
02. Define counting and looping.
[Link] POP and PUSH Instruction.
[ Nov / Dec 2018]
01. Define counters and time delays.
02. Write an ALP to add two-N byte numbers.

UNIT-IV
[ Nov / Dec 2016]
01. Differentiate between absolute and partial decoding.
[ Nov / Dec 2017]
02. Define maskable and Non-maskable interrupts of 8085.
[ Nov / Dec 2018]
03. Define interrupt.
UNIT-V

[ Nov / Dec 2016]

01. What is I/O Interfacing?
02. Draw the bit pattern of control word for 8255.
03. Explain the priority modes of 8259.
[ Nov / Dec 2017]
01. What are handshake signals?

SECTION – B ( 5 Marks)

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 UNIT-I

[ Nov / Dec 2016]

01. a) Draw the pin configuration of 8085 microprocessor.

b) With diagram explain how control signals are generated?
02. Explain Memory read machine cycle with timing diagram.
[ Nov / Dec 2017]
01. Draw the architecture of 8085 microprocessor and briefly explain.
02. What are flags? Draw the format of flag register and explain their function.

UNIT-II
[Nov / Dec 2016]
01.a) Write an ALP to add two-N byte numbers.
b) Classify the instructions based on sizes and explain each with example.
02. a) Explain i) STAX D ii) ADC R iii)XCHG instructions.
03. Write an ALP for block transfer of data bytes.
[ Nov / Dec 2017]
01. Write a program to load 07F in the register B and find its 2’s compliment.
02. Explain the following instructions of 8085:
STAXD
CMPM
XCHG
3. Write short notes on :
a) Addressing modes of 8085.
b) Data transfer instructions in 8085.

[ Nov / Dec 2018]

01. a) What is addressing mode? explain briefly the various addressing modes of
8085Microprocessor
b) Explain the classification of 8085 microprocessor instruction based on word size. Give
example.
02. a) write assembly language program to subtract two 16- bit numbers.
b) Explain the instructions DAA and DAD Rp.
03. With an example, explain the logical instructions of 8085 microprocessors.
[ TMAQ - important tutor mark assignment questions ]
01 Explain Call, Reset, Conditional(any instructions)
02 Data transfer instructions
03 Logical Instructions

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 04 Stack operations
05 Machine control instructions

UNIT III

[ Nov / Dec 2016]

01. Explain unconditional Jump Instructions.
02. Explain nesting of subroutine with an example.

[ Nov / Dec 2017]

01. What is stack? Explain PUSH and POP operation.
02. Explain CALL and RETURN operations in 8085.

[ TMAQ - important tutor mark assignment questions ]

01 What is time delay and counter?
02 Explain programmed I/O data transfer
03 Explain Push and Pop operations
04 Explain Subroutine and call.

UNIT-IV

[ Nov / Dec 2016]

01. Compare memory mapped I/O and I/O mapped I/O.
02. a) What is an Interrupt? Explain the classification of interrupts.
b) Explain RIM instruction with bit pattern.
[ Nov / Dec 2018]
01. Briefly explain the 8085 vectored interrupts.

[ TMAQ - important tutor mark assignment questions ]

1. 01 Algorithm and steps for Binary to ASCII

02 Algorithm and steps for ASCII to Binary
03 Algorithm and steps for ASCII to BCD conversion
04 Types of Interrupts
05 Explain Daisy Chain Method
06 What is hardware and software interrupt?
07 What is maskable and non- maskable interrupts?

UNIT-V

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 [ Nov / Dec 2016]
01. Explain the functional block diagram of 8255 PPI.
02. write a note on interfacing devices.

[ Nov / Dec 2017]

01. Explain SIM and RIM Instructions.

[ Nov / Dec 2018]

01. Write short notes on:
DMA (Direct memory Access)
[ TMAQ - important tutor mark assignment questions ]
01. 8257 DMA Controller
02 .8255 Control word format
03 .8255 Block diagram and Pin diagram
04 .8259 Block diagram and Pin configuration

SECTION – A ( 2 Marks)
UNIT-I
[ Nov / Dec 2016 ]
01. Draw the flag register mentioning the flag status?

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[ Nov / Dec 2017]
01. What is Microprocessor? Give the word length of 8085 Microprocessor.
A microprocessor is a multipurpose programmable clock driven register based
semiconductor device manufactured by using VLSI techniques to perform all
computations in digital computer.

[Link] Program Counter and Stack Pointer.

 Program Counter: This register is used to sequence the execution of the instructions. The
function of the program counter is to point to the memory address from which the next byte
is to be fetched. When a byte (machine code) is being fetched, the program counter is
incremented by one to point to the next memory location.
 Stack Pointer: It is used as a memory pointer. It points to a memory location in read/write
memory, called the stack. It is always incremented/decremented by 2 during push and pop
operation.

03. Explain SID and SOD pins of 8085.

 SID (Serial Input port): It is a data line for serial input. The 7 th bit of the
accumulator is loaded with the data on SID line, when RIM (Read Interrupt
Mask) instruction is executed.
 SOD (Serial Output port): It is a data line for serial output. The 7th bit of
the accumulator is outputted on SOD line, when SIM(Set Interrupt Mask)
instruction is executed.

[ Nov / Dec 2018]

1. What is a microprocessor?
A microprocessor is a multipurpose programmable clock driven register based
semiconductor device manufactured by using VLSI techniques to perform all
computations in digital computer.

2. Explain briefly about the different types of buses in 8085.

Address bus: It is a group of 16 lines identified as A0to A15 used to identify the
peripheral devices or memory locations in a digital computer system & is
unidirectional i.e., data bits flow in one direction.
Data bus: The data bus is a group of 8 lines identified as D0 to D7 and is a
bidirectional bus used to carry 8-bits data between μP and other external units in
both directions.
Control bus: It contains various single lines which have specific functions for
coordinating and controlling μP operations.

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3. Name the flags of 8085.
 Sign Flags[S]
 Zero Flags[Z]
 Auxiliary Carry Flags[AC]
 Parity Flags[P]
 Carry Flags[CY]

04. Define the terms machine cycle and instruction cycle.

 Machine cycle: It is the time required to access the memory devices or I/O
devices. In machine cycle various operations like opcode fetch, memory
read, memory write, I/O read, I/O write are performed.
 Instruction cycle: The time taken to complete the execution of one
instruction. The 8085 microprocessor consists of one to six machine cycle
or operations.

05. What is memory interfacing?

 While executing a program, the microprocessor needs to access memory
frequently to read instruction codes and data stored in memory and the
interfacing circuit enables that access.

UNIT-II

[ Nov / Dec 2016]

01. What is the function of instruction register and decoder?
 When an instruction is fetched from memory then it is stored in the Instruction register.
 Instruction decoder decodes the information present in the Instruction register. 8085
microprocessor is one of the most interesting topic.

02. What is Immediate addressing? Mention an example.

In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand.
For example: MVI K, 20F: means 20F is copied into register K.

03. Write any two instructions to clear the contents of accumulator register.
[Link] A 00H
[Link] A
[Link] A
[Link] 00H....

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04. Find the contents of accumulator after executing the following block of
program segment. Content of B register is 3EH. Initially.
MOV A,B
RLC
RLC
HLT
3 E
0011 1110 1st RLC (to shift left by 1 bit)

0011 1110 2nd RLC (again shift by 1 bit)

F 8
1111 1000 Accumulator=F8

05. Explain DAA instruction

The DAA (Decimal Adjust after Addition) instruction allows addition of numbers represented in
8-bit packed BCD code.
It is used immediately after normal addition instruction operating on BCD codes.

06. Two consecutive memory locations store 3EH and 2FH data respectively.
Find the content of accumulator after executing following segment of
program.
LXI H 2050H
MOV A,M
INXH
SUBM
INXH
MOV M, A
(1111) Borrow
3E-> 00111110
2F-> 00101111
00001111

[ Nov / Dec 2017]

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01. Write any two examples for 3 byte Instructions.
LDA 8509 Hex code = 3A, 09, 85 (Three bytes)
STA 2600 Hex code = 32, 00, 26 (Three bytes)
02. Explain Instruction DAD D.
DAD is a mnemonic, which stands for Double ADD and also rp stands for any one of the
following register pairs as mentioned below.

rp = BC, DE, or HL

As rp can have any of the three values, there are three opcodes for this type of instruction. It
occupies only 1-Byte in memory.

03. Find the number of bytes required to store the following instructions:
I. CPI FFH.
II. LXI D, 8500.
I. 16bits (2 bytes).
II. 8bits (3 byte).

[ Nov / Dec 2018]

01. Mention any two instructions which clear the contents of accumulator.
 MVI A 00H
 XRA A
 SUB A
 ANI 00H....
02.. Explain any two data transfer instructions of 8085.
MOV Rd, RS [Move the content of one register to another]: This instruction
copies the contents of the source register [, RS] into the destination register [Rd].
LDA 16-bit address: It transfers the content stored in the addressed memory
location to accumulator.
STA 16-bit address: It transfers the content stored in the accumulator to
addressed memory location. i.e.,[M address] [A].

03. Compare SUB reg and CMP reg instructions.

SUB(subtracts register from accumulator):The contents of the register are subtracted from the
contents of the accumulator and the result is placed in the ‘A’.
CMP(compare register with accumulator): The contents of register R is subtracted from the
contents of accumulator but the result is not stored.

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04. Write an assembly language program to find the 2’s complement of an 8-
bit number. Algorithm –

MEMORY MNEMONICS OPERANDS COMMENT

2000 LDA [3000] [A] <- [3000]

2003 CMA [A] <- [A^]

2004 STA [3001] 1’s complement

2007 ADI 01 [A] <- [A] + 01

2009 STA [3002] 2’s complement

200C HLT Stop

UNIT-III

[ Nov / Dec 2016]

01. Draw the flowchart to generate delay loop using register.

[ Nov / Dec 2017]

[Link] is Subroutine?
A subroutine is a sequence of program instructions that perform a specific task, packaged as a unit. This
unit can then be used in programs wherever that particular task have to be performed. A subroutine is
often coded so that it can be started (called) several times and from several places during one execution of

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the program, including from other subroutines, and then branch back (return) to the next instruction after
the call, once the subroutine’s task is done. It is implemented by using Call and Return instructions.

02. Define counting and looping.

Counting: This technique allows programmer to count how many times the instruction/set of
instructions are executed.
Looping: In this technique, the program is instructed to execute certain set of instructions
repeatedly to execute a particular task number of times.

[Link] POP and PUSH Instruction.

POP instruction: It is a one byte instruction, which can be used to retrieve the contents of
registers from the stack. It is generally represented by POP Rp.
PUSH instruction: It is a one byte instruction, which can be used to copy the contents of
register pairs [Rp] to the me0mory location
MEMORY pointed by Stack pointer(SP). It is generally
MNEMONICS COMMENTS
ADDRESS represented by the instruction.

2000 LDA 2050 A ← 2050

[ Nov / Dec 2018]
2003 MOV B, A B←A 01. Define counters and time delays.
A counter is designed simply by loading
2004 LDA 2052 A ← 2052 appropriate number into one of the registers and
using INR or DCR instructions.
2007 ADD B A ← A+B Time delay is a procedure used to design a
specific delay. It is designed by loading a
2008 STA 3050 A → 3050 register with a delay count and set up a loop to
decrement the count until zero.
200B LDA 2051 A ← 2051

200E MOV B, A B←A 02. Write an ALP to add two-N byte

numbers.

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 200F LDA 2053 A ← 2053

2012 ADC B A ← A+B+CY

2013 STA 3051 A → 3051

2016 HLT Stops execution

UNIT-IV

[ Nov / Dec 2016]

01. Differentiate between absolute and partial decoding.

Absolute Decoding Partial Decoding
The decoding in which all available address line The decoding in which all available address line(16
(16 lines in memory mapped and 8 lines in lines in memory mapping and 8 lines in. peripheral
peripheral mapping) are used for decoding to mapping) are not used for decoding resulting in
generate a unique address. multiple address for same port.

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[ Nov / Dec 2017]
01. Define maskable and Non-maskable interrupts of 8085.
 Maskable interrupt:Maskable Interrupts are those which can be disabled or ignored by
the microprocessor. These interrupts are either edge-triggered or level-triggered, so they
can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085
microprocessor.
 Non-Maskable interrupt:Non-Maskable Interrupts are those which cannot be disabled
or ignored by microprocessor. TRAP is a non-maskable interrupt. It consists of both level
as well as edge triggering and is used in critical power failure conditions.

[ Nov / Dec 2018]

01. Define interrupt.

Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

UNIT-V

[ Nov / Dec 2016]

01. What is I/O Interfacing?
There are various communication devices like the keyboard, mouse, printer, etc. To interface the
keyboard and other devices with the microprocessor by using latches and buffers. This type of
interfacing is known as I/O interfacing.
02. Draw the bit pattern of control word for 8255.

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03. Explain the priority modes of 8259.
1. Fully Nested Mode(FNM):
The fully nested mode is the general purpose mode is the purpose mode in which all
interrupt requests are arranged from the highest to lowest priority level.’
[Link] Rotation mode:
A device after being serviced receives the lowest priority.
[Link] Rotation Mode:
This mode is similar to the automatic rotation mode, except that the user can select an IR
for the lowest priority, thus fixing all other priorities.

[ Nov / Dec 2017]

01. What are handshake signals?
Handshaking is a I/O control method to synchronize I/O devices with the microprocessor. As
many I/O devices accepts or release information at a much slower rate than the microprocessor,
this method is used to control the microprocessor to work with a I/O device at the I/O devices
data transfer rate.

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 SECTION – B ( 5 Marks)
UNIT-I

[ Nov / Dec 2016]

01. a) Draw the pin configuration of 8085 microprocessor.

1. Address Bus and Data Bus:

The address bus is a group of sixteen lines i.e., A0-A15. The address bus is
unidirectional, i.e., bits flow in one direction from the microprocessor unit to the
peripheral devices and uses the high order address bus.
2. Control and Status Signals:
 ALE– It is an Address Latch Enable signal. It goes high during first T state of a
machine cycle and enables the lower 8-bits of the address, if its value is 1
otherwise data bus is activated.
 IO/M’ – It is a status signal which determines whether the address is for input-
output or memory. When it is high(1) the address on the address bus is for input-
output devices. When it is low(0) the address on the address bus is for the
memory.
 SO, S1– These are status signals. They distinguish the various types of operations
such as halt, reading, instruction fetching or writing.
 RD’– It is a signal to control READ operation. When it is low the selected
memory or input-output device is read.
 WR’ – It is a signal to control WRITE operation. When it goes low the data on the
data bus is written into the selected memory or I/O location.
 READY – It senses whether a peripheral is ready to transfer data or not. If
READY is high(1) the peripheral is ready. If it is low(0) the microprocessor waits
till it goes high. It is useful for interfacing low speed devices.

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 3. Power Supply and Clock Frequency:
 Vcc– +5v power supply
 Vnn– Ground ReferenceXI, X2 – A crystal is connected at these two pins. The
frequency is internally divided by two, therefore, to operate a system at 3MHZ the
crystal should have frequency of 6MHZ.
 CLK (OUT) – This signal can be used as the system clock for other devices.
 Interrupts and Peripheral Initiated Signals:
 The 8085 has five interrupt signals that can be used to interrupt a program
execution.

b) With diagram explain how control signals are generated?

Control signals:
The control signals are provided to support the 8085 memory instructions. They control
functions such as when the bus is to carry a valid address in which direction data are to be
transferred over the bus, when to put read data on the system bus.
Three control signals are RD, WR & ALE.
 RD – This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
 WR – This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
 ALE – It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.

02. Explain Memory read machine cycle with timing diagram.

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 Operation:
 It is used to fetch one byte from the memory.

 It requires 3 T-States.

 It can be used to fetch operand or data from the memory.

 During T1, A8-A15 contains higher byte of address. At the same time ALE is high.
Therefore Lower byte of address A0-A7 is selected from AD0-AD7.

 Since it is memory ready operation, IO/M(bar) goes low.

 During T2 ALE goes low, RD(bar) goes low. Address is removed from AD0-AD7
and data D0-D7 appears on AD0-AD7.

 During T3, Data remains on AD0-AD7 till RD(bar) is at low signal.

[ Nov / Dec 2017]

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01. Draw the architecture of 8085 microprocessor and briefly explain

The following are the functional blocks in the 8085 Microprocessor.

1. Accumulator
2. Temporary register
3. Arithmetic and Logic Unit (ALU)
4. Flag register
5. Instruction Register
6. Instruction Decoder and Machine cycle encoder
7. General purpose registers
8. Stack Pointer
9. Program Counter
10. Increment / Decrement
11. Timing and Control unit
12. Interrupt control
13. Serial I/O control
14. Address buffer and Address / Data buffer

1. Accumulator (A-register)
It is an 8-bit register. It is associated with ALU. The accumulator is also called A-register.
During the arithmetic / logic operations, one of the operand is available in Accumulator. The
result of the arithmetic / logic operations is also stored in the Accumulator.

2. Temporary (TEMP) register

It is an 8-bit register. It is also associated with ALU. This register is used to hold one of the data

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(from memory or general purpose registers) during an arithmetic / logic operation.

3. Arithmetic and Logic Unit (ALU)

The Arithmetic and Logic Unit includes Accumulator, Temporary register, arithmetic and logic
circuits and flag register. The ALU can perform arithmetic (such as addition and subtraction) and
logic operations (such as AND, OR and EX-OR) on 8-bit data. It receives the data from
accumulator and or TEMP register. The result is stored in the accumulator. The conditions of the
result (such as carry, zero) are indicated in the flags.

4. Flag register
It is an 8-bit register. But only five bits are used. The flag positions in the flag register are shown
below.

Flag register of 8085: The flags are affected by the arithmetic and logic operations in the ALU.
The flag register is also known as Status register or Condition code register. There are five flags
namely Sign (S) flag, Zero (Z) flag, Auxiliary Carry (AC) flag, Parity (P) flag and Carry (CY)
flag.

• Sign (S) flag: Sign flag is set (1) if the bit D7 of the result in the accumulator is 1, otherwise it
is reset (0). This flag is set when the result is negative. This flag is used only for signed numbers.

• Zero (Z) flag: Zero flag is set (1) if the result in the accumulator is zero, otherwise it is reset
(0).

• Auxiliary Carry (AC): Auxiliary Carry flag is set (1) if there is a carry from bit position D3of
result in the accumulator, otherwise it is reset (0). This flag is used for BCD operations.

• Parity (P) flag: Parity flag is set (1) if the result in the accumulator has even number of 1s,
otherwise it is reset (0).

• Carry (CY) flag: Carry flag is set (1) if the result of an arithmetic operation results in a carry
from bit position D7, otherwise it is reset (0). This flag is also used to indicate a borrow
condition during subtraction operations.

5. Instruction register
When an instruction is fetched from memory, it is stored in the Instruction register. It is an 8-bit
register. This resister cannot be used in the programs.

6. Instruction Decoder and Machine cycle encoding

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This unit decodes the instruction stored in the Instruction register. It determines the nature of the
instruction and establishes the sequence of events to be followed by the Timing and control unit.

7. General purpose registers

There are six 8-bit general purpose registers namely B, C, D, E, H and L registers. B and C
registers are combined together as BC register pair for 16-bit operations. Similarly, D and E
registers can be used as DE resister pair and H and L as HL register pair. The HL register pair is
also used as memory pointer (M-register) for storing 16-bit address in some instructions. There
are two more 8-bit temporary registers W and Z. These registers are used to hold data during the
execution of some instructions. W and Z registers cannot be used in programs.

8. Stack Pointer (SP)

Stack is a portion of memory (RAM) used as FILO (First In Last Out) buffer. This is mainly
used during subroutine operations. Stack Pointer is a 16-bit register used as a memory pointer
(16-bit address) for denoting the stack position in memory. The Stack pointer is decremented
each time when data is loaded into the stack and incremented when data is retrieved from the
stack. Stack pointer always points to the top of the stack memory.

9. Program Counter (PC)

The Program Counter (PC) is a 16-bit register. It is used to point the address of the next
instruction to be fetched from the memory. When one instruction is fetched from memory, PC is
automatically incremented to point out the next instruction.

10. Increment / Decrement

This unit is used to increment or decrement the contents of the 16-bit registers.

11. Timing and Control unit

The internal clock generator is available in this unit. This unit has the micro programs for all the
instructions to carry out the micro steps required in completing the instructions. This unit
receives signals from the Instruction decoder and Machine cycle encoding unit and generates
control signals according to the micro-program for the instruction.

12. Interrupt control

There are five hardware interrupts available in 8085 Microprocessor namely TRAP, RST 7.5,
RST 6.5, RST 5.5 and INTR for interfacing the peripherals with the microprocessor. These
interrupts are handled by the Interrupt control unit. INT A signal is generated by the Interrupt
control unit as an acknowledgement for an interrupting device. If two or more interrupts occur at
the same time, service is given according to the priority basis.

13. Serial I/O control

Serial data is transmitted to the peripherals through SOD pin and received through the SID pin.
The SOD and SID pins are handled by the Serial I/O control unit using the SIM and RIM
instructions.

14. Address buffer and Address / Data buffer

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The Address buffer is an 8-bit unidirectional buffer from which the higher order address bits A8
– A15 leaves the microprocessor to the memory and peripherals. The Address / Data buffer is an
8-bit bidirectional buffer used for sending the lower order address bits A0 – A7 and sending and
receiving the data bits D0 – D7 to the memory and peripherals.

02. What are flags? Draw the format of flag register and explain their
function.

The Flag register is a Special Purpose Register. Depending upon the value of result after any
arithmetic and logical operation the flag bits become set (1) or reset (0). In 8085
microprocessor, flag register consists of 8 bits and only 5 of them are useful.

It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
These are the set of 5 flip-flops −
 Sign Flag: It occupies the seventh bit of the flag register, which is also known as the most
significant bit. It helps the programmer to know whether the number stored in the
accumulator is positive or negative. If the sign flag is set, it means that number stored in
the accumulator is negative, and if reset, then the number is positive.
 Zero Flag:It occupies the sixth bit of the flag register. It is set, when the operation
performed in the ALU results in zero (all 8 bits are zero), otherwise it is reset. It helps in
determining if two numbers are equal or not.
 Auxiliary Carry Flag: It occupies the fourth bit of the flag register. In an arithmetic
operation, when a carry flag is generated by the third bit and passed on to the fourth bit,
then Auxiliary Carry flag is set. If not flag is reset. This flag is used internally for BCD
(Binary-Coded Decimal Number) operations.
 Parity Flag: It occupies the second bit of the flag register. This flag tests for number of
1’s in the accumulator. If the accumulator holds even number of 1’s, then this flag is set
and it is said to even parity. On the other hand, if the number of 1’s is odd, then it is reset
and it is said to be odd parity.
 Carry Flag: It occupies the zeroth bit of the flag register. If the arithmetic operation
results in a carry (if result is more than 8 bit), then Carry Flag is set; otherwise it is reset.

UNIT-II

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[ Nov / Dec 2016]
01. Write an ALP to add two-N byte numbers.

MEMORY
MNEMONICS COMMENTS
ADDRESS

2000 LDA 2050 A ← 2050

2003 MOV B, A B←A

b) Classify the instructions based on
sizes and explain each with example.
2004 LDA 2052 A ← 2052
8085 instruction set is classified into 3
2007 ADD B A ← A+B categories by considering the length of the
instructions. In 8085, the length is measured
2008 STA 3050 A → 3050 in terms of “byte” rather then “word” because
8085 microprocessor has 8-bit data bus. Three
200B LDA 2051 A ← 2051 types of instruction are: 1-byte instruction, 2-
byte instruction, and 3-byte instruction.
200E MOV B, A B←A 1. One-byte instructions –
In 1-byte instruction, the opcode and the
200F LDA 2053 A ← 2053
operand of an instruction are represented in
2012 ADC B A ← A+B+CY one byte.
Example-1:
2013 STA 3051 A → 3051 Copy the contents of accumulator in register
B.
2016 HLT Stops execution
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Mnemonic- MOV B, A
Opcode- MOV
Operand- B, A
Hex Code- 47H
Binary code- 0100 0111

02. Two-byte instructions –

Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next 8 bits indicates the operand.
Example-1:
Task- Load the hexadecimal data 32H in the accumulator.
Mnemonic- MVI A, 32H
Opcode- MVI
Operand- A, 32H
Hex Code- 3E
32
Binary code- 0011 1110
0011 0010

[Link]-byte instructions –
Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next two bytes specify the 16-bit address. The low-order address is represented in second
byte and the high-order address is represented in the third byte.
Example-1:
Task- Load contents of memory 2050H in the accumulator.
Mnemonic- LDA 2050H
Opcode- LDA
Operand- 2050H
Hex Code- 3A
50
20
Binary code- 0011 1010
0101 0000
0010 0000

02. a) Explain i) STAX D ii) ADC R iii)XCHG instructions.

i) STAX(Store accumulator indirect): - The contents of the accumulator are copied into the
memory location specified by the contents of the operand (register pair). The contents of the
accumulator are not altered.
Eg: - STAX B (the content of accumulator is stored into the memory location specified by the
DE register pair.)

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ii) ADC R:-Adds the destination operand (first operand), the source operand (second operand),
and the carry (CF) flag and stores the result in the destination operand. The destination operand
can be a register or a memory location; the source operand can be an immediate, a register, or a
memory location.

iii) XCHG: - Exchange H and L with D and E. The contents of register H are exchanged with the
contents of register D, and the contents of register L are exchanged with the contents of register
E.
Eg: - XCHG

03. Write an ALP for block transfer of data bytes.

[ Nov / Dec 2017]

01. Write a program to load 07F in the register B and find its 2’s compliment.
MVI B 07H  Move 07 in register B
CMA Complement 07
INR A 2’s Complement of 07
STA Store the 2’s complement
01. Explain the following instructions of 8085:
STAXD
CMPM

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XCHG
STAX (Store accumulator indirect):- The contents of the accumulator are copied into the
memory location specified by the contents of the operand (register pair). The contents of the
accumulator are not altered.

Eg:- STAX B (the content of accumulator is stored into the memory location specified by the
BC register pair.)
Compare (register or memory) with accumulator (CMP R/M):
This is a 1-byte instruction. It compares the data byte in the register or memory with the contents
of accumulator.
1. If A less than (R/M), the CY flag is set and Zero flag is reset.
2. If A equals to (R/M), the Zero flag is set and CY flag is reset.
3. If A greater than (R/M), the CY and Zero flag are reset.
When memory is an operand, its address is specified by HL Pair. No contents are modified;
however all remaining flags (S, P, AC) are affected according to the result of subtraction.
XCHG:-Exchange H and L with D and E. The contents of register H are exchanged with the
contents of register D, and the contents of register L are exchanged with the contents of
register E.

1. Write short notes on :

c) Addressing modes of 8085.
Addressing modes are the instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the memory without any
alteration in the content. In 8085 microprocessor there are 5 types of addressing modes:
1. Immediate Addressing Mode –
In immediate addressing mode the source operand is always data. If the data is 8-bit, then
the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3
bytes.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)
2. Register Addressing Mode –
In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore the operation is performed within various registers of
the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)

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 ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
3. Direct Addressing Mode –
In direct addressing mode, the data to be operated is available inside a memory location
and that memory location is directly specified as an operand. The operand is directly
available in the instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 01)
4. Register Indirect Addressing Mode –
IN register indirect addressing mode, the data to be operated is available inside a memory
location and that memory location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contains of B-C register to the accumulator)
LXIH 9570 (load immediate the H-L pair with the address of the location 9570)
5. Implied/Implicit Addressing Mode –
In implied/implicit addressing mode the operand is hidden and the data to be operated is
available in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contains of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

d) Data transfer instructions in 8085.

 MOV Rd, Rs [Move the content of one register to another]: This instruction copies
the contents of the source register (Rs) into the destination register (Rd). The contents of
the source register are not altered. The Rd, Rscan be any general purpose registers or
Accumulator (B, C, D, E H, L or A).
Ex: Assume register C contains 42H. To transfer the contents of register C to register B,
the required instruction is MOV B, C.
 It has one-byte size.
 Register addressing mode.
 4 T-state.
 1 machine cycle.
 No flags are affected.

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 MVI R, 8-bit data [Move immediate 8-bit data to register]: This instruction transfer
the given 8-bit data to the register[R]. Where, R is any general purpose register or
Accumulator (A, B, C, D, E, H or L).
Ex: The instruction required to copy the 8-bit data (88H) into Accumulator is MVI A,
88H.
 It has 2-byte size.
 Immediate addressing mode.
 7 T-state.
 2 machine cycle.
 No flags affected.

 LXI Rp, 16-bit data [Load register pair immediate]: Specified 16-bit data is loaded
into the register pair[Rp]. Where, Rpis BC, DE or HL register pair or SP (Stack Pointer).
Ex: The instruction required to load 16-bit data 2050H into the DE register pair is LXID
D, 2050H
 It is 3-byte size.
 Immediate addressing mode.
 10 T-state.
 3 machine cycle.
 No flags are affected.

 LDA 16-bit address: It transfers the content stored in the addressed memory location to
accumulator.
Ex: Assume 2050 memory location contains the 8-bit data is 25H into the accumulator.
Instruction: LDA 2050H.
 3-byte size.
 Direct addressing mode.
 13 T-state.
 4 machine cycle.
 No flags are affected.

 STA 16-bit address (Store Accumulator direct): It transfers the content stored in the
accumulator to addressed memory location.
Ex: Assume Accumulator contains 25H as 8-bit data. The instruction required to transfer
the contents of accumulator(25H) into the memory location of 2050H.
Instruction: STA 2050H.
 3-byte size.
 Direct addressing mode.
 13 T-state.
 4 machine cycle.
 No flags are affected.

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 LDAX Rp (Load accumulator indirect): The contents of memory location whose
address is in BC or DE register pair is loaded into the accumulator. Here Rp can be BC or
DE register pair.
[A] [[Rp]]
Ex: Assume the contents of B and C are 20H and 50H respectively and memory location
2050H has the 8-bit data is 30H. The instruction required to load this content into the
accumulator.
Instruction: LDAX B
 1-byte size.
 Register addressing mode.
 7 T-state.
 2 machine cycle.
 No flags are affected.
 STAX Rp (Store accumulator indirect): The content of accumulator is stored in
memory location whose address is in either BC or DE register pair. Here also Rpcan be
BC or DE register pair.
[[Rp]][A]
Ex: Assume accumulator content is 70H and registers D and E respectively. The
instruction required to store the content of accumulator into 2050H memory location.
Instruction: STAX D
 1-byte size.
 Register direct addressing mode.
 7 T-state.
 2 machine cycle.
 No flags are affected.
 LHLD 16-bit address [Load H and L direct]: The instruction copies the contents of the
memory location pointed out by the 16-bit address in register L and copies the contents of
the next memory location in register H.
[L][16-bit address]
[H][16-bit address + 1]
Ex: Assume the contents of memory location 2050H and 2051 are 42H and 32H. The
instruction required to store the data 42H are 32H into H and L register.
Instruction: LHLD 2050H
 3-byte size.
 Direct addressing mode.
 16 T-state.
 5 machine cycle.
 No flags are affected.

 SHLD 16-bit address (Store H and L direct): This instruction copies the contents of L
and H registers into two consecutive memory locations. The contents of L register are
stored in the memory location specified by the 16-bit address in the operand and the

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 contents of H register are stored in the next memory locations by incrementing the
operand.
[16-bit address] [L]
[16-bit address + 1] [H]
Ex: Assume the contents of H and L are 50H and 62H respectively. To store this data in two
consecutive memory location 2050H and 2051H.
Instruction: SHLD 2050H.

 3-byte size.
 Direct addressing mode.
 16 T-state.
 5 machine cycle.
No flags are affected.
 XCHG (Exchange H and L with D and E): The contents of H and L registers are
exchanged with the contents of D and E registers.
Ex: Assume H and L registers contents are 10H and 15H and the contents of D and E
registers are 20H and 25H respectively. The instruction required to exchange the HL and
DE register pair content.
Instruction: XCHG.
 3-byte size.
 Direct addressing mode.
 4 T-state.
 1 machine cycle.
 No flags are affected.

[ Nov / Dec 2018]

01. a) What is addressing mode? explain briefly the various addressing modes
of 8085Microprocessor
The various techniques used to specify the data (operand) for instruction to perform specific task
is called addressing mode
There are five types of addressing modes:

1. Direct addressing mode

2. Immediate addressing mode
3. Register addressing mode
4. Register indirect addressing mode
5. Implicit addressing mode
1. Direct addressing mode
In this mode the address of the data is given in the instruction itself.

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For example:
STA 9000H: Store the content of accumulator in memory location 9000H
9000HA
LDA 2050H: Load accumulator with the data of specified location 2050H
A2050H
[Link] addressing mode:
In this mode the operand is available in the instruction itself.
For example:
MVI A, 50H: Move immediately the given data 50H to the accumulator.
ADI,65H: Add immediately the given data 65H with the content of accumulator.
3. Register addressing mode:
In this mode the data is available in a general purpose register.
For example:
MOV A, C: Move the content of register to accumulator.
ADD B: Add the content of register B with the content of accumulator.
4. Register indirect addressing mode:
In this addressing mode the address of the data is stored in a register pair and that register pair is
specified in the instruction
For example:
STAX D: The content of accumulator is stored to memory location of DE register pair.
MOV A, M: Move the content of memory location pointed by HL register pair to accumulator.

5. Implicit addressing mode:

In this addressing mode the instructions operate only on one operandThese instructions assume
that the data is to be in accumulator. All these instructions are one-byte instruction.
For example:
CMA: Compliment the content of accumulator.
RAL: Rotate accumulator content left.

b) Explain the classification of 8085 microprocessor instruction based on word

size. Give example.
The 8085 microprocessoris an 8-bitmicroprocessor and it can handle 8-bit data at a time. Thus
the memory location of 8085 microprocessors is designed to accommodate 8-bit data. If 16-bit
are to stored, they are stored in two consecutive memory location.
Three types of instruction are:
1. 1-byte instruction

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 2. 2-byte instruction
3. 3-byte instruction.
1. One-byte instructions –
In 1-byte instruction, the opcode and the operand of an instruction are represented in one byte.
operand are internal register and are coded into the instruction. These instruction requires only
one memory location to store single byte in memory.
 Example-1:
Task- Copy the contents of accumulator in register B.

 Mnemonic- MOV B, A
 Opcode- MOV
 Operand- B, A
 Hex Code- 47H
 Binary code- 0100 0111

2. Two-byte instructions –
Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next 8 bits indicates the operand.
 Example-1:
Task- Load the hexadecimal data 32H in the accumulator.
 Mnemonic- MVI A, 32H
 Opcode- MVI
 Operand- A, 32H
 Hex Code- 3E
 32
 Binary code- 0011 1110
0011 0010
3. Three-byte instructions –
Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next two bytes specify the 16-bit address. The low-order address is represented in second
byte and the high-order address is represented in the third byte.
 Example-1:
Task- Load contents of memory 2050H in the accumulator.
 Mnemonic- LDA 2050H
 Opcode- LDA
 Operand- 2050H
 Hex Code- 3A
 50
 20
 Binary code- 0011 1010
 0101 0000

02. a) write assembly language program to subtract two 16- bit numbers.
Memory Label Mnemonics operand Machine comments
code

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Address
F000 START LXI H F102 21 02 F1 Point to 2nd number
F003 LXI D F100 11 00 F1 Point to 1st number
F006 LXI B FFF7 01 F7 FF Point to result
F009 LDAX D IA Get lower byte of 1st
number into
accumulator
F00A SUB M 96 Subtract lower byte
of 2nd number
F00B STAX B 02 Store lower byte
result in FFF7
FOOC INX H 23 Point to higher byte
of 2nd number
F00D INX D 13 Point to higher of 1st
byte number
F00El INX B 03 Point to higher byte
of result
F00F LDAX D IA Get higher byte of
1st number
F010 SUB M 9E Subtract higher byte
of 2nd number
F011 STAX B 02 Store higher byte
result in FFF8
F012 CALL UPDAD CDBC 06 -
F015 JMP DISP C3 12 F0 -

b) Explain the instructions DAA and DAD Rp.

DAA-Decimal Adjust Accumulator: The 8-bit result in accumulator is normally in binary form
represented by 2 Hexadecimal digits [00H to FFH]. The contents of the accumulator are changed
from a binary value to two 4-binary coded decimal [BCD] digits by using DAA instruction. This
instruction is used always immediately after any ADD instruction to convert the auxiliary carry
flag[AC] and carry flag[CY] to perform binary to BCD conversion.

DAD Rp – Add register pair to HL register pair: The 16 bit contents of the specified register pair
are added to the contents of the HL register pair and the sum is saved in the HL register pair. The
content of the source register pair is not altered.

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03. With an example, explain the logical instructions of 8085 microprocessors.
 AND Operations
ANA R [AND register ‘R’ with accumulator]: In this instruction each bit of the given
register contents are ANDed with each bit f the accumulator contents [bit by bit]. The result
is saved in the accumulator. It does not affect the contents of the given register
[A][A]AND[R]
Where, R can bean accumulator or any general purpose register [A,B,C,D,E,H or L].
Ex: Assume ‘A’ contain 54H and register B contains 82H and CY=1
Instruction: ANA B
 1-byte size
 Register addressing mode.
 4 T-state.
 1 machine cycle.
 Z, S and P flags are affected.

 OR Operations
ORA R[OR register with accumulator]: In this instruction each bit of the given register
contents are ORed with each bit of the accumulator contents[bit by bit]. The result is saved in the
accumulator. It does not affect the contents of the given register.
[A][A] OR [R]
Where, R can be an accumulator or any general purpose register[A,B,C,D,E,H or L].
Ex: Assume[A]=73H and [C]=C3H before execution of the instruction ORA C. After execution
of the instruction ORA C is:
Instruction ORA C
 1-byte size
 Register addressing mode
 4 T-state
 1 Machine cycle
 Z, S and P flags are affected

 EX-OR operation
XRA R:[Exclusive OR register with Accumulator]: In this instruction each bit of the
given register contents are XORed with each bit of the accumulator contents. The result is saved
in the accumulator. It does not affect the contents of the given register.
[A][A]XOR[R]
Where, R can be an accumulator or any general purpose register[A,B,C,D,E,H or L].
Ex: Assume [A]= 77H and register[D]=56H
Instruction: XRA D; [21H][77H]XOR[56H]
 1-byte size
 Register addressing mode
 4 T-state
 1 Machine cycle
 Z, S and P flags are affected

 Compare instructions

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 The microprocessor compares the contents of the accumulator with the data byte memory
contents by subtracting the data byte or register contentsfrom the accumulator.
CMP R:The contents of register R is subtracted from the contents of Accumulator but the result
is not stored. Result not stored [A]- [R].
Ex: Assume [A] =25H and Register [C] =09H. The instruction required to compare the contents
of register C from the Accumulator.
Instruction: CMP C
 1-byte size
 Register addressing mode
 4 T-state
 1 Machine cycle
 All flags are affected.

 CPI 8-bit data [Compare immediate 8-bit data with Accumulator]: The given 8-bit is
subtracted from the contents of accumulator but the result in not stored.

[A]- 8-bit data.

Ex: Assume [A]=23H. Compare the 8-bit data byte 2A from the accumulator.
Instruction: CPI 2AH
 2-byte size
 Immediate addressing mode
 7 T-state
 2 Machine cycle
 All flags are affected

 RLC (Rotate Accumulator Left): Each binary bit of the accumulator is rotated left by one bit
position. The high order bit (D7) is shifted to low-order bit(D0) as well as to the carry
flag(CY). Cy is modified according to bit D7.
Ex: Assume [A]=C6H and CY=0, before executing the RLC instructions.
 1-byte size
 Implicit addressing mode
 4 T-state
 1 Machine cycle +
 CY flag is affected.

 CMC (Complement the carry status): This instruction complements the carry flag.

CYCY

Ex: If CY=1 before the execution of CMC instruction, the carry flag will be reset (CY=0)
after the execution of this instruction. Similarly, if CY=0 before the execution of CMC
instruction, the carry flag will be set(CY=10 after the execution of this instruction.
 1-byte size
 Implicit addressing mode
 4 T-state
 1 Machine cycle
 CY flag is affected

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  STC (Set carry flag): The carry flag is set to 1.

CY1

 1-byte size
 Implicit addressing mode
 4 T-state
 1 Machine cycle
 CY flag is affected

UNIT III
[ Nov / Dec 2016]
01. Explain unconditional Jump Instructions.
The unconditional Jump instructions enable the programmer to set up continuous loops.
INSTRUCTION
Opcode Operand Description
JMP 16-bit Jump

 This is a 3-byte instruction.

 The second and third bytes specify the 16-bit memory address. The second byte specifies the
low-order and the third byte specifies the high-order memory address.
 Eg: To instruct the microprocessor to got to the memory location 2000H, and the mnemonics
and the machine code entered will be as:
 Machine Code Mnemonics
C3 JMP 2000H
00
20
02. Explain nesting of subroutine with an example.
The programming technique of a subroutine calling another subroutine is called nesting. This
process is limited only by the number of available stack locations. When a subroutine calls
another subroutine, all return addresses are stored on the stack.

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The main program calls the subroutine from location 2050H. The address of the next instruction,
2050H, is placed on the stack, and the program is transferred to the subroutine at 2090H.
Subroutine 1 calls Subroutine 2 from location 209AH. The address 209DH is placed on the
stack, and the program is transferred to Subroutine 2. The sequence of execution returns to the
main program.

[ Nov / Dec 2017]

01. What is stack? Explain PUSH and POP operation.
Stack is a group of memory locations in the R/W memory (RAM) defined by the
programmer for temporary storage of data bytes of the register pairs or program status
word(PSW) during the execution of program.
PUSH operation: PUSH is used to store register pair data onto stack.
Syntax
PUSH Reg. pair
The contents of the register pair designated in the operand are copied onto the stack in the
following sequence. The stack pointer register is decremented and the contents of the high
order register (B, D, H, A) are copied into that location. The stack pointer register is
decremented again and the contents of the low-order register (C, E, L, flags) are copied to
that location.
Example: PUSH B
Suppose B contains 34 and C contains 56 and Top of Stack (i.e. SP) =2000

34 56
The PUSH B instruction makes the following changes in memory as shown and top of stack
is decremented by 2.
i.e. Top Of Stack = SP – 2 = 2000 – 2 = 1998

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 Memory location Data
2000 34
1999 56
1998 POP operation:
POP is used to
extract data off stack and to store in register pair
Syntax
POP Reg. pair
The contents of the memory location pointed out by the stack pointer register are copied to
the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented
by 1 and the contents of that memory location are copied to the high-order register (B, D, H,
A) of the operand. The stack pointer register is again incremented by 1.

03. Explain CALL and RETURN operations in 8085.

CALL:
The call instructions allow the programmer to call the subroutine program. The address of the
subroutine program is specified with the CALL instruction. During the execution of CALL
instruction, the current contents of program counter are saved on the stack and the address of
subroutine is copied in the program counter. Like the jump instructions, the CALL instructions
are also of two types:
Unconditional Call Instructions: - The unconditional all instructions transfer the program
execution flow to the address of the subroutine program unconditionally.
Example:
CALL 16-bit address [Calls the addressed subroutine program]: When this instruction is
executed the current contents of program counter are saved on this stack and the address
specified with call instruction is copied into the program counter to transfer the program
sequence to the specified memory location of the subroutine program unconditionally.
[SP-1][PCH]
[SP-2][PCL]
and [PC]16-bit address

Conditional Call Instructions: - The conditional call instructions transfer the program
execution flow to the address of the subroutine program when certain condition is satisfied.
 CC 16-bit address [CALL Subroutine if Carry Flag is set]: The addressed subroutine will
be called by the microprocessor, if the Carry Flag is Set (CY=1) as per the result of the
preceding instruction.
[SP-1][PCH]
[SP-2][PCL]
and [PC]16-bit address, to transfer the program sequence to specified memory location of the
subroutine program.

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Return Instructions:The return instructions are used to end of the subroutine to transfers the
program sequence from subroutine program to the calling program unconditionally or
conditionally.
It is of two types:
 Unconditional return instruction:
1. RET (Return from Subroutine unconditionally): The RET instruction is used at the
end of the subroutine to transfers the program sequence from subroutine program to
the instructions of the main program next to the CALL instruction which called the
subroutine.
[PCL][SP]
[PCH][SP + 1]
[SP] [SP] + 2

 1-byte size.
 Register Indirect addressing mode.
 10 T-state.
 4 machine cycle.
 No flags are affected.
 Conditional return instruction: If the condition is true the execution of the conditional
return instruction takes 3 machine cycles and 12 T-states. If the condition is not true only
one Machine cycles and 6 T-states are required to execute the instructions.
[PCL][SP]
[PCH][SP + 1]
 1-byte size.
 Register Indirect addressing mode.
 12 T-state.
 3 machine cycle.
 No flags are affected.

UNIT-IV
[ Nov / Dec 2016]

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01. Compare memory mapped I/O and I/O mapped I/O.

02. a) What is an Interrupt? Explain the classification of interrupts.

Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

Interrupt are classified into following groups based on their parameter –

 Vector interrupt – In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.

 Non-Vector interrupt – In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.

 Maskable interrupt – In this type of interrupt, we can disable the interrupt by writing
some instructions into the program. For example: RST7.5, RST6.5, RST5.5.

 Non-Maskable interrupt – In this type of interrupt, we cannot disable the interrupt by

writing some instructions into the program. For example: TRAP.

 Software interrupt – In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e.
RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.

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  Hardware interrupt – There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.

b) Explain RIM instruction with bit pattern.

Read Interrupt Mask.
 It is a 1-Byte multi-purpose instruction. It is used for the following purposes.
 To check whether RST7.5, RST6.5, and RST5.5 are masked or not;
 To check whether interrupts are enabled or not;
 To check whether RST7.5, RST6.5, or RST5.5 interrupts are pending or not;
 To perform serial input of data.

Read Interrupt Mask instruction provides status information about interrupt system and this
instruction can be used for serial input of data. Through this RIM instruction, 8085 can know
which interrupt is masked or unmasked, etc. The contents of the Accumulator after the execution

of the RIM instruction provide this information.

[ Nov / Dec 2018]

01. Briefly explain the 8085 vectored interrupts.
• The instructions EI sets the interrupt enable flip-flop to enable the interrupt.
• The use of EI instructions enable all the interrupts.
• The instructions DI(Disable Interrupt is used to disable interrupt.
• In some case it can be situation to present the occurrence of interrupt when some task is
being performed in MPU. This is done by using DI instructions.
• The DI instructions resets the interrupt enable flip-flop and disable all the interrupt except
nonmaskable interrupt TRAP.
• When an interrupt line goes HIGH the processor completes its current instructions and same
PC on the stack.
It resets interrupt enable flip-flop before taking up ISS.
• All the interrupt except TRAP are disable by resetting the interrupt enable flip-flop.

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 UNIT-IV
[ Nov / Dec 2016]
01. Explain the functional block diagram of 8255 PPI.

Programmable peripheral interface 8255

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.

 It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We
can assign different ports as input or output functions.
 The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O under certain conditions as required. It can be used with almost
any microprocessor.

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  It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as
per the requirement.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.

 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.

These three ports are further divided into two groups, i.e. Group A includes PORT A and upper
PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed
in three different modes, i.e. the first mode is named as mode 0, the second mode is named as
Mode 1 and the third mode is named as Mode 2.

Operating Modes
8255A has three different operating modes –

 Mode 0 – In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit
ports. Each port can be programmed in either input mode or output mode where outputs
are latched and inputs are not latched. Ports do not have interrupt capability.

 Mode 1 – In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as
either input or output ports. Each port uses three lines from port C as handshake signals.
Inputs and outputs are latched.

 Mode 2 – In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals
for data transfer. The remaining three signals from Port C can be used either as simple
I/O or as handshake for port B.

Features of 8255A
The prominent features of 8255A are as follows –
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux’d.
 It is TTL compatible.
 It has improved DC driving capability.

02. write a note on interfacing devices.

 Interfacing can be defined as transferring data between microcontrollers and interfacing
peripherals such as sensors, keypads, microprocessors, analog to digital converters or ADC, LCD
displays, motors, external memories, even with other microcontrollers, some other interfacing
peripheral devices and so on or input devices and output devices. These devices that are

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 interfacing with 8051 microcontroller are used for performing special tasks or functions are called
as interfacing devices.
 The transfer of data between keyboard and microprocessor, and microprocessor and display
device is called Input Output Interfacing 8085 Microprocessor or I/O data transfer. This data
transfer is done with the help of I/O ports.
 Input Port :
 It is used to read data from the input device such as keyboard. The simplest form of input port is a
buffer. The input device is connected to the microprocessor through buffer as shown in the Fig.
4.28. This buffer is a tri-state buffer and its output is available only when enable signal is active.
 Output Port :
 It is used to send data to the output device such as display from the microprocessor. The simplest
form of output port is a latch.

[ Nov / Dec 2017]

01. Explain SIM and RIM Instructions.
SIM Instruction:
The individual masks for RST 5.5, RST 6.5, and RST 7.5 are manipulated using SIM instruction.
This instruction takes the bit pattern in the Accumulator and applies it to the interrupt to enable
or disable the specific interrupts. The accumulator is loaded by MVI A, data (data bits are as per
the requirements) instruction. The SIM instruction is then executed.
1. The bit D0is the mask for RST 5.5,bit D1is the mask for RST 6.5 and bit D2 is the mask
for RST 7.5.
 If the mask bit is 0, the interrupt is available.
 If the mask bit is 1, the interrupt is masked.
2. Bit D3(Mask Set Enable-MSE) is an control bit for bits D0, D1 and D2
 If it is set to 0 the mask is ignored and the old settings remain.
 If it is set to 1, the bits D0, D1and D2are effective and the new setting is applied.
3. The RST 7.5 is only the interrupt that has memory. Bit D4is additional control for RST
7.5. If D4=1, RST 7.5 is reset. This is used to override or ignore RST 7.5 without
servicing it.
4. Bits D7 and D6 of the accumulator are used for serial I/O and it do not affect the
interrupts.
 If D6 = 1, the bit D7 is used to transmit serial data.
 If D6 = 0, the bit D7 do not transmit serial data.
RIM (Read Interrupt Mask) instruction: This instruction will give the present status of the
interrupt. This instruction loads the accumulator with 8 bit data pattern and it shows the status of
each interrupt pin and mask. The RIM is a one byte instruction that can be used for the following
instructions:
 To read interrupt mask: This instruction loads the accumulator with 8-bit data pattern,
which indicates the current status of the interrupt mask. The bits D2-D6 show the current
setting of the mask for each of RST 7.5, RST 6.5, RST 5.5. Bit D3 shows whether the

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 maskable interrupt process is enabled or not. If D3=1, maskable interrupt process is
enabled.
To identify the pending interrupts: The bits D6 D5 D4 identify the pending interrupts. If bits are
1, the interrupt is pending.

[ Nov / Dec 2018]

01. Write short notes on:

DMA (Direct memory Access):
In a microprocessor, data transfers between I/O devices and memory will take place
through the microprocessor. The involvement of the processor slows down the data transfers
speed between I/O devices and memory because each instructions needs to defected and
executed. The transfer of data directly from I/O devices and memory without involvement of
microprocessor is called DMA, thus it is commonly used for high speed data transfer. In DMA,
the MPU releases the control of buses to a device called DMA controller. It uses two signals
named as HOLD and HLDA signals.

 HOLD signal: This is an active high input signal to the 8085 and active high output signal
to the DMA controller. This signal is operated by DMS controller to transfers the data
between two peripherals through DMA controller or without being routed through
microprocessor. This signal goes high when the DMA controller requesting to use the
address and data buses for data transfer between I/O devices to memory and vice-versa
without involvement of microprocessor.

 HLDA (Hold Acknowledge): This is an active high output signal to the microprocessor.
This signal goes high when the microprocessor surrenders the address and the data buses
to transfer data between the peripherals through DMA controller.

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