RAJKIYA ENGINEERING COLLEGE

KANNAUJ

VLSI Design Lab

(BEC 751)

Submitted By: - Submitted to: -

Name: Prince Kumar Mr. Om Singh

Roll No: 2208390300038 Dept. of Electronics Engineering
Electronics Engineering 4th Year
Semester: 7th
 INDEX
S. no Name of Experiment Experiment Date Signature
1. Design and analysis of basic of logic
Gates: AND, OR, NOT, NAND, NOR, 29 – 08 – 2025
XOR, XNOR.
2. Design and implementation of Half adder
and Full adder using CMOS logic. 05 – 09 – 2025

3. Design of 3-8 decoder using MOS

technology. 24 – 10 – 2025

4. Design a 4:1 Multiplexer.

05 – 11 – 2025
5. Design and implementation of Flip flop
circuit. 12 – 11 – 2025

6. Layout design of PMOS, NMOS

transistors. 19 – 11 – 2025

7. Layout design of CMOS inverter and its

analysis. 26 – 11 – 2025
 EXPERIMENT NO. 01
Aim: Design and analysis of basic of logic Gates: AND, OR, NOT, NAND, NOR, XOR,
XNOR.

Software Used: Tanner EDA (VLSI Suite) – S-Edit, T-Spice, Waveform Viewer, Tanner
Design.

Technology Used: Generic 250 nm Technology – Default Tanner EDA Educational PDK.

CMOS Implementation Concept

 PMOS transistors conduct when the input is LOW (0) and are used to build the pull-up
network (PUN) connecting the output to VDD.
 NMOS transistors conduct when the input is HIGH (1) and are used to build the pull-down
network (PDN) connecting the output to GND.
 By arranging NMOS and PMOS devices in series or parallel, different logic functions can be
realized.

AND Gate
 Output is HIGH only when all inputs are HIGH.
 CMOS realization uses series NMOS in PDN and parallel PMOS in PUN.
 Output goes LOW unless all NMOS are ON simultaneously.

Fig 1(a). 2-Input AND Gate Fig 1(b). 2-Input AND Gate Test Circuit
AND Gate Results:
Sample Input/ Output:
Input A: 0 0 1 1 0 0 1 1 …
Input B: 0 1 0 1 0 1 0 1 …
Output: 0 0 0 1 0 0 0 1 …
Waveform Output:

Fig 1(c). 2-Input And Gate Output Waveform

OR Gate
 Output is HIGH when any input is HIGH.
 CMOS uses parallel NMOS in PDN and series PMOS in PUN.

Fig 1(d) 2-Input OR Gate Fig 1(e). 2-Input OR Gate Test Circuit
OR Gate Results:
Sample Input/ Output:
Input A: 0 0 1 1 0 0 1 1 …
Input B: 0 1 0 1 0 1 0 1 …
Output: 0 1 1 1 0 1 1 1 …
Waveform Output:

Fig 1(f). 2-Input OR Gate Output Waveform

NOT Gate (Inverter)

 Single input gate; output is logical complement of input.
 CMOS uses one PMOS (pull-up) and one NMOS (pull-down).
 Forms the fundamental building block of all gates.

Fig 1(g). NOT Gate Circuit Fig 1(h). NOT Gate Test Circuit
NOT Gate Results:
Sample Input/ Output:
Input A: 0 1 0 0 1 0 1 1 1 1 …
Input B: 1 0 1 1 0 1 0 0 0 0 …

Waveform Output:

Fig 1(i). NOT Gate Output Waveform

NAND Gate
 Output is LOW only when all inputs are HIGH.
 CMOS uses series NMOS in PDN and parallel PMOS in PUN.
 It is a universal gate.

Fig 1(j). NAND Gate Circuit Fig 1(k). NAND Gate Test Circuit
NAND Gate Results:
Sample Input/ Output:
Input A: 0 0 1 1 0 0 1 1 …
Input B: 0 1 0 1 0 1 0 1 …
Output: 1 1 1 0 1 1 1 0 …
Waveform Output:

Fig 1(l). 2-Input NAND Gate Output Waveform

NOR Gate
 Output is HIGH only when all inputs are LOW.
 CMOS uses parallel NMOS in PDN and series PMOS in PUN.
 Also, a universal gate.

Fig 1(m). NOR Gate Circuit Fig 1(n). NOR Gate Test Circuit
NOR Gate Results:
Sample Input/ Output:
Input A: 0 0 1 1 0 0 1 1 …
Input B: 0 1 0 1 0 1 0 1 …
Output: 1 0 0 0 1 0 0 0 …
Waveform Output:

Fig 1(o). 2-Input NOR Gate Output Waveform

XOR Gate
 Output is HIGH when inputs are different.
 CMOS requires combination of transmission gates or optimized complementary
networks.
 Implemented using a mix of series–parallel NMOS/PMOS networks.

Fig 1(p). XOR Gate Circuit Fig 1(q). XOR Gate Test Circuit
XOR Gate Results:
Sample Input/ Output:
Input A: 0 0 1 1 0 0 1 1 …
Input B: 0 1 0 1 0 1 0 1 …
Output: 0 1 1 0 0 1 1 0 …
Waveform Output:

Fig 1(r). 2-Input XOR Gate Output Waveform

XNOR Gate
 Output is HIGH when inputs are same.
 Implemented as inverted XOR, commonly realized using XOR network followed by a
CMOS inverter.

Fig 1(s). XNOR Gate Circuit Fig 1(t). XNOR Gate Test Circuit
XNOR Gate Results:
Sample Input/ Output:
Input A: 0 0 1 1 0 0 1 1 …
Input B: 0 1 0 1 0 1 0 1 …
Output: 1 0 0 1 1 0 0 1 …
Waveform Output:

Fig 1(u). 2-Input XNOR Gate Output Waveform

 EXPERIMENT NO. 02
Aim: Design and implementation of Half adder and Full adder using CMOS logic.

Software Used: Tanner EDA (VLSI Suite) – S-Edit, T-Spice, Waveform Viewer, Tanner
Design.

Technology Used: Generic 250 nm Technology – Default Tanner EDA Educational PDK.

1. Half Adder
A Half Adder is a combinational circuit that adds two single-bit binary inputs: A and B.
It produces two outputs:
 SUM = A ⊕ B
 CARRY = A · B

CMOS Implementation
 SUM is realized using a CMOS XOR gate, built using complementary pull-up/pull-down
transistor networks.
 CARRY is implemented using a CMOS AND gate constructed with series NMOS in PDN
and parallel PMOS in PUN.
 The design is drawn in S-Edit, and transistor-level behavior is verified through T-Spice
simulation.

Fig 2(a). CMOS – Half Adder Circuit.

 Fig 2(b). Half Adder Test Circuit.

Half Adder Results:

Sample Input/ Output:
Input A: 0 0 1 1 0 0 1 1 …
Input B: 0 1 0 1 0 1 0 1 …
Out S: 0 1 1 0 0 1 1 0 …
Out C: 0 0 0 1 0 0 0 1 …

Waveform Output:

Fig 2€. Half Adder Output Waveform

2. Full Adder
A Full Adder adds three single-bit inputs: A, B, and Cin (carry-in).
It produces:
 SUM = A ⊕ B ⊕ Cin
 Cout = (A · B) + (Cin · (A ⊕ B))

CMOS Implementation
 The SUM output is built using two cascaded CMOS XOR gates:
o First XOR generates (A ⊕ B).
o Second XOR combines this with Cin.
 The CARRY (Cout) output is implemented using CMOS AND and OR structures:
o A·B uses series NMOS / parallel PMOS.
o Cin·(A ⊕ B) uses another AND network.
o Outputs are combined using a CMOS OR gate.
 The complete transistor-level schematic is created in S-Edit, and timing correctness is
verified using T-Spice and waveform analysis.

Fig 2(d). CMOS – Full Adder Circuit.

 Fig 2(e). Full Adder Test Circuit.

Full Adder Results:

Sample Input/ Output:
Input A: 0 0 0 0 1 1 1 1 0 0 0 0 …
Input B: 0 0 1 1 0 0 1 1 0 0 1 1 …
Input C: 0 1 0 1 0 1 0 1 0 1 0 1 …
Out S: 0 1 1 0 1 0 0 1 0 1 1 0 …
Out C: 0 0 0 1 0 1 1 1 0 0 0 1 …
Waveform Output:

Fig 2(f). Full Adder Output Waveform

 EXPERIMENT NO. 06
Aim: Design of 3-8 decoder using MOS technology.

Software Used: Tanner EDA (VLSI Suite) – S-Edit, T-Spice, Waveform Viewer, Tanner
Design.

Technology Used: Generic 250 nm Technology – Default Tanner EDA Educational PDK.

Theory:
A 3-to-8 decoder is a combinational digital circuit that converts 3 input binary lines into 8 unique
output lines. For every possible input combination, exactly one output becomes HIGH, while
all others remain LOW. It is widely used in memory address decoding, microprocessor control,
data selection, and enabling operations.
Decoder Logic
For inputs A2, A1, A0, the outputs are:
 Y0 = 𝑨2 𝑨1 𝑨0
 Y1 = 𝑨2 𝑨1 𝑨0
 Y2 = 𝑨2 𝑨1 𝑨0
 Y3 = 𝑨2 𝑨1 𝑨0
 Y4 = 𝑨2 𝑨1 𝑨0
 Y5 = 𝑨2 𝑨1 𝑨0
 Y6 = 𝑨2 𝑨1 𝑨0
 Y7 = 𝑨2 𝑨1 𝑨0
This is achieved using combinations of NOT, AND, and NAND logic at the transistor level.

CMOS (MOS) Implementation

In MOS/CMOS technology, the decoder is designed using NMOS and PMOS transistors
arranged in pull-up (PUN) and pull-down (PDN) networks.

1. Inverters (NOT Gates)

 Used to generate complemented inputs A2', A1', A0'.
 Implemented using one PMOS (pull-up) and one NMOS (pull-down).

2. AND Gate Realization

To generate each output Yi, a 3-input AND gate is required.
In CMOS:
 NMOS transistors are placed in series in the PDN for AND logic.
  PMOS transistors are placed in parallel in the PUN.

3. NAND-Based Realization (Optimized)

A practical CMOS design often uses:
 3-input NAND gate (series NMOS, parallel PMOS)
 Followed by an inverter
This reduces transistor count and improves speed.

Fig 6(a). CMOS – 3x8 Decoder Circuit.

Fig 6(b). 3x8 Decoder Test Circuit.

Results:
Sample Input/ Output:
Input A: 0 0 0 0 1 1 1 1 0 0 0 0 …
Input B: 0 0 1 1 0 0 1 1 0 0 1 1 …
Input C: 0 1 0 1 0 1 0 1 0 1 0 1 …
Out I: I0 I1 I2 I3 I4 I5 I6 I7 I8 …

Waveform Output:

Fig 6(c). 3x8 Decoder Output Waveform

 EXPERIMENT NO. 07
Aim: Design a 4:1 Multiplexer.

Software Used: Tanner EDA (VLSI Suite) – S-Edit, T-Spice, Waveform Viewer, Tanner
Design.

Technology Used: Generic 250 nm Technology – Default Tanner EDA Educational PDK.

Theory:
A 4:1 MUX selects one of four inputs D0–D3 to the output Y based on two select lines S1, S0:
𝑌 = 𝐷 𝑆‾ 𝑆‾ + 𝐷 𝑆‾ 𝑆 + 𝐷 𝑆 𝑆‾ + 𝐷 𝑆 𝑆

Truth table:
 S1S0 = 00 → Y = I0
 S1S0 = 01 → Y = I1
 S1S0 = 10 → Y = I2
 S1S0 = 11 → Y = I3

CMOS Implementation
Transmission-gate MUX
 Use 4 transmission gates (NMOS + PMOS pairs) connecting D 0–D3 to Y.
 Each TG is enabled by an active enable signal (E0...E3) derived from S1, S0 (via
inverters/2→4 decoder).
 Advantages: low on-resistance, near-rail output, fewer transistors than static CMOS AND–
OR implementation.

Pin Placement:

Select Line : S0 and S1

Data Line : I0, I1, I2 and I3
Output : Out
 Fig 7(a). CMOS – 4x1 Multiplexer Circuit Diagram.

Fig 7(b). 4x1 Multiplexer Test Circuit Diagram.

Test Presets:
I0 = 1 (HIGH)
I1 = 0 (LOW)
I3 = 1 (HIGH)
I4 = 0 (LOW)
Results:
Sample Input/ Output:
Input S0: 0 0 1 1 0 0 1 1 …
Input S1: 0 1 0 1 0 1 0 1 …
Out : 1 0 1 0 1 0 1 0 … (As per test preset)
Waveform Output:

Fig 2(f). 4x1 Multiplexer Output Waveform

 EXPERIMENT NO. 08
Aim: Design and implementation of Flip flop circuit.

Software Used: Tanner EDA (VLSI Suite) – S-Edit, T-Spice, Waveform Viewer, Tanner
Design.

Technology Used: Generic 250 nm Technology – Default Tanner EDA Educational PDK.

Theory:
A flip-flop is a bistable storage element that stores one bit of information. Unlike level-sensitive
latches, an edge-triggered flip-flop updates its output only on a clock edge (rising or falling),
making it the fundamental memory element in synchronous digital systems.

CMOS Implementation (D Flip-Flop - using transmission gates)

The D Flip-Flop was implemented at the transistor level in Tanner EDA using CMOS technology
from the 250 nm PDK. The circuit is built using two latches arranged in a master–slave
configuration, where each latch is formed using a pair of cross-coupled CMOS inverters. The input
signal D is first connected to a transmission gate made from one NMOS and one PMOS transistor.
This transmission gate is driven by the clock signals CLK and CLK̅, so that the input is allowed
to pass only when the clock is high. When CLK = 1, the transmission gate conducts and the master
latch becomes transparent, allowing the value of D to propagate and get stored inside the cross-
coupled inverter pair on the left side of the schematic. When the clock goes low, the transmission
gate switches off and the master latch holds the stored value through the feedback loop created by
its inverters.

The slave latch on the right side of the circuit is constructed in the same way as the master latch,
using another pair of interconnected CMOS inverters. Its transmission gate is controlled by the
opposite clock phase, CLK̅, so it becomes active only when the clock is low. When CLK = 0, the
slave latch receives the stored value from the master latch and updates its output nodes. When
CLK goes high again, this latch also becomes closed and preserves its output state. Because one
latch is transparent only when the other is closed, the combination of both forms an edge-triggered
D Flip-Flop where the output changes only at the clock transition.

The output Q is taken from the slave latch, and the complementary output Q̅ is obtained from the
opposite internal node of the same latch. All PMOS devices in the circuit are connected to VDD,
and all NMOS devices are tied to ground in accordance with standard CMOS structure. After
drawing the schematic in S-Edit, the design was simulated using T-Spice, and the waveform viewer
confirmed that the output Q follows the input D only during the correct clock phase, verifying the
proper operation of the implemented flip-flop circuit.

Fig 8(a). CMOS – D - Flip Flop Circuit Diagram.

Fig 8(b). D – Flip Flop Test Circuit Diagram.

Results:
Sample Input/ Output:
Input C: 0 1 0 1 0 1 0 1 …
Input D: 0 1 0 1 0 0 1 1 …
Out Q: 1 1 1 1 1 0 1 1 …
Out QB: 1 0 1 0 1 1 1 0 …

Waveform Output:

Fig 8(c). D – Flip Flop Output Waveform

 EXPERIMENT NO. 09
Aim: Layout design of PMOS, NMOS transistors.

Software Used: Tanner EDA (VLSI Suite) – L-Edit, T-Spice, Waveform Viewer, Tanner
Design.

Technology Used: Generic 250 nm Technology – Default Tanner EDA Educational PDK.

Theory:
PMOS and NMOS are the basic building blocks of CMOS technology. An NMOS transistor is
formed by creating n-type diffusion regions in a p-type substrate, while a PMOS transistor is
created using p-type diffusion inside an n-well. The gate terminal is formed by polysilicon
crossing over the diffusion region, and source/drain contacts are added through metal layers. In
layout design, proper spacing rules, well formation, contact placement, and design rule checks
(DRC) must be followed to ensure correct device functionality and manufacturability.

Implementation:
The layout of both transistors was created using L-Edit with the 250 nm Tanner PDK. For the
NMOS, the design begins by defining the p-type substrate region, followed by placing the n+
diffusion for source and drain. A polysilicon strip is drawn perpendicular to the diffusion region
to form the gate. Contacts are placed on the diffusion and connected using metal-1 routing. For the
PMOS, an n-well is drawn first, and inside this well, p+ diffusion regions are created for the
source and drain. The polysilicon gate is again placed across the diffusion. Metal layers and
contacts are added similarly. Both layouts were checked using DRC and LVS, ensuring that the
transistors match the schematic design rules. After extraction, the devices were simulated using T-
Spice to verify electrical behaviour.

PMOS Design:
The PMOS transistor was designed in L-Edit using the 250 nm Tanner educational PDK. The
layout begins by creating a large n-well region, which forms the body of the PMOS device. Inside
this n-well, two p+ diffusion regions are placed on the left and right sides to act as the source (S)
and drain (D) terminals. A polysilicon gate is drawn vertically, crossing the diffusion region to
define the transistor channel. This crossing of polysilicon over p+ diffusion forms the active gate
area of the PMOS.
 S = Source
G = Gate
D = Drain

Layer Sequence:
Contact VIA
Metal 1
Active Region
P_Implant
N_Well
Fig 9(a). PMOS Layout Design.

Metal contacts are added on both the source and drain diffusion regions, and these contacts are
connected to Metal-1 to allow external routing. A contact is also placed over the polysilicon gate
to provide a metal connection for the gate terminal (G). Proper design rules for well enclosure,
diffusion spacing, gate length, and contact placement were followed based on the 250 nm
technology requirements. After drawing the layout, DRC was performed to ensure rule
compliance, and the extracted view confirms the correct parameters of the PMOS device.

NMOS Design:
The NMOS transistor layout was created in L-Edit using the Tanner 250 nm PDK. The device is
placed directly inside a p-type substrate, since NMOS does not require an additional well. The
n+ diffusion regions for the drain (D) and source (S) are drawn horizontally on the left and right
sides, and these regions form the active terminals of the NMOS. A polysilicon gate is drawn
vertically across the diffusion area, and its crossing over the n+ diffusion defines the transistor
channel. This poly strip acts as the gate (G) terminal.

S = Source
G = Gate
D = Drain

Layer Sequence:
Contact VIA
Metal 1
Active Region
N_Implant

Fig. 9(b) NMOS Layout Design.

Contacts are added on both the drain and source diffusions, and these contacts are connected to
Metal-1 for routing. A separate contact is also placed on the polysilicon gate to allow its metal
connection. The layout follows all the required 250 nm design rules for diffusion width, poly gate
length, contact spacing, and substrate enclosure. After completing the structure, DRC was
performed to ensure no rule violations, and the extracted view confirms that the NMOS device
parameters are correct according to the technology specifications.

Results:
The transistor layouts for both PMOS and NMOS were successfully designed using the Tanner
250 nm educational PDK in L-Edit. All layout components—including diffusion regions,
polysilicon gates, contacts, and metal connections—were placed according to the design rules.
After completing the drawings, DRC (Design Rule Check) was performed, and no rule violations
were found, confirming that the layouts comply with the 250 nm technology requirements. The
layouts were then extracted and simulated, and the electrical characteristics matched the expected
behaviour of standard CMOS transistors. Thus, the PMOS and NMOS layouts are verified to be
correct and ready for use in higher-level circuit design.
 EXPERIMENT NO. 10
Aim: Layout design of CMOS inverter and its analysis

Software Used: Tanner EDA (VLSI Suite) – L-Edit, T-Spice, Waveform Viewer, Tanner
Design.

Technology Used: Generic 250 nm Technology – Default Tanner EDA Educational PDK.

Theory:
A CMOS inverter consists of two complementary MOSFETs:
 PMOS transistor connected to the supply voltage 𝑉
 NMOS transistor connected to ground

Their gates are tied together to form the input, and their drains are connected to form the output.
When the input is:
 Low (0): PMOS ON, NMOS OFF → Output = High (1)
 High (1): PMOS OFF, NMOS ON → Output = Low (0)

Thus, the CMOS inverter provides an inverted output of the input signal.

Implementation:
The CMOS inverter layout was created in L-Edit using the Tanner 250 nm educational PDK. The
circuit consists of one PMOS placed in the n-well region at the top and one NMOS placed in the
p-type substrate at the bottom. Both transistors are vertically aligned so that their polysilicon
gate (red layer) can act as a shared input terminal IN, simplifying routing and reducing area. The
PMOS source is connected to the VDD rail using Metal-1, while the NMOS source is connected
to the GND rail. Their drains are connected together through Metal-1 to form the output node
OUT, matching the standard CMOS inverter structure.

Fig 10(a). CMOS Inverter Fabrication.

Diffusion regions (p+ for PMOS, n+ for NMOS) are properly enclosed within their respective
wells/substrate. Contacts are added on the source, drain, and gate regions, and Metal-1 is used to
complete all interconnections. The layout follows all 250 nm design rules for spacing, contact
enclosure, well boundaries, and gate length. After drawing the inverter, DRC was run to ensure
there were no violations, and LVS verified that the layout matched the intended schematic. The
extracted netlist was simulated in T-Spice, and the waveform confirmed correct inverter
behaviour, where the output switches to logic high when the input is low and switches to logic
low when the input is high.

VDD = +5v Input

GND = 0v Input
IN = Inverter Input Pin

OUT = Inverter Output Pin

Fig 10(b). CMOS Inverter Layout Design.

T-Spice Test Bench:

M1 OUT IN GND 1 NMOS25 l=6.25e-07 w=5.5e-07 ad=9.9e-13 as=8.8e-13 pd=4.7e-06 ps=4.3e-06 $ (-
0.3 -4.625 0.325 -4.075)
M2 OUT IN VDD 2 PMOS25 l=6.25e-07 w=5.5e-07 ad=9.9e-13 as=8.8e-13 pd=4.7e-06 ps=4.3e-06 $ (-
0.3 -0.3 0.325 0.25)

.tran 10n 200n

.lib
"C:\Users\Prince\Documents\TannerEDA\TannerTools_v2019.2\Process\Generic_250nm\Models\Generic
_250nm.lib" TT
.print tran .lib
"C:\Users\Prince\Documents\TannerEDA\TannerTools_v2019.2\Process\Generic_250nm\Models\Generic
_250nm.lib" TT v(OUT,GND)
.print tran .print tran .lib
"C:\Users\Prince\Documents\TannerEDA\TannerTools_v2019.2\Process\Generic_250nm\Models\Generic
_250nm.lib" TT v(OUT,GND)v(IN,GND)
VIN IN GND dc 5 BIT ({10110010101})
VDD VDD GND 5
.END
Results:

Fig 10(c). CMOS Inverter T-Spice Simulation Results.

Fig 10(d). CMOS Inverter Input-Output Waveform.