Analog and Digital Electronics

CHAPTER – 3

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 CHAPTER – 3
SYLLABUS

Sequential Circuits – Basic Flip – flop & Latch, Flip – flops - SR, JK, D,
T and JK Master – slave Flip Flops, Registers (SISO, SIPO, PIPO, PISO)
Ring counter, Johnson counter Basic concept of Synchronous and
Asynchronous counters (detail design of circuits excluded), Design of Mod
N Counter.

Sequential Circuits
Sequential circuits are digital circuits that store and use previous state
information to determine their next state. They are commonly used in digital
systems to implement state machines, timers, counters, and memory elements
and are essential components in digital systems design.
 ➢ The memory elements in sequential circuits can be implemented using
flip-flops, which are circuits that store binary values and maintain
their state even when the inputs change.

Sequential circuit is a combinational logic circuit that consists of inputs

variable (X), logic gates (Computational circuit), and output variable (Z).

A combinational circuit produces an output based on input variables only,

but a sequential circuit produces an output based on current input and
previous output variables. That means sequential circuits include memory
elements that are capable of storing binary information. That binary
information defines the state of the sequential circuit at that time. A latch
capable of storing one bit of information.
As shown in the figure, there are two types of input to the combinational
logic :

1. External inputs which are not controlled by the circuit.

2. Internal inputs, which are a function of a previous output state.

Secondary inputs are state variables produced by the storage elements,

whereas secondary outputs are excitations for the storage elements.

Types of Sequential Circuits

There are two types of sequential circuits

Asynchronous Sequential Circuit

These circuits do not use a clock signal but uses the pulses of the inputs.
These circuits are faster than synchronous sequential circuits because there is
clock pulse and change their state immediately when there is a change in
the input signal. We use asynchronous sequential circuits when speed of
operation is important and independent of internal clock pulse.

But these circuits are more difficult to design and their output is uncertain.
Synchronous Sequential Circuit

These circuits uses clock signal and level inputs (or pulsed) (with
restrictions on pulse width and circuit propagation). The output pulse is the
same duration as the clock pulse for the clocked sequential circuits. Since
they wait for the next clock pulse to arrive to perform the next operation,
so these circuits are bit slower compared to asynchronous. Level output
changes state at the start of an input pulse and remains in that until the
next input or clock pulse.

We use synchronous sequential circuit in synchronous counters, flip flops,

and in the design of MOORE-MEALY state management machines. We use
sequential circuits to design Counters, Registers, RAM, MOORE/MEALY
Machine and other state retaining machines.

Latch and Flip-Flop

Flip-flops and latches are two kinds of memory circuits used in electronics.
The main difference between them is how they react to changes. A latch
changes its output whenever its input changes. This means it's always ready
to respond. On the other hand, a flip-flop only changes its output at
specific moments, like when its control signal goes from low to high. This
makes flip-flops more stable in many situations.

In simple terms, latches are always alert to changes, while flip-flops only
act at certain times.

Flip Flop

Flip-flop is a basic digital memory circuit, which stores one bit of

information. Flip flops are the fundamental blocks of most sequential
circuits. It is also known as a bistable multivibrator or a binary or one-bit
memory. Flip-flops are used as memory elements in sequential circuits.

Latch

Latch is an electronic device, which changes its output immediately based

on the applied input. It is used to store either 1 or 0 at any specified time.
It consists of two inputs namely "SET" and RESET and two outputs,
which are complement to each other.
Difference Between Flip-Flop and Latch
Flip-Flop Latch
Flip-flop is a bistable device i.e., it has Latch is also a bistable device
two stable states that are represented as whose states are also represented
0 and 1. as 0 and 1.
It is a edge triggered device. It is a level triggered device.
Gates like NOR, NOT, AND, NAND These are also made up of
are building blocks of flip flops. gates.
They are classified into asynchronous There is no such classification
or synchronous flipflops. in latches
Flip-flop always have a clock signal Latches doesn't have a clock
signal
Flip-flop can be build from Latches Latches can be build from gates
ex: D Flip-flop, JK Flip-flop ex: SR Latch, D Latch

SR Latch
S-R latches i.e., Set-Reset latches are the simplest form of latches and are
implemented using two inputs: S (Set) and R (Reset). The S input sets the
output to 1, while the R input resets the output to 0. When both S and R
inputs are at 1, the latch is said to be in an "undefined" state. They are
also known as preset and clear states. The SR latch forms the basic
building blocks of all other types of flip-flops.

Truth Table of SR Latch

S R Q Q'

0 0 Latch Latch

0 1 0 1

1 0 1 0

1 1 0 0
Logic Diagram of SR Latch

SR Latch is a logic circuit with:

➢ 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.

➢ 2 input S for SET and R for RESET

➢ 2 output Q, Q'.

The below logic diagram represents the SR latch using NAND gate.

The below logic diagram represents SR latch using NOR Gate.

SR Flip-Flop
It is a Flip Flop with two inputs, one is S and the other is R. S here
stands for Set and R here stands for Reset. Set basically indicates set the
flip flop which means output 1 and reset indicates resetting the flip flop
which means output 0. Here, a clock pulse is supplied to operate this flip-
flop, hence it is a clocked flip-flop.

Construction of SR Flip Flop

We can construct SR flip flop with two ways, one is with 2 NOR Gates +
2 AND Gates and other is with 4 NAND Gates.

SR Flip Flop Construction using 2 NOR + 2 AND Gates:

SR Flip Flop Construction using 4 NAND Gates

SR Flip Flop using NAND Gate

Basic Block Diagram of SR Flip Flop

The basic block diagram contains S and R inputs, and between them is
clock pulse, Q and Q' is the complemented outputs.

SR Flip Flop basic Block diagram

Working of SR Flip Flop

➢ Case 1 : Let's say, S=0 and R=0 , then output of both AND gates
will be 0 and the value of Q and Q' will be same as their previous
value, i.e, Hold state.

➢ Case 2 : Let's say, S=0 and R=1 , then output of both AND gates
will be 1 and 0, correspondingly the value of Q will be 0 as one of
 input is 1 and it is a NOR gate so it will ultimately gives 0, hence
Q gets 0 value, similarly Q' will be 1.

➢ Case 3 : Let's say, S=1 and R=0 , then output of both AND gates
will be 0 and 1, correspondingly the value of Q' will be 0 as one of
input to NOR gate is 1, so output will be 0 ultimately and this 0
value will go as input to upper NOR gate, and hence Q will become
1.

➢ Case 4 : Let's say, S=1 and R=1 , then output of both AND gates
will be 1 and 1 which is invalid, as the outputs should be
complement of each other.

Truth Table of SR Flip Flop

Here, S is the Set input, R is the reset input,Qn+1 is the next state and
State tells in which state it enters
Applications of SR Flip Flop

➢ Register : SR Flip Flop used to create register. Designer can create

any size of register by combining SR Flip Flops.
 ➢ Counters : SR Flip Flops used in counters . Counters counts the
number of events that occurs in a digital system.

➢ Memory : SR Flip Flops used to create memory which are used to

store data, when the power is turned off.

➢ Synchronous System : SR Flip Flop are used in synchronous system

which are used to synchronize the operation of different component.

JK Flip-Flop
It is one kind of sequential logic circuit which stores binary information in
bitwise manner. It consists of two inputs and two outputs. Inputs are Set(J)
& Reset (K) and their corresponding outputs are Q and Q'. JK flipflop has
two modes of operation which are synchronous mode and asynchronous
mode. In synchronous mode, the state will be changed with the clock(clk)
signal, and in asynchronous mode, the change of state is independent from
its clock signal. Let's see its diagram structure.
The JK flip flop diagram above represents the basic structure which consists
of Clock (CLK), Clear (CLR), and Preset (PR).

Below is the circuit diagram of JK Flip Flop. Two 3-input NAND gates are
used in place of the original two 2-input AND gates. The outputs at Q and
Q' are coupled to each gate's third input. Since the two inputs are now
interlocked, the SR flip-flop's cross-coupling enables the previously invalid
condition of (S = "1", R = "1") to be employed to perform the "toggle
action".

JK Flip Flop

In a circuit "set", the bottom NAND gate interrupts the J input coming
from the "0" position of Q'. In the "RESET" state, the top NAND gate
interrupts the K input coming from the 0 positions of Q. We can use Q
and Q' to control the input because they are always different. The flip flop
is toggled according to the truth table when both inputs "J" and "K" are set
to 1.

Applications of JK Flip-Flop

➢ Counters: Counters are very essential components for the application

of frequency dividers and event sequencers where there is a need of
storing and propagating the count value. We can design binary
synchronous and asynchronous counters using JK-flipflop.

➢ Shift Registers: For data storage and manipulation, serial-to-parallel or

parallel-to-serial data conversion the shift registers are widely used.
Registers can store and shift the binary data in a sequential manner.
We can design it by JK-flipflops.

➢ Memory Units: JK-flipflop itself act as a memory unit to store binary

information. By making a sequential chain of JK-flipflops we can use
it even as RAM.

Advantages of JK Flip-Flop

➢ Versatility: As discussed above, JK-flipflops can be used as a basic

memory element or a primary building block of further complex
memory design. It is very much adaptive as it can be operated in
both synchronous and asynchronous modes.

➢ Toggle Functionality: The application which are required to get

output as its complement of input that also can be developed by JK-
flipflops as when J=K=1 it triggers toggle state which gives output
which is complement with it's each clock pulse.
 ➢ Error Detection and Correction: We can use a complex circuit built
by JK-flipflops which can detect and correct information during data-
transmission.

Disadvantages of JK Flip-Flop

➢ Complexity: Compared to other types of flipflops(D,T, SR), JK

flipflop requires additional logic gates to implement which consumes
extra memory resources and increases complexity to operate.

➢ Propagation Delay: This is the major problem present in JK-FF.

Propagation delay results a timing delay in certain application which
are time-flow sensitive.

➢ Race Problem: This issue arises when the clock input's timing pulse
isn't given enough time to turn "Off" before the output Q's state is
altered.

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FULL SYLLABUS NOTES !!!

✓ CHAPTER 1 Colourful Notes
✓ CHAPTER 2 Important Questions Marked With
✓ CHAPTER 3 Syllabus Wise Notes
✓ CHAPTER 4
FULL SYLLABUS COVERED !!!
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