MICROPROCESSOR INTERLOCKINGS:
DESIGNING NETWORK EQUATIONS
By Albert M. Santini
Assistant Director, Signals
MTA Metro North Railroad
ABSTRACT a full universal four track interlocking using
this method is included as a model.
Railroad Signal Systems have evolved
over the years t o be one of the safest
systems in the Transportation Industry. With I NTRODUCTI0N
the expanding use of microprocessor based
interlocking systems, the implementation of Even during the days of the first Electro-
signalling logic using Boolean equations mechanical interlockings, relay networks
needs t o be done with methods that retain were elegantly used t o implement route
the inherent safety in designs previously check, home, distant and other basic
achieved using vital relays. Most circuits interlocking functions. The familiar relay
used in signalling can be represented quite style network has remained essentially
well using Boolean logic. However, the unchanged t o the present day. There are
author has found that networks, such as many features that are inherent in the relay
route check, home, and distant networks network that has made this such an elegant
used extensively in Railroad Signalling, pose implementation for all these years. Some of
a unique set of problems when they are these features are listed below.
represented in Boolean logic using
conventional methods. These problems are Relay networks are drawn and laid out in
especially severe when implementing the much the same manner as the physical
larger three or four track interlockings. track layout.
Networks are easy t o design, understand
This paper describes a new technique and modify.
that can be used t o program vital and non- Errors found in testing are almost self-
vital microprocessor systems using Boolean revealing. A wrong contact used
logic. This technique implements the somewhere in the network will reveal
traditional relay networks by using what are itself for each route that traverses that
called network node equations. A discussion point in the network.
of the problems using conventional methods Changes involving tracks or switches
is included. The network node equation affecting the interlocking configuration
method is introduced, and the solutions t o can be implemented quickly and easily.
these problems are demonstrated. The
method described allows the reader t o In all of the new microprocessor based
program networks in a fashion that retains all interlockings that are being installed, the
the advantages of the relay style network. logic for these new interlockings is
An example of an actual implementation of implemented using Boolean expressions. The
0-7803-3854-5/97/$10.000 1997 IEEE
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CP 1
-@ EAST
1W TRACK 1
I 4E
Figure 1- interlocking Arrangement
common method of writing these are labeled based on the tracks they are
expressions for the networks has been t o between, always from West t o East. For
construct an equation representing each of instance, a switch that takes you from track
the network relays. All paths through the 3 t o track 1 in the Eastbound direction is
network must then be included for each called the 31 switch. Track circuits are also
expression representing the network relays. labeled after the track they are on. For
While it is true that the relay-based circuit multiple track circuits on the same track, as
can be translated directly into its Boolean is the case here, the track number followed
equivalent representation, practically, this by a letter beginning with " A " is used, with
works well for only the simplest of relay letters incrementing in the Eastward
circuits, and rapidly becomes very unwieldy direction.
for complex circuits such as the networks.
Figure 2 shows what a relay-based route
The n e w method discussed in this paper, check network might look like for the
called the Node Equation Method, allows one interlocking configuration in Figure 1. The
t o maintain all the features t h a t are inherent route check network will be used t o
in relay networks. demonstrate the node equation method. The
same methods described within can be used
RELAY NETWORKS on all other networks in any microprocessor
based interlocking.
Figure 1 shows the arrangement of a
typical four track universal interlocking. This Referring t o Figure 2, the layout of the
interlocking will be used for discussion network generally follows the geographic
purposes throughout the paper and as an layout of the interlocking. A n exception here
example t o demonstrate the Node Equation is where the 12 and 21 crossovers are
Method. Metro-North standard practice is t o represented. A route over both these
name the signals after the track and the crossovers reverse is called an "over and
direction of traffic they govern. Switches back" or runaround route. These routes
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%ROUTE CHECK EQUATIONS\
ASSIGN((3EEFK*-3WRCSK*3ETBK*l3RWCK+lEEFK*-lWRCSK*lETBK*l3NWCK)*l2NWCK
+(2EEFK*-ZWRCSK*ZETBK*24NWCK+4EEFK*-4WRCSK*24RWCK)*l2RWCK
*13NWCK)*21NWCK*31NWCK*lEGZ TO 1ERCSR;
ASSIGN ((3WWFK*-3ERCSK*3WTBK*3lRWCK+l~FK*-1ERCSK*lWTBK*3lNWCK)*2lNWCK
+(2WWFK*-2ERCSK*2WTBK*42NWCK+4~FK*-4ERCSK*4WTBK*42RWCK)*2lRWCK
*31NWCK)*12NWCK*13NWCK*lWGZ TO 1WRCSR;
ASSIGN ((3EEFK*-3WRCSK*3ETBK*l3RWCK+1EEFK*-lWRCSK*lETBK*l3NWCK)*2lRWCK
*31NWCK+(2EEFK*-ZWRCSK*2ETBK*Z4NWCK+4EEFK*-4WRCSK*4ETBK*24RWCK)
*21NWCK)*12NWCK*42NWCK*2EGZ TO ZERCSR;
ASSIGN ((3WWFK*-3ERCSK*3WTBK*3lRWCK+l~FK*~lERCSK*lWTBK*3lNWCK)*l2RWCK
*13NWCK+(2WWFK*-2ERCSK*ZWTBK*4ZNWCK+4WWFK*-4ERCSK*4WTBK*42RWCK)
*12NWCK)*21NWCK*24NWCK*2WGZ TO 2WRCSR;
ASSIGN (((2EEFK*-2WRCSK*2ETBK*Z4NWCK+4EEFK*-4WRCSK*4ETBK*24RWCK)*l2RWCK
*13NWCK+1EEFK*-1WRCSK*lETBK*l2NWCK)*21"CK+3EEFK*-3WRCSK
*3ETBK*13NWCK*31NWCK)*3EGZ TO 3ERCSR;
ASSIGN (((2WWFK*-2ERCSK*2WTBK*42NWCK+4WWFK*~4ERCSK*4WTBK*4ZRWCK)*2lRWCK
*31NWCK+1WWFK*-1ERCSK*lWTBK*2lNWCK)*l2NWCK*l3RWCK+3EEFK*-3WRCSK
*3WTBK*31NWCK*13NWCK)*3WGZ TO 3WRCSR;
ASSIGN (((3EEFK*-3WRCSK*3ETBK*l3RWCK+lEEFK*-lWRCSK*lETBK*l3NWCK)*ZlRWCK
*31NWCK+2EEFK*-2WRCSK*2ETBK*24NWCK*ZlNWCK)*l2~CK*42RWCK+4EEFK*-4WRCSK
*4ETBK*24NWCK*42NWCK)*4EGZ TO 4ERCSR;
ASSIGN (((3WWFK*-3ERCSK*3WTBK*3lRWCK+l~FK*~lERCSK*lWTBK*3lNWCK)*l2RWCK
*13NWCK+ZWWFK*-2ERCSK*2WTBK*42NWCK*l2NWCK)*ZlNWCK*24RWCK+4WWFK*-4ERCSK
*4WTBK*42NWCK*24NWCK)*4WGZ TO 4WRCSR;
Figure 3- Equations Using Conventional Methods
are prohibited in this particular interlocking. is simple t o troubleshoot, and any temporary
The contacts for the t w o crossovers are or permanent modifications and
flipped left t o right in the network with reconfiguration changes t o the interlocking
respect t o the actual switch positions in the can easily be implemented. Perhaps the most
field. This saves the designer contacts in important point is that an inadvertent error
implementing the network t o exclude this in the network will be seen by each route
over and back route. Another example is the that traverses the point on the network
relative positions of the 1 3 and 3 1 where the error is located. For example,
crossovers for the same reason. It should be suppose t h a t the 1ETBR Track Block contact
noted here that the saving of contacts is of is in error. Assume a 1WTBR contact was
little t o no value when implementing circuits wired in place of the 1ETBR. The result
using Boolean values and expressions. would be that each route exiting the
interlocking on track number 1 East would
Notice the advantages of this type of be affected by the wrong contact. During
network. Because it correlates well with the testing, this error will become evident for all
physical layout of the interlocking, it can be routes exiting the interlocking o n track 1
designed directly from the track layout East.
drawing merely by inspection. The network
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% ROUTE CHECK EQUATIONS \
% EASTBOUND ROUTE CHECK EXIT EQUATIONS \
ASSIGN 3EEFK * -3WRCSK 3ETBK TO [Link];
ASSIGN 4EEFK * -4WRCSK 4ETBK TO [Link];
% WESTBOUND ROUTE CHECK EXIT EQUATIONS \
ASSIGN 3WWFK * -3ERCSK 3WTBK TO [Link];
ASSIGN 4WWFK * -4ERCSK * 4WTBK TO [Link];
% EASTBOUND ROUTE CHECK NODE EQUATIONS \
ASSIGN 13NWCK * lEEFK * -lWRCSK * lETBK
+13RWCK * [Link] TO [Link];
ASSIGN 24NWCK * 2EEFK * -2WRCSK * ZETBK
+24RWCK [Link] TO [Link];
ASSIGN 12NWCK * [Link]
+12RWCK * 13NWCK [Link] TO [Link];
ASSIGN 2lNWCK * 12NWCK * [Link]
+21RWCK * 31NWCK * [Link] 12NWCK TO [Link];
ASSIGN 31NWCK * 13NWCK * [Link]
+31RWCK * 2lNWCK [Link] * 13NWCK TO [Link];
ASSIGN 42NWCK * 24NWCK * [Link]
+42RWCK * [Link] (24NWCK + 21RWCK)TO [Link];
-
Figure 4a Equations Using Node Method
CONVENTIONAL PROGRAMMING sketch out a relay equivalent network from
METHODS inspection of the track plan. The expressions
are then written using this sketch. Any given
Figure 3 is a Boolean equation listing of portion of the network is repeated in each
expressions representing 'the route check expression for all the different route paths
network written using conventional through the network. A n error can therefore
programming methods. The designer often be made in one expression that would affect
begins by drawing a relay-based network. A only one route while all other routes remain
Boolean expression is written representing unaffected. The resulting expression is
each relay in the network. Every valid route extremely difficult t o analyze, since it
from entrance point t o exit point must be contains many embedded parentheses, and
traced through the network, and represented is nearly impossible t o modify without having
in the equations. The result is a total of eight t o redraw the sketch of the network. Even if
large and cumbersome expressions, leaving the original drawing has been retained and is
behind a multitude of problems. available, this still introduces a problem of
version control, and the designer must
The disadvantages t o this method are check, verify and revise the drawing against
numerous. First, the designer needs t o the expressions. The author has seen several
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% WESTBOUND ROUTE CHECK NODE EQUATIONS \
ASSIGN 31NWCK * lWWFK * -lERCSK * lWTBK
+31RWCK * [Link] TO [Link];
ASSIGN 42NWCK * 2WWFK * -2ERCSK * 2WTBK
+42RWCK * [Link] TO [Link];
ASSIGN 21NWCK [Link]
+21RWCK * 31NWCK * [Link] TO [Link];
ASSIGN l2NWCK * 2lNWCK * [Link]
+ 12RWCK * 13NWCK * [Link] * 21NWCKTO [Link];
ASSIGN 13NWCK * 31NWCK * [Link]
t13RWCK * l2NWCK * [Link] 31NWCK TO [Link];
ASSIGN 24NWCK * 42NWCK * [Link]
+24RWCK * [Link] (42NWCK + 12RWCK) TO [Link];
% ROUTE CHECK ENTRANCE EQUATIONS \
ASSIGN 31NWCK * 2lNWCK * [Link] * lATWSK * lEGZ TO 1ERCSR;
ASSIGN 13NWCK * 12NWCK * [Link] * lBTWSK lWGZ TO 1WRCSR;
ASSIGN 42NWCK * [Link] * 2ATWSK * 2EGZ TO 2ERCSR;
ASSIGN 24NWCK * [Link] * 2BTESK * 2WGZ TO ZWRCSR;
ASSIGN [Link] * 3ATWSK * 3EGZ TO 3ERCSR;
ASSIGN [Link] * 3BTESK * 3WGZ TO 3WRCSR;
ASSIGN [Link] * 4ATWSK * 4EGZ TO 4ERCSR;
ASSIGN [Link] 4BTESK * 4WGZ TO 4WRCSR;
Figure 4b - Equations Using Node Method (cont.)
compilers capable of drawing relay associated expression would reveal the
equivalent circuits directly from the Boolean problem.
equations. For all but the simplest relay
circuits, these compilers leave much t o be
desired when they attempt t o draw out an NETWORK NODE EQUATION METHOD
expression representing a network.
The network node equation method
Even after an accurate sketch is developed by the author allows the designer
constructed, implementing changes t o the t o write network equations that maintain all
network is extremely perilous. Every route the benefits that are inherent in relay-based
affected by that change must be located in networks. The method is based on the fact
the program and modified. Testing a n e w or that routes through an interlocking can be
modified set of expressions is extremely viewed as a series of segments, where each
onerous since an error can be present that segment of the route represents a path that
affects only a single route, with no effect on progresses from one facing point switch up
any other routes. As in the case of the t o the next facing point switch. The facing
erroneous track block mentioned previously, point switch can be thought of as being a
only the one route governed by its node, where a decision is made, depending
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on whether that switch is normal or reverse. Likewise, exit logic for tracks one and t w o
Based on the position of the switch, each West is contained in the equations for the
node is linked t o the next appropriate node 31 B and 42B respectively. On the outside
and so on until the exit point of the tracks, however, an exit can be arrived at
interlocking is reached. from either traveling over a switch reverse,
or from a straight track route. This drives the
To implement this method, three sets of need t o maintain discrete exit equations for
equations are written for each direction of these tracks.
traffic. The first set are entrance equations,
which represent the route segments from the Node Equations
beginning point of the route up t o the first
node or facing point switch. The second set The next set of equations are the route
are the node equations, which represent that check node equations for each direction of
portion of the route from the facing point traffic. There is a node equation for each
switch up t o the next facing point switch or crossover for each direction of traffic. To
exit point of the interlocking. Depending on distinguish for which end of a crossover the
which position the switch is lined, the node node equations are written, the t w o
equation determines the appropriate linkage switches of a crossover are uniquely
t o the next equation. The third set of identified as the " A " end and the "B" end.
equations are the exit equations, The " A " switch is always on the West end,
representing the exit points of the with the "B" switch on the East end. Notice
interlocking. These exit equations would that all the Eastbound node equations
contain elements such as direction of traffic, exclusively use the " A " ends of the
opposing route checks and track blocks. crossovers, while the Westbound node
equations use the "B'l end.
Figures 4a and 4b show a complete set
of network equations using this method for Each of the node equations is written as
the route check network of the interlocking the sum of t w o product terms, the terms
in figure 1. The exit, node and entrance being separated by the logical OR ( + )
equations are written and described in that symbol. The first term governs that portion
order for reasons t o be discussed under the of the route segment over the switch in the
heading "ORDERING OF THE EQUATIONS". normal position. It will link t o the next node
or exit point as appropriate for the normal
Exit equations path of that switch. The second term
governs that portion of the route segment
Referring t o Figures 4a and 4b, the exit ov0r the switch in the reverse position.
equations are written first. The only exit Similarly, it will link t o the next node or exit
equations needed for the interlocking point as appropriate for the reverse path of
configuration shown in Figure 1 are those for that switch. The positions of any trailing
tracks three and four, west and east of the point switches encountered in proceeding t o
plant. The exit logic for tracks one and t w o the next node or exit point are also included
East is contained in the node equations for in these terms.
the 1 3 A and 2 4 A switch respectively, since
the only possible path t o arrive at these exit Route restrictions are another important
points is over the 13 or 24 switch normal. element included in these node equation
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terms. As an example, the restricted "over equation is written for each entrance point of
and back" routes mentioned previously for the interlocking. These equations link t o the
the 1 2 and 2 1 crossovers are implemented in first node equation in the route. Opposing
the equation for the [Link] in Figure 4a. route sticks and the signal call (GZ) are
The last variable in the second product term included in each of these expressions. Any
(12NWCK) enforces that the 1 2 crossover is trailing point switches encountered between
normal if w e are routed over the 2 1 the entrance point and the first node are also
crossover reverse. The same can be found included in these expressions.
for the Westbound node equations in Figure
4b for the [Link]. In this equation, the 21
is checked normal (21NWCK) for routes over ORDERING OF THE EQUATIONS
the 1 2 crossover reverse. Similar over and
back restrictions are found for the 13 and 31 When implementing this method of
crossovers and also for the 42 and 24 writing the network equations, the designer
crossovers. The 42 and 24 crossovers are must pay careful attention t o the order in
somewhat unique in that the restriction is which the equations are written and
conditional. The conditional restriction is as subsequently processed by the processor.
follows: To route over the 42 crossover Since the equations are linked t o each other,
reverse, the 24 must be normal unless the it is important t o insure that equations
21 crossover is reverse. This is implemented whose results are needed t o evaluate other
in the [Link] equation in Figure 4a using equations be processed prior t o these other
the following: equations. This will insure that the processor
(24NWCK + 21RWCK) can evaluate all the network equations in one
A similar conditional restriction is found in iteration, and subsequently reduce
the equation of the [Link] in Figure 4b processing time.
involving the 1 2 crossover due t o symmetry
of the interlocking. Generally, the order in which the
equations should be written is from exit
There is another class of restrictions point t o entrance point, paying careful
called forced switches. These are switches attention t o the order of the node equations.
that are not in the route, but must be in a Equations governing routes of opposite
certain position for the route t o be allowed. direction can be intermingled t o allow the
One example is the 2 1 and 31 crossovers. entrance, node and exit equations t o be
Any route over the 2 1 crossover reverse grouped together. The equations shown in
must check that the 3 1 crossover is Figure 4 have been arranged as described
positioned normal. The same restriction above.
exists between the 1 2 and the 13
crossovers. These restrictions are also
included in the node equations of Figures 4a CONCLUSION
and 4b.
This paper has described a method of
Entrance Equations writing network equations used extensively
in Railway Signal Systems for application in
The last set of network equations in Boolean logic microprocessor systems.
Figure 4 are the entrance equations. One Traditional relay-based networks were
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discussed, along with their advantages. advantages of the relay networks used for
Current methods of programming networks many years in the Railway Signalling
were discussed and compared to the new industry.
method. It was shown that the new method
is far superior t o preserving the features and
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