Experiment 1
AIM: To design basic logic gates using gate level, data flow and behavioral modelling in
Verilog HDL.
SOFTWARE USED: Vivado
THEORY:
A logic gate is an idealized or physical device that performs a Boolean function, a logical
operation performed on one or more binary inputs that produces a single binary output. We
have implemented them in Verilog HDL through gate level, data flow and behavioral
modelling.
Gate level Modeling: The module is implemented in terms of logic gates and
interconnections between these gates. Design at this level is similar to describing a design in
terms of gate-level logic diagram.
Dataflow Modeling: At this level, the module is designed by specifying the data flow. The
designer is aware of how data flows between hardware registers and how the data is
processed in the design.
Behavioral Modeling: This is the highest level of abstraction provided by Verilog HDL. A
module can be implemented in terms of the desired design algorithm without concern for the
hardware implementation details. Designing at this level is very similar to C programming.
PROGRAM AND SIMULATIONS:
Gate level modeling
Verilog Code
module gate_level(input c_aarushi, input d,output [5:0] y);
and(y[0],c_aarushi,d);
or(y[1],c_aarushi,d);
nand(y[2],c_aarushi,d);
nor(y[3],c_aarushi,d);
xnor(y[4],c_aarushi,d);
xor(y[5],c_aarushi,d);
endmodule
AARUSHI GUPTA 1
Schematic
Waveforms
AARUSHI GUPTA 2
Data flow modeling
Verilog Code
module data_flow(input a, input b_aarushi, output [5:0] y);
assign y[0]=a&b_aarushi; //and
assign y[1]=a|b_aarushi; //or
assign y[2]=a^b_aarushi; //xor
assign y[3]=a~^b_aarushi; //xnor
assign y[4]=~(a&b_aarushi); //nand
assign y[5]=~(a|b_aarushi);//nor
endmodule
AARUSHI GUPTA 3
Behavioral modeling
1. AND Gate
Verilog Code
module behav_and(input a, input b,output reg y_aarushi);
always@(a or b)
begin
if(a==1'b1 & b==1'b1)
begin y_aarushi=1'b1;
end
else
y_aarushi=1'b0;
end
endmodule
AARUSHI GUPTA 4
2. OR Gate
module behav_or(input a, input b,output reg y_aarushi);
always@(a or b)
begin
if(a==1'b0 & b==1'b0)
y_aarushi=1'b0;
else
y_aarushi=1'b1;
end
endmodule
AARUSHI GUPTA 5
3. NAND Gate
module behav_nand(input a, input b, output reg y_aarushi);
always@(a or b)
begin
if(a==1'b1 & b==1'b1)
y_aarushi=1'b0;
else
y_aarushi=1'b1;
end
endmodule
AARUSHI GUPTA 6
4. NOR Gate
module behav_nor(input a, input b, output reg y_aarushi);
always@(a or b)
begin
if(a==1'b0 & b==1'b0)
y_aarushi=1'b1;
else
y_aarushi=1'b0;
end
endmodule
AARUSHI GUPTA 7
5. XOR Gate
module arush_xor(input a, b, output reg y_aarushi);
always@(a,b,y_aarushi)
begin
if((a==1’b1 & b==1’b0)|(a==1’b0 & b==1’b1))
y_aarushi=1’b1;
else
y_aarushi=1’b0;
end
endmodule
AARUSHI GUPTA 8
6. XNOR Gate
module arush_xnor(input a, b, output reg y_aarushi);
always@(a,b,y_aarushi)
begin
if((a==1’b1 & b==1’b0)|(a==1’b0 & b==1’b1))
y_aarushi=1’b0;
else
y_aarushi=1’b1;
end
endmodule
AARUSHI GUPTA 9