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ARM Microcontroller Exam Question Paper

This document is a model question paper for the B.E. Degree Examination in Microcontrollers at The National Institute of Engineering, Mysuru for the year 2024. It includes various questions covering topics such as ARM core data flow, RISC vs CISC, arithmetic instructions, software interrupts, and cache memory architecture. The paper consists of multiple sections with questions aimed at different cognitive levels and marks allocation.

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8 views5 pages

ARM Microcontroller Exam Question Paper

This document is a model question paper for the B.E. Degree Examination in Microcontrollers at The National Institute of Engineering, Mysuru for the year 2024. It includes various questions covering topics such as ARM core data flow, RISC vs CISC, arithmetic instructions, software interrupts, and cache memory architecture. The paper consists of multiple sections with questions aimed at different cognitive levels and marks allocation.

Uploaded by

padmavatik79
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

US

THE NATIONAL INSTITUTE OF ENGINEERING, MYSURU – 8


(An Autonomous Institute Affiliated to VTU, Belagavi)

MODEL QUESTION PAPER


B.E. Degree Examination - 2024

BCS402 Microcontrollers

Time: 3Hrs Max. Marks: 100


Note: Answer all the questions.

Q. No. Cognt. COs Questions Marks


Level

1.a) L2 CO1 Explain ARM core data flow model with neat diagram 10M

b) L2 CO1 Discuss the general purpose register of ARM controller 5M

Differentiate between RISC and CISC machines 5M

2.a) L3 CO2 Analyse the following scenario based on the given precondition and 8M
instruction. Write the post condition of destination registers
Precondition:
R0= 0x2456734AB
R1= 0x676BCFBD
R2= 0xF43DE4B4
R3= 0xB8054AF4
Instruction:
i) AND R4, R2, R1
ii) BIC R4, R3, R0
iii)MOV R5,R1, ASR #2
iv)MOV R6,R0,ROR #1

b) L3 CO2 Demonstrate the working of the following arithmetic instructions 12M


for the given source registers R0=2CA456FE and R1=987AF234

i) MOV R3, R0, ROR #2


ii) MOV R1, R0, ASR #2
iii) MOV R4, R0, LSR #2
iv) MOV R5, R2, LSL #2

OR

2.c) L3 C02 Demonstrate the execution of the following Software interrupt 10M
instruction considering the precondition of the cpsr status and
instruction
Precondition:
cpsr = nzcVqift_USER
pc = 0x00008000
lr = 0x003fffff; lr = r14
r0 = 0x12 0x00008000
SWI 0x123456

2.d) L3 CO2 Demonstrate the execution of Logical operations for the following 10M
instructions for the two source registers R0=0x00000304 and
R1=00000ABC
i)EOR ii) RSB iii) SBC iv) ADC v) SUB
3.a) L4 CO3 Develop an ALP to find largest numbers in an array of 32bit 10M
numbers

b) L4 CO3 Discuss and Demonstrate the optimization possible when the 10M
variable i is
declared as int instead of char in the following C code. (Illustrate
both
the scenario with the help of Assembly Level code).
int checksum_v1(int *data)
{
char i;
int sum=0;
for (i=0; i<64; i++)
{
sum +=data[i];
}
return sum;
}

4.a) L3 CO4 Illustrate with suitable example how to enable and disable FIQ 10M
interrupt

b) L2 CO4 Explain the interrupt latency and discuss interrupt handler methods 10M
OR

4.c) L2 CO4 Explain the Link Register Offsets by considering the examples of 10M
handler

d) L2 CO4 With suitable diagram explain IRQ and FIQ Exceptions 10M

5.a) L1 CO1 Discuss the basic architecture of cache memory with suitable 10M
diagram

b) L3 CO5 Explain with neat diagram hierarchy with a neat Memory hierarchy 6M

c) L4 CO5 Analyse the following scenarios and identify the appropriate Write 4M
Policy for the same with justification

i) Real-Time Systems
ii) High-Performance Computing (HPC)
---***---

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