MODULE 5

Module V (8 Hours)

The Memory System – basic concepts, semiconductor RAM

memories - organization – static and dynamic RAM, Structure of
larger memories, semiconductor ROM memories, Speed, Size
and cost, Cache memory – mapping functions – replacement
S
algorithms , Virtual memory – paging and segmentation.
Q

• Hamacher, Vranesic & Zaky, “Computer Organization” (5th QEd), McGraw

R
Hill.
 Introduction

• Ideally, the memory would be fast, large, and

inexpensive.
• Unfortunately, it is impossible to meet all three of these
requirements simultaneously.
• Increased speed and size are achieved at increased
cost.
 BASIC CONCEPTS

• The maximum size of the memory that can be used in

any computer is determined by the addressing scheme.
• For example, a computer that generates 16-bit
addresses is capable of addressing up to 216 = 64K
(kilo) memory locations.
• Machines whose instructions generate 32-bit addresses
can utilize a memory that contains up to 232 = 4G
(giga) ≈ 4 × 109 locations, whereas machines with 64-
bit addresses can access up to 264 = 16E (exa) ≈ 16 ×
1018 locations.
• The number of locations represents the size of the
address space of the computer.

Tera – 1012 Peta - 1015

 BASIC CONCEPTS

• If the smallest addressable unit of information is a memory

word, the machine is called word-addressable.
• If individual memory bytes are assigned distinct addresses,
the computer is called byte-addressable.
• Most of the commercial machines are byte addressable. For
example in a byte-addressable 32-bit computer, each
memory word contains 4 bytes.
 BASIC CONCEPTS

• Main Memory (MM) unit can be viewed as a “black box”.

• Data transfer between CPU and MM takes place through the
use of two CPU registers, usually called MAR (Memory
Address Register) and MDR (Memory Data Register).
• If MAR is ‘k’ bits long and MDR is ‘n’ bits long, then the MM
unit may contain upto 2k addressable locations and each
location will be ‘n’ bits wide, while the word length is equal
to ‘n’ bits.
 BASIC CONCEPTS

• During a “memory cycle”, n bits of data may be transferred

between the MM and CPU.
• This transfer takes place over the processor bus, which has k
address lines (address bus), n data lines (data bus) and
control lines like Read, Write, Memory Function completed
(MFC), Bytes specifiers etc (control bus).
BASIC CONCEPTS

Processor Memory
k-bit
address bus
MAR

n -bit
data bus k
Up to 2 addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)

Figure 1 Connection of memory to the processor

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
 BASIC CONCEPTS
• For a read operation, the CPU loads the address into MAR,
set READ to 1 (R/W = 1) and sets other control signals if
required. The data from the MM is loaded into MDR and MFC
is set to 1.
• Upon receipt of the MFC signal, the processor loads the data
on the datalines into the MDR register.

• For a write operation, MAR, MDR are suitably loaded by the

CPU, WRITE is set to 1 (R/W = 0) and other control signals
are set suitably. The MM control circuitry loads the data into
appropriate locations and sets MFC to 1.
 BASIC CONCEPTS
• The connection between the processor and its memory
consists of address, data, and control lines.
• The processor uses the address lines to specify the memory
location involved in a data transfer operation, and uses the
data lines to transfer the data.
• At the same time, the control lines carry the command
indicating a Read or a Write operation and whether a byte or
a word is to be transferred.
• The control lines also provide the necessary timing
information and are used by the memory to indicate when it
has completed the requested operation.
 BASIC CONCEPTS
Measures for the speed of a memory
• Memory Access Time: - It is a useful measure of the speed of
the memory unit. It is the time that elapses between the
initiation of an operation and the completion of that operation
(for example, the time between READ and MFC).

• Memory Cycle Time :- It is an important measure of the

memory system. It is the minimum time delay required
between the initiations of two successive memory operations
(for example, the time between two successive READ
operations).

• The cycle time is usually slightly longer than the access time,
depending on the implementation details of the memory
unit.
 BASIC CONCEPTS
• Memory
• Primary Memory (directly accessed by processor)
• RAM(Random Access Memory) – Volatile(data stored is
lost when power is turned off) – OS, applicn program,
data currently using
• ROM(Read Only Memory) – Non-volatile(data stored is
retained even if when power is turned off) –
BIOS(booting), firmware for other hardware devices
[Firmware is a form of microcode or program embedded into hardware devices
to help them operate effectively.]

• Secondary Memory
 BASIC CONCEPTS

• A memory unit is called a random-access memory (RAM) if

the access time to any location is the same, independent of
the location’s address.
• This distinguishes such memory units from serial, or partly
serial access storage devices such as magnetic and optical
disks.
• Access time of the latter devices depends on the address or
position of the data.
• The technology for implementing computer memories uses
semiconductor integrated circuits.
 BASIC CONCEPTS
• There are techniques used to increase the effective speed
and size of the memory.
• Cache Memory (to increase the effective speed)
• Virtual memory (to increase the effective size)

• The processor of a computer can usually process instructions

and data faster than they can be fetched from the main
memory. Hence, the memory access time is the bottleneck in
the system.
• One way to reduce the memory access time is to use a
cache memory. This is a small, fast memory inserted
between the larger, slower main memory and the processor.
It holds the currently active portions of a program and their
data.
 BASIC CONCEPTS
• There are techniques used to increase the effective speed
and size of the memory.
• Cache Memory (to increase the effective speed)
• Virtual memory (to increase the effective size)
• Virtual memory is another important concept related to
memory organization.
• With this technique, only the active portions of a program
are stored in the main memory, and the remainder is stored
on the much larger secondary storage device.
• Sections of the program are transferred back and forth
between the main memory and the secondary storage
device in a manner that is transparent to the application
program.
• As a result, the application program sees a memory that is
much larger than the computer’s physical main memory.
 SEMICONDUCTOR RAM MEMORIES

• Semiconductor random-access memories (RAMs) are

available in a wide range of speeds.
• Their cycle times range from 100 ns to less than 10 ns.
• Previously very costly, but now it is dropped down. (rapid
advances in VLSI)
• In this section, we discuss the main characteristics of these
memories.
• We start by introducing the way that memory cells are
organized inside a chip.
INTERNAL ORGANIZATION OF MEMORY CHIPS

• Memory cells are usually organized in the form of an array,

in which each cell is capable of storing one bit of
information. [Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]

CS (Chip Select) input

selects a given chip in
a multichip memory
system.
INTERNAL ORGANIZATION OF MEMORY CHIPS

• A possible organization is
illustrated in Figure 2.
• Each row of cells constitutes
a memory word, and all cells
of a row are connected to a
common line referred to as
the word line, which is driven
by the address decoder on
the chip.
• The cells in each column are
connected to a Sense/Write
circuit by two bit lines, and
the Sense/Write circuits are
connected to the data
input/output lines of the chip.
INTERNAL ORGANIZATION OF MEMORY CHIPS

• During a Read operation,

these circuits sense, or read,
the information stored in the
cells selected by a word line
and place this information on
the output data lines.
• During a Write operation, the
Sense/Write circuits receive
input data and store them in
the cells of the selected
word.
INTERNAL ORGANIZATION OF MEMORY CHIPS
• Figure 2 is an example of a very
small memory circuit consisting of
16 words of 8 bits each (16 × 8
organization).
• The data input and the data output
of each Sense/Write circuit are
connected to a single bidirectional
data line that can be connected to
the data lines of a computer.
• Two control lines, R/W and CS, are
provided. The R/W (Read/Write)
input specifies the required
operation, and the CS (Chip Select)
input selects a given chip in a
multichip memory system.
INTERNAL ORGANIZATION OF MEMORY CHIPS

• The memory circuit in Figure 2 stores 128 bits(16 x 8) and

requires 14 external connections for address(4), data(8),
and control lines(2).
• It also needs two lines for power supply and ground
connections.
• Consider now a slightly larger memory circuit, one that has
1K (1024) memory cells. This circuit can be organized as a
128 × 8 memory, requiring a total of 19 external
connections.(7+8+2+2(power and gnd))
• Alternatively, the same number of cells can be organized
into a 1K×1 format. In this case, a 10-bit address(1K ≈ 210)
is needed, but there is only one data line, resulting in 15
external connections. (10+1+2+2)
INTERNAL ORGANIZATION OF MEMORY CHIPS

1024 bits(32x32)

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
INTERNAL ORGANIZATION OF MEMORY CHIPS

• The 10-bit address is divided into two groups of 5 bits each

to form the row and column addresses for the cell array.
• A row address selects a row of 32 cells, all of which are
accessed in parallel.
• One of these, selected by the column address, is connected
to the external data lines by the input and output
multiplexers.
• This structure can store 1024 bits(32x32), can be
implemented in a 16-pin chip.
STATIC MEMORIES

• Memories that consist of circuits capable of retaining their

state as long as power is applied are known as static
memories.
• Figure illustrates how a static RAM (SRAM) cell may be
implemented.

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
STATIC MEMORIES

• Two inverters are cross-connected

to form a latch.
• The latch is connected to two bit
lines by transistors T1 and T2.
• These transistors act as switches
that can be opened or closed
under control of the word line.
When the word line is at ground
level, the transistors are turned
off and the latch retains its state.
• For example, if the logic value at
point X is 1 and at point Y is 0,
this state is maintained as long as
the signal on the word line is at
ground level. [Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
STATIC MEMORIES

Read Operation
• In order to read the state of the
SRAM cell, the word line is
activated to close switches T1 and
T2.
• If the cell is in state 1, the signal
on bit line b is high and the signal
on bit line b’ is low.
• The opposite is true if the cell is in
state 0. Thus, b and b’ are always
complements of each other.
• The Sense/Write circuit at the end
of the two bit lines monitors their
state and sets the corresponding
output accordingly. [Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
STATIC MEMORIES

Write Operation
• During a Write operation,
the Sense/Write circuit
drives bit lines b and b’,
instead of sensing their
state.
• It places the appropriate
value on bit line b and its
complement on b’ and
activates the word line.
• This forces the cell into the
corresponding state.

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
CMOS Cell
• A CMOS realization of the
cell is in Figure5.
• Transistor pairs (T3, T5) and
(T4, T6) form the inverters
in the latch.
• The state of the cell is read
or written as just explained.
• For example, in state 1, the
voltage at point X is
maintained high by having
transistors T3 and T6 on,
while T4 and T5 are off.
• If T1 and T2 are turned on,
bit lines b and b’ will have
high and low signals, [Hamacher, Vranesic & Zaky, “Computer
respectively. Organization” (5th Ed), McGraw Hill]
CMOS Cell

• Continuous power is needed for the cell to retain its state.

• If power is interrupted, the cell’s contents are lost.
• When power is restored, the latch settles into a stable state,
but not necessarily the same state the cell was in before the
interruption.
• Hence, SRAMs are said to be volatile memories because their
contents are lost when power is interrupted.

• A major advantage of CMOS SRAMs is their very low power

consumption, because current flows in the cell only when the
cell is being accessed.
• Otherwise, T1, T2, and one transistor in each inverter are
turned off, ensuring that there is no continuous electrical
path between Vsupply and ground.
Static RAM (SRAM)

• Static RAMs can be accessed very quickly. Access times on

the order of a few nanoseconds are found in commercially
available chips.
• SRAMs are used in applications where speed is of critical
concern.
RAM

• Static RAMs (SRAMs):

• Consist of circuits that are capable of retaining their state
as long as the power is applied.
• Volatile memories, because their contents are lost when
power is interrupted.
• Access times of static RAMs are in the range of few
nanoseconds.
• However, the cost is usually high.
• Dynamic RAMs (DRAMs):
• Do not retain their state indefinitely.
• Contents must be periodically refreshed.
• Contents may be refreshed while accessing them for
reading.
 SRAM VS DRAM

SRAM DRAM
• Very fast • Slower than SRAM
• Very Expensive • Cheaper than SRAM
• Used in Cache memory • Used in most computer as
and CPU register main memory
• Need to be refreshed
periodically
ASYNCHRONOUS DYNAMIC RAMS

• Static RAMs are fast, but their cells require several

transistors.
• Less expensive and higher density RAMs can be implemented
with simpler cells. Such cells do not retain their state
indefinitely; hence, they are called dynamic RAMs (DRAMs).

• Information is stored in a dynamic memory cell in the form of

a charge on a capacitor, but this charge can be maintained
for only tens of milliseconds.
• Since the cell is required to store information for a much
longer time, its contents must be periodically refreshed by
restoring the capacitor charge to its full value.
ASYNCHRONOUS DYNAMIC RAMS
• An example of a dynamic memory cell that consists of a
capacitor, C, and a transistor, T.
• To store information in this cell, transistor T is turned on and
an appropriate voltage is applied to the bit line.
• This causes a known amount of charge to be stored in the
capacitor.

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
ASYNCHRONOUS DYNAMIC RAMS

• After the transistor is turned off, the charge remains stored in

the capacitor, but not for long.
• The capacitor begins to discharge. This is because the
transistor continues to conduct a tiny amount of current,
measured in picoamperes, after it is turned off.
• Hence, the information stored in the cell can be retrieved
correctly only if it is read before the charge in the capacitor
drops below some threshold value.

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
ASYNCHRONOUS DYNAMIC RAMS
• During a Read operation, the transistor in a selected cell is
turned on.
• A sense amplifier connected to the bit line detects whether
the charge stored in the capacitor is above or below the
threshold value.
• If the charge is above the threshold, the sense amplifier
drives the bit line to the full voltage representing the logic
value 1. As a result, the capacitor is recharged to the full
charge corresponding to the logic value 1.
ASYNCHRONOUS DYNAMIC RAMS
• If the sense amplifier detects that the charge in the capacitor
is below the threshold value, it pulls the bit line to ground
level to discharge the capacitor fully.
• Thus, reading the contents of a cell automatically refreshes
its contents.
• Since the word line is common to all cells in a row, all cells in
a selected row are read and refreshed at the same time.
ASYNCHRONOUS DYNAMIC RAMS

212 (A20-9) ≈ 4096

29 ≈ 512
(A20-9)

221 ≈ 2M

The timing of the

operation of the DRAM is
controlled by the RAS and (A8-0)
CAS signals .
221 ≈ 2M

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
ASYNCHRONOUS DYNAMIC RAMS

• During a Read or a Write operation, the row address is

applied first.
• It is loaded into the row address latch in response to a signal
pulse on an input control line called the Row Address Strobe
(RAS). This causes a Read operation to be initiated, in which
all cells in the selected row are read and refreshed.
• Shortly after the row address is loaded, the column address
is applied to the address pins and loaded into the column
address latch under control of a second control line called
the Column Address Strobe (CAS).
ASYNCHRONOUS DYNAMIC RAMS

• The timing of the operation of the DRAM is controlled by the

RAS and CAS signals.
• These signals are generated by a memory controller circuit
external to the chip when the processor issues a Read or a
Write command.
• During a Read operation, the output data are transferred to
the processor after a delay equivalent to the memory’s
access time. Such memories are referred to as asynchronous
DRAMs.
• The memory controller is also responsible for refreshing the
data stored in the memory chips.
Fast Page Mode

• All bytes in the selected row can be transferred in sequential

order by applying a consecutive sequence of column
addresses under the control of successive CAS signals.
• Thus, a block of data can be transferred at a much faster
rate than can be achieved for transfers involving random
addresses.
• The block transfer capability is referred to as the fast page
mode feature. (A large block of data is often called a page.)
SYNCHRONOUS DRAMS
• Developments in memory technology resulted in DRAMs
whose operation is synchronized with a clock signal. Such
memories are known as synchronous DRAMs (SDRAMs).

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
SYNCHRONOUS DRAMS
• The cell array is the same as in asynchronous DRAMs.
• The distinguishing feature of an SDRAM is the use of a clock
signal, the availability of which makes it possible to
incorporate control circuitry on the chip that provides many
useful features.
• For example, SDRAMs have built-in refresh circuitry, with a
refresh counter to provide the addresses of the rows to be
selected for refreshing.
• The address and data connections of an SDRAM may be
buffered by means of registers.
• Internally, the Sense/Write amplifiers function as latches, as
in asynchronous DRAMs.
SYNCHRONOUS DRAMS

• A Read operation causes the contents of all cells in the

selected row to be loaded into these latches.
• The data in the latches of the selected column are
transferred into the data register and thus becoming
available on the data output pins.
• The buffer registers are useful when transferring large blocks
of data at very high speed.
SYNCHRONOUS DRAMS
• SDRAMs have several different modes of operation, which
can be selected by writing control information into a mode
register.
• It is not necessary to provide externally-generated pulses on
the CAS line to select successive columns.
• The necessary control signals are generated internally using
a column counter and the clock signal.
• New data are placed on the data lines at the rising edge of
each clock pulse.
• Synchronous DRAMs can deliver data at a very high rate,
because all the control signals needed are generated inside
the chip.
SYNCHRONOUS DRAMS
• Indication of performance : Latency and bandwidth
Memory latency is the time it takes to transfer a word of data
to or from memory.
Memory bandwidth is the number of bits or bytes that can be
transferred in one second.

• Various techniques are used to transfer the bits quickly to the

pins of the chip.
• To make the best use of the available clock speed, data are
transferred externally on both the rising and falling edges of
the clock. The memories that use this technique are called
double-data-rate SDRAMs (DDR SDRAMs).
Structure of larger memories
• Static Memory Systems

• Dynamic Memory Systems

Structure of larger memories

22=4 units

[512 x 8] * 4 units = 2M x 32

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
 MODULE 5

Module V (8 Hours)

The Memory System – basic concepts, semiconductor RAM

memories - organization – static and dynamic RAM, Structure
of larger memories, semiconductor ROM memories, Speed,
Size and cost, Cache memory – mapping functions –
S
replacement algorithms , Virtual memory – pagingQ and
segmentation.

• Hamacher, Vranesic & Zaky, “Computer Organization” (5th QEd), McGraw

R
Hill.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Read-Only Memory (ROM)

• Both static and dynamic RAM chips are volatile, which means that
they retain information only while power is turned on.
• There are many applications requiring memory devices that retain
the stored information when power is turned off.

• Many embedded applications do not use a hard disk and require

non-volatile memories to store their software.
• Non-volatile memory’s contents can be read in the same way as
for their volatile counterparts.
• A special writing process is needed to place the information into a
non-volatile memory.

• Since its normal operation involves only reading the stored data, a
memory of this type is called a read-only memory (ROM).
 Read-Only Memory (ROM)

• A logic value 0 is stored in the

cell if the transistor is
connected to ground at point P;
otherwise, a 1 is stored.
• The bit line is connected
through a resistor to the power
supply.
• To read the state of the cell, the
word line is activated to close
the transistor switch.
• As a result, the voltage on the
bit line drops to near zero if
there is a connection between
the transistor and ground.
[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
 Read-Only Memory (ROM)

• If there is no connection to
ground, the bit line remains at
the high voltage level,
indicating a 1.
• A sense circuit at the end of the
bit line generates the proper
output value.
• The state of the connection to
ground in each cell is
determined when the chip is
manufactured, using a mask
with a pattern that represents
the information to be stored.

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
 Read-Only Memory (ROM)

PROM
• Some ROM designs allow the data to be loaded by the user
and thus providing a programmable ROM (PROM).
• Programmability is achieved by inserting a fuse at point P, in
Figure.
• Before it is programmed, the memory contains all 0s. The
user can insert 1s at the required locations by burning out
the fuses at these locations using high-current pulses.
• Of course, this process is irreversible.
• PROMs provide flexibility and convenience not available with
ROMs.
Read-Only Memory (ROM)

EPROM
• Another type of ROM allows the stored data to be erased and
new data to be written into it.
• Such an erasable, reprogrammable ROM is usually called an
EPROM.
• It provides considerable flexibility during the development
phase of digital systems.
• Since EPROMs are capable of retaining stored information for
a long time, they can be used in place of ROMs or PROMs
while software is being developed.
• In this way, memory changes and updates can be easily
made.
• An EPROM cell has a structure similar to the ROM cell.
• However, the connection to ground at point P is made
through a special transistor.
Read-Only Memory (ROM)

EEPROM
• An EPROM must be physically removed from the circuit for
reprogramming. Also, the stored information cannot be
erased selectively. The entire contents of the chip are erased
when exposed to ultraviolet light.
• Another type of erasable PROM can be programmed, erased,
and reprogrammed electrically. Such a chip is called an
electrically erasable PROM, or EEPROM.
• It does not have to be removed for erasure.
• Moreover, it is possible to erase the cell contents selectively.
• One disadvantage of EEPROMs is that different voltages are
needed for erasing, writing, and reading the stored data,
which increases circuit complexity.
Read-Only Memory (ROM)

Flash Memory
• A flash cell is based on a single transistor controlled by
trapped charge, much like an EEPROM cell.
• Also like an EEPROM, it is possible to read the contents of a
single cell.
• The key difference is that, in a flash device, it is only possible
to write an entire block of cells.
• Prior to writing, the previous contents of the block are
erased.
• Flash devices have greater density, which leads to higher
capacity and a lower cost per bit.
• They require a single power supply voltage, and consume
less power in their operation.
Read-Only Memory (ROM)

Flash Cards
• One way of constructing a larger module is to mount flash
chips on a small card.
• Such flash cards have a standard interface that makes them
usable in a variety of products.
• A card is simply plugged into a conveniently accessible slot.
• Flash cards with a USB interface are widely used and are
commonly known as memory keys
Read-Only Memory (ROM)

Flash Drives
• Larger flash memory modules have been developed to
replace hard disk drives, and hence are called flash drives.
• However, the storage capacity of flash drives is significantly
lower than hard disks.
• Commonly, the capacity of flash drives is in the order of 64
to 128 Gbytes. In contrast, hard disks have capacities
exceeding a terabyte.
• Also, disk drives have a very low cost per bit.
SPEED, SIZE AND COST
• An ideal memory would be fast, large, and inexpensive.
• It is clear that a very fast memory can be implemented using
static RAM chips.
• However, these chips are not suitable for implementing large
memories, because their basic cells are larger and consume
more power than dynamic RAM cells.
• Although dynamic memory units with gigabyte capacities can
be implemented at a reasonable cost, the affordable size is
still small compared to the demands of large programs with
voluminous data.
• A solution is provided by using secondary storage, mainly
magnetic disks, to provide the required memory space.
• Disks are available at a reasonable cost, and they are used
extensively in computer systems. However, they are much
slower than semiconductor memory units.
SPEED, SIZE AND COST

Figure 10: Memory Hierarchy

[Hamacher, Vranesic & Zaky, “Computer Organization” (5th Ed), McGraw Hill]
SPEED, SIZE AND COST
[Hamacher, Vranesic & Zaky, “Computer
Organization” (5th Ed), McGraw Hill]

• Fastest access is to the data held

in processor registers. Registers are
at the top of the memory hierarchy.

• Relatively small amount of

memory that can be implemented
directly on the processor chip. This
is processor cache.

• Two levels of cache. Level 1 (L1)

cache is on the processor chip.
Level 2 (L2) cache is in between
main memory and processor.

Figure 10: Memory Hierarchy

SPEED, SIZE AND COST
[Hamacher, Vranesic & Zaky, “Computer
Organization” (5th Ed), McGraw Hill]

• Next level is main memory,

implemented using dynamic
memory components. Much
larger, but much slower than
cache memory.

• Next level is magnetic disks. It

provides huge amount of
inexpensive storage.

• Speed of memory access is

critical; the idea is to bring
instructions and data that will be
used in the near future as close
Figure 10: Memory Hierarchy to the processor as possible.
SPEED, SIZE AND COST

Figure 10a: Pyramid Structure Memory Hierarchy

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