Counters
Prepared by
Mr Sandeep kanaujia
Assistant professor
1
1. Introduction To Counters :
• A counter is a sequential digital
device, which is used for
counting ( up or down) .
Counters is a very wide
application of flip-flops, where
it is a group of flip-flops with a
clock signal applied .
• Types of counters :
o Asynchronous (Ripple)
counters.
o Synchronous (parallel)
2
counters.
2. Frequency Division :
• Frequency division is one of the main propose of
counters, the division process is used to reduce the
frequency of the clock input waveform.
3
Divide by 2 counter :
• This type of counters reduces the frequency of
the clock input exactly to the half for each flip-
flop, this type of counters is called binary ripple
counters. For nth FFs , the input frequency
𝑓𝑖𝑛
reduces by the factor 𝑛 .
2
• For example, the output frequency :
𝑓𝑖𝑛 𝑓𝑖𝑛
After 4 FFs = 4 =
2 16
𝑓𝑖𝑛
After 8 FFs =
256
𝑓𝑖𝑛
After 12 FFs =
4096 4
Example :
• If an input frequency of 200 KHz is applied
to a binary ripple counter that has 6 FFs ,
what is the out put frequency of the last FF
in KHz ?
• Solution :
200
f= = 3.125 KHz
26
5
6
Example :
• If an input frequency of 200 KHz is applied
to a binary ripple counter that has 6 FFs ,
what is the out put frequency of the last FF
in KHz ?
• Solution :
200
f= = 3.125 KHz
26
7
AsynchronousCounter/synchronous
• Up Counters(123456…..)
• down Counters (98765…)
• Bidirectional Counters
4. Types of counters :
4.1 : Asynchronous (Ripple) Counter :
• Definition : Type of counters in which each flip flop output
serves as the clock input signal for the next FF in the
sequence.
• In Asynchronous counters , the input of some or all FFs are
triggered not by the common clock pulse, but rather by the
transition that occurs in other FF output.
• The FFs don’t change states at exactly the same time as they
don’t have a common clock pulse.
• For a ripple counter consists of n FFs , the number of its
states equals 2n , and It can count from 0 to (2n -1).
Notes :
To operate the toggle mode , the FFs must be connected with J=K=1
Remember that the FFs are connected in series in Asynchronous systems. 10
3 bit Asynchronous up Counters
3 bit Asynchronous down Counters
Waveform of 3 bit Asynchronous down
Counters
3 bit (ripple)Asynchronous up/down
Counters
4.1.5 : Asynchronous Counters advantages and
disadvantages:
• Advantages :
1. Asynchronous Counters can easily be made from Toggle or D-
type flip-flops.
2. They are called “Asynchronous Counters” because the clock
input of the flip-flops are not all driven by the same clock
signal.
3. Each output in the chain depends on a change in state from
the previous flip-flops output.
4. Asynchronous counters are sometimes called ripple counters
because the data appears to “ripple” from the output of one
flip-flop to the input of the next.
5. They can be implemented using “divide-by-n” counter circuits.
6. Truncated counters can produce any modulus number count.
17
• Disadvantages :
1. An extra “re-synchronizing” output flip-flop may be
required.
2. To count a truncated sequence not equal to 2n,
extra feedback logic is required.
3. Counting a large number of bits, propagation delay
by successive stages may become undesirably large.
4. This delay gives them the nickname of “Propagation
Counters”.
5. Counting errors occur at high clocking frequencies.
6. Synchronous Counters are faster and more reliable
as they use the same clock signal for all flip-flops.
18
4.2 : Synchronous (Parallel) Counter :
• We see that an asynchronous suffers from what is
known as “Propagation Delay” in which the timing
signal is delayed a fraction through each flip-flop.
• All the individual output bits changing state at exactly
the same time in response to the common clock
signal with no ripple effect and therefore, no
propagation delay.
19
4.2.3 : Design a synchronous counter :
• Procedure to design a parallel counter :
1. Determine the number and type of FF you have to use.
2. Obtain the excitation table .
3. Obtain the state diagram ,ckt excitation table.
4. Obtain and simplify the function of each FF input using
K-map.
5. Draw the circuit.
20
Example :2bit synchronous up counter
• Step1
no of FF = no of bits 1. 2n = 4 n = 2 FFs
2FF of JK FF
• Step 2
Present state next state
Step 3
2. State transition diagram
State diagram
Step 4
Step 5
Example :2bit synchronous down
counter
• Only excitation table change(3-0)
• Excitation table for 2 bit synchronous down
counter
4.2.2 : Synchronous Bidirectional Counter :
• The figure below shows a parallel up/down counter .
• The control input up/down controls whether the normal FF
outputs or the inverted once, are fed to the J&K inputs of
the successive FFs.
26
• When up/down is held high ,
1. AND gates 1 &2 are enabled .
2. AND gates 3&4 are disabled (Note the inverter).
3. This allows the A &B outputs through gates 1and 2
into the J and K inputs of FFs B and C.
• When up/down is held low ,
1. AND gates 1 &2 are disabled .
2. AND gates 3&4 are enabled .
3. This allows the A &B outputs through gates 3and 4
into the J and K inputs of FFs B and C
27
Timing diagram of a 4-bit binary parallel bidirectional counter
Note :
For the first 5 clock pulses , up/down =1 and the counter counts up ; for the first 5
clock pulses , up/down =1 and the counter counts up 28