Module 2 Practice Problem Set: The following problems are under the topic of Amplifier
Frequency Response. Study and analyze the problems carefully and try to practice solving
related problems afterwards.
A. The Decibel Unit
1. Find the magnitude gain corresponding to a voltage gain of 50 dB.
For the voltage gain in dB, we have,
𝑉𝑜
𝐴𝑣 (𝑑𝐵) = 20 log ( )
𝑉𝑖
𝑉𝑜
50 = 20 log ( )
𝑉𝑖
𝑉𝑜
log ( ) = 2.5
𝑉𝑖
Using antilog, the magnitude of the gain will be,
𝑽𝒐
𝑨𝒗 = = 𝟑𝟏𝟔. 𝟐𝟐𝟕𝟕
𝑽𝒊
2. A device has an input power of 8000 W with input voltage rating of 1200 V. The output
power is rated as 400 W and the output impedance is 40 Ω. Find the (a) power gain in
dB; (b) voltage gain in dB and (c) Explain why (a) and (b) agree or disagree.
Solution:
(a) Solving for the power gain, we have,
𝑃𝑜
𝐴𝑝 (𝑑𝐵) = 10 log ( )
𝑃𝑖
400
𝐴𝑝 (𝑑𝐵) = 10 log ( )
8000
𝑨𝒑 (𝒅𝑩) = −𝟏𝟑. 𝟎𝟏𝟎𝟐 𝒅𝑩
(b) Solving for the voltage gain, we have,
𝑉𝑜
𝐴𝑣 (𝑑𝐵) = 20 log ( )
𝑉𝑖
But,
𝑉𝑜 = √𝑃𝑜 𝑅𝑜 = √(400)(40)
𝑉𝑜 = 126.4911 𝑉
Hence,
126.4911
𝐴𝑣 (𝑑𝐵) = 20 log ( )
1200
𝑨𝒗 (𝒅𝑩) = −𝟏𝟗. 𝟓𝟒𝟐𝟒 𝒅𝑩
(c) To determine if (a) and (b) agree or disagree, we have,
𝑉𝑖2 (1200)2
𝑅𝑖 = = = 𝟏𝟖𝟎 Ω
𝑃𝑖 8000
𝑹𝒊 ≠ 𝑹 𝒐
3. An amplifier is rated 50 W as its output power. It is used for a speaker load with 10-
ohm resistance rating. Calculate (a) the input power required for full power output if
the power gain is 20 dB and (b) the input voltage for rated output if the amplifier
voltage gain is 50 dB.
Solution:
(a) For the input power required,
𝑃𝑜
𝐴𝑝 (𝑑𝐵) = 10 log ( )
𝑃𝑖
20 50
= log ( ) = 2
10 𝑃𝑖
20
𝑃𝑖 =
𝑎𝑛𝑡𝑖𝑙𝑜𝑔(2)
𝑷𝒊 = 𝟓𝟎𝟎 𝒎𝑾
(b) For the input voltage,
𝑉𝑜
𝐴𝑣 (𝑑𝐵) = 20 log ( )
𝑉𝑖
But,
𝑉𝑜 = √𝑃𝑜 𝑅𝑜 = √(50)(10)
𝑉𝑜 = 22.3606 𝑉
So that,
50 22.3606
= log ( )
20 𝑉𝑖
22.3606
𝑉𝑖 =
𝑎𝑛𝑡𝑖𝑙𝑜𝑔(2.5)
𝑽𝒊 = 𝟕𝟎. 𝟕𝟏𝟎𝟔 𝒎𝑽
4. Convert the following power levels to dBm: (a) 31 W (b) 203 mW (c) 1 mW (d) 0.1 mW
Solution:
(a) For P1 = 31 W,
31
𝑃𝑑𝐵𝑚 = 10 log ( ) = 𝟒𝟒. 𝟗𝟏𝟑𝟔 𝒅𝑩𝒎
1 × 10−3
(b) For P1 = 203 mW,
203 × 10−3
𝑃𝑑𝐵𝑚 = 10 log ( ) = 𝟐𝟑. 𝟎𝟕𝟒𝟗 𝒅𝑩𝒎
1 × 10−3
(c) For P1 = 1 mW,
1 × 10^ − 3
𝑃𝑑𝐵𝑚 = 10 log ( ) = 𝟎 𝒅𝑩𝒎
1 × 10−3
(d) For P1 = 0.1 mW,
0.1 × 10−3
𝑃𝑑𝐵𝑚 = 10 log ( ) = −𝟏𝟎 𝒅𝑩𝒎
1 × 10−3
5. Given the system shown below, compute for the total power gain of the system in dB
and in magnitude value. If the input power is 20 W, solve for PO in dBW, dBm, and in
watts.
Solution:
The total power gain in dB is,
𝐴𝑝𝑇 (𝑑𝐵) = 4 + 4 − 4 + 4
𝑨𝒑𝑻 (𝒅𝑩) = 𝟖 𝒅𝑩
But for the power gain in magnitude,
𝑃𝑂
𝐴𝑃 (𝑑𝐵) = 4 𝑑𝐵 = 10 log ( )
𝑃𝑖
𝐴𝑃 1 = 𝐴𝑃 2 = 𝐴𝑃 3 = 2.5118
𝑃𝑂
𝐴𝑃 (𝑑𝐵) = −4 𝑑𝐵 = 10 log ( )
𝑃𝑖
𝐴𝑃 (𝑓𝑖𝑙𝑡𝑒𝑟) = 0.3981
Hence,
𝐴𝑃 = (2.5118)(2.5118)(0.3981)(2.5118)
𝑨𝑷 = 𝟔. 𝟑𝟎𝟖𝟗
Converting the input power to dBW and dBm, we have,
20
𝑃𝑖𝑛 (𝑑𝐵𝑊) = 10 log ( ) = 13.0102 𝑑𝐵𝑊
1𝑊
20
𝑃𝑖𝑛 (𝑑𝐵𝑚) = 10 log ( ) = 43.0102 𝑑𝐵𝑚
1 × 10−3
Therefore, the output power is,
𝑃𝑜𝑢𝑡 (𝑑𝐵𝑊) = 13.0102 + 4 + 4 − 4 + 4
𝑷𝒐𝒖𝒕 (𝒅𝑩𝑾) = 𝟐𝟏. 𝟎𝟏𝟎𝟐 𝒅𝑩𝑾
𝑃𝑜𝑢𝑡 (𝑑𝐵𝑚) = 43.0102 + 4 + 4 − 4 + 4
𝑷𝒐𝒖𝒕 (𝒅𝑩𝒎) = 𝟓𝟏. 𝟎𝟏𝟎𝟐 𝒅𝑩𝒎
Solving the output power in watts,
𝑃𝑜
21.0102 𝑑𝐵𝑊 = 10 log ( )
1𝑊
𝑷𝑶 = 𝟏𝟐𝟔. 𝟏𝟖𝟖𝟓 𝑾
Also, alternative solution can be,
𝑃𝑂 = 𝐴𝑃 𝑃𝑖𝑛 = (6.3089)(20)
𝑷𝑶 = 𝟏𝟐𝟔. 𝟏𝟕𝟖 𝑾
126.178
𝑃𝑜𝑢𝑡 (𝑑𝐵𝑊) = 10 log ( )
1𝑊
𝑷𝒐𝒖𝒕 (𝒅𝑩𝑾) = 𝟐𝟏. 𝟎𝟎𝟗𝟖 𝒅𝑩𝑾
126.178
𝑃𝑜𝑢𝑡 (𝑑𝐵𝑚) = 10 log ( )
1 × 10−3
𝑷𝒐𝒖𝒕 (𝒅𝑩𝒎) = 𝟓𝟏. 𝟎𝟎𝟗𝟖 𝒅𝑩𝒎
B. Low Frequency Response
1. Determine the cut-off frequencies and select the overall lower cut-off frequency of the
voltage divider bias BJT amplifier shown below with the following parameters:
CCi = CS = 10 µF RB1 = 50 kΩ RC = 8 kΩ VCC = 25 V
CB = CE = 15 µF RB2 = 15 kΩ RL = 2.2 kΩ β = 100
CCo = CC = 0.5 µF RE = 5 kΩ ro = ∞ Ω
Solution:
Using the test equation first to determine re for dc conditions, we have,
𝛽𝑅𝑒 ≫ 10𝑅2 = (100)(5000) ≫ 10(15000)
500 𝑘Ω ≫ 150𝑘Ω
Since satisfied, solving for VB, we have,
𝑅𝐵2 𝑉𝐶𝐶 (15 × 103 )(25)
𝑉𝐵 ≅ = = 5.7692 𝑉
𝑅𝐵2 + 𝑅𝐵1 15 × 103 + 50 × 103
And,
𝑉𝐸 5.7692 − 0.7
𝐼𝐸 = = = 1.0138 𝑚𝐴
𝑅𝐸 5000
So that,
26 𝑚𝑉
𝑟𝑒 = = 𝟐𝟓. 𝟔𝟒𝟓 Ω
1.0138 𝑚𝐴
And,
𝛽𝑟𝑒 = (100)(25.645) = 𝟐. 𝟓𝟔𝟒𝟓 𝒌Ω
At middle frequencies, we can solve for the voltage gain of the amplifier given by,
𝑉𝑜 𝑉𝑅 𝑟𝑜 ||𝑅𝐶 ||𝑅𝐿
𝐴𝑣 = = 𝐿 = −
𝑉𝑖 𝑉𝑖 𝑟𝑒
But output resistance is infinite, hence,
𝑅𝐶 ||𝑅𝐿 8000 || 2200
𝐴𝑣 = − =− = −𝟔𝟕. 𝟐𝟖𝟑𝟔
𝑟𝑒 25.645
Solving for the cut-off frequency due to the input coupling capacitor,
1
𝑓𝐿 =
2𝜋𝑅𝐶𝑆
But for voltage divider bias amplifier,
1
𝑓𝐿 𝑖𝑛 = 𝑓𝐿𝑆 =
2𝜋𝑅𝑖 𝐶𝑆
Solving for the input resistance,
1
𝑅𝑖 = = 2.0981 𝑘Ω
1 1 1
+ +
50000 15000 2564.5
Therefore,
1
𝑓𝐿 𝑖𝑛 = 𝑓𝐿𝑆 =
2𝜋(2.0981 × 103 )(10 × 10−6 )
𝒇𝑳 𝒊𝒏 = 𝒇𝑳𝑺 = 𝟕. 𝟓𝟖𝟓𝟔 𝑯𝒛
Solving for the cut-off frequency due to the output coupling capacitor,
1
𝑓𝐿𝐶 = 𝑓𝐿𝑂𝑈𝑇 =
2𝜋(𝑅𝑜 + 𝑅𝐿 )𝐶𝐶
But for voltage divider bias, output impedance is,
𝑅𝑜 = 𝑅𝐶 ||𝑟𝑜 ≅ 𝑅𝐶
So that,
1
𝑓𝐿𝐶 = 𝑓𝐿𝑂𝑈𝑇 =
2𝜋(8 × 103 + 2.2 × 103 )(0.5 × 10−6 )
𝒇𝑳𝑪 = 𝒇𝑳𝑶𝑼𝑻 = 𝟑𝟏. 𝟐𝟎𝟔𝟖 𝑯𝒛
Solving for the cut-off frequency due to the bypass capacitor,
1
𝑓𝐿𝐸 = 𝑓𝐿𝐵 =
2𝜋𝑅𝑒𝑞 𝐶𝐸
But for voltage divider bias, the equivalent resistance is,
𝑅𝐵1 ||𝑅𝐵2
𝑅𝑒𝑞 = 𝑅𝐸 || ( + 𝑟𝑒 )
𝛽
50 × 103 ||15 × 103
𝑅𝑒𝑞 = 5 × 103 || ( + 25.645)
100
𝑅𝑒𝑞 = 137.1608 Ω
Therefore,
1
𝑓𝐿𝐸 = 𝑓𝐿𝐵 =
2𝜋(137.1608)(15 × 10−6 )
𝒇𝑳𝑬 = 𝒇𝑳𝑩 = 𝟕𝟕. 𝟑𝟓𝟔𝟖 𝑯𝒛
Since, 𝑓𝐿𝐸 ≫ 𝑓𝐿𝐶 or 𝑓𝐿 𝑆 the bypass capacitor is determining the overall lower cutoff
frequency of the amplifier, that is,
𝒇𝑳 = 𝟕𝟕. 𝟑𝟓𝟔𝟖 𝑯𝒛
2. Solve the previous problem but with a source resistance, RS = Rsig, with a value of 1 kΩ.
The gain of interest will now be 𝑉𝑜 /𝑉𝑠 instead of 𝑉𝑜 /𝑉𝑖 . Compare the results.
Solution:
The resulting amplifier circuit is shown below,
The dc conditions remain the same,
𝒓𝒆 = 𝟐𝟓. 𝟔𝟒𝟓Ω
𝜷𝒓𝒆 = 𝟐. 𝟓𝟔𝟒𝟓 𝒌Ω
At the middle frequencies, the gain will be the same as before,
𝐴𝑣 = −𝟔𝟕. 𝟐𝟖𝟑𝟔
Solving for the cut-off frequency due to the input coupling capacitor, we now have,
1
𝑓𝐿 𝑖𝑛 = 𝑓𝐿𝑆 =
2𝜋(𝑅𝑆 + 𝑅𝑖 )𝐶𝑆
1
𝑍𝑖 = 𝑅𝑖 = = 2.0981 𝑘Ω
1 1 1
+ +
50000 15000 2564.5
So that,
1
𝑓𝐿 𝑖𝑛 = 𝑓𝐿𝑆 =
2𝜋(1 × 103 + 2.0981 × 103 )(10 × 10−6 )
𝒇𝑳 𝒊𝒏 = 𝒇𝑳𝑺 = 𝟓. 𝟏𝟑𝟕𝟏 𝑯𝒛
Solving for the gain of interest based on the above figure,
𝑅𝑖 𝑉𝑠
𝑉𝑏 =
𝑅𝑖 + 𝑅𝑠
𝑉𝑏 𝑅𝑖 2.0981
= = = 0.6772
𝑉𝑠 𝑅𝑖 + 𝑅𝑠 2.0981 + 1
So that,
𝑉𝑜 𝑉𝑜 𝑉𝑏
𝐴𝑣 𝑠 = = ∙ = (−67.2836)(0.6772) = −𝟒𝟓. 𝟓𝟔𝟓𝟗
𝑉𝑠 𝑉𝑖 𝑉𝑠
Solving for the cut-off frequency due to the output coupling capacitor, we will have
similar derivation of formula hence, the same answer,
𝒇𝑳𝑪 = 𝒇𝑳𝑶𝑼𝑻 = 𝟑𝟏. 𝟐𝟎𝟔𝟖 𝑯𝒛
Solving for the cut-off frequency due to the bypass capacitor, we now have,
𝑅𝑆 ′
𝑅𝑒𝑞 = 𝑅𝐸 || ( + 𝑟𝑒 )
𝛽
where
𝑅𝑆′ = 𝑅𝑆 ||𝑅𝐵
So that,
1
𝑅𝑆′ = = 920.2453 Ω
1 1 1
+ +
1000 50000 15000
Therefore,
920.2453
𝑅𝑒𝑞 = 5 × 103 || ( + 25.645)
100
𝑅𝑒𝑞 = 34.6062 Ω
Hence,
1 1
𝑓𝐿𝐸 = 𝑓𝐿𝐵 = =
2𝜋𝑅𝑒𝑞 𝐶𝐸 2𝜋(34.6062)(15 × 10−6 )
𝒇𝑳𝑬 = 𝒇𝑳𝑩 = 𝟑𝟎𝟔. 𝟔𝟎𝟏𝟗 𝑯𝒛
Since, 𝑓𝐿𝐸 ≫ 𝑓𝐿𝐶 or 𝑓𝐿 𝑆 the bypass capacitor is determining the overall lower cutoff
frequency of the amplifier, that is,
𝒇𝑳 = 𝟑𝟎𝟔. 𝟔𝟎𝟏𝟗 𝑯𝒛
It can be observed that there is a severe reduction in overall gain (at 32% level) but a
corresponding reduction in the lower cutoff frequency. Recall that the highest of the
low cutoff frequencies will determine the overall low cutoff frequency for the amplifier.
The results point out that the internal series resistance can have a very strong impact
on the midband gain, but on the other side of the coin it can improve the overall
bandwidth. In this case the loss in gain far outweighs any gain in bandwidth.
Keep in mind that for any transistor configuration it is simply necessary to isolate each
RC combination formed by a capacitive element and determine the break frequencies.
The resulting frequencies will then determine whether there is a strong interaction
between capacitive elements in determining the overall response and which element
will have the greatest effect on establishing the lower cutoff frequency.
3. Determine the cut-off frequencies and select the overall lower cut-off frequency on the
common source (self-bias) FET amplifier shown below. The following parameters are
to be considered:
CCi = CG = 0.05 µF Rsig = 11 kΩ RS = 1.8 kΩ VP = -7 V
CCo = CC = 1 µF RG = 1 MΩ RL = 3.3 kΩ VDD = 20 V
Cb = CS = 3.1 µF RD = 5.3 kΩ IDSS = 10 mA rd = ∞ Ω
Solution:
Using DC analysis to solve for the transconductance (will be needed later in this
solution),
𝑉𝐺𝑆𝑄 2𝐼𝐷𝑆𝑆 𝑉𝐺𝑆𝑄
𝑔𝑚 = 𝑔𝑚0 (1 − )= (1 − )
𝑉𝑃 |𝑉𝑃 | 𝑉𝑃
But,
𝑉𝐺𝑆𝑄 = −(𝐼𝐷𝑄 )(𝑅𝑆 )
2
𝑉𝐺𝑆𝑄
𝐼𝐷𝑄 = 𝐼𝐷 = 𝐼𝐷𝑆𝑆 [1 − ]
𝑉𝑃
2
−(𝐼𝐷𝑄 )(1.8 × 103 )
𝐼𝐷𝑄 = (10 × 10−3 ) [1 − ]
−7
𝐼𝐷𝑄1 = 2.1047 𝑚𝐴
𝐼𝐷𝑄2 = 7.1853 𝑚𝐴
To solve for the quiescent VGS, we will use IDQ1 due that this value will be first reached
when VGS is more negative, so that,
𝑉𝐺𝑆𝑄 = −(2.1047 × 10−3 )(1800) = −3.7884 𝑉
Therefore,
2(10 × 10−3 ) −3.7884
𝑔𝑚 = (1 − )
|−7| −7
𝑔𝑚 = 1.3108 𝑚𝑆
Solving for the cut-off frequency due to the input coupling capacitor at the gate
terminal, we have,
1
𝑓𝐿 𝑖𝑛 = 𝑓𝐿 𝐺 =
2𝜋(𝑅𝑠𝑖𝑔 + 𝑅𝑖 )𝐶𝐺
Also, for this configuration,
𝑅𝑖 = 𝑅𝐺
Therefore,
1
𝑓𝐿 𝑖𝑛 = 𝑓𝐿 𝐺 =
2𝜋(1 × 106 + 11 × 103 )(0.05 × 10−6 )
𝒇𝑳 𝒊𝒏 = 𝒇𝑳 𝑮 = 𝟑. 𝟏𝟒𝟖𝟒 𝑯𝒛
Solving for the cut-off frequency due to the output coupling capacitor at the drain
terminal, we have,
1
𝑓𝐿 𝑜𝑢𝑡 = 𝑓𝐿 𝐶 =
2𝜋(𝑅𝐿 + 𝑅𝑜 )𝐶𝐶
Also, for this configuration,
𝑅𝑜 = 𝑅𝐷 ||𝑟𝑑 ≅ 𝑅𝐷
Therefore,
1
𝑓𝐿 𝑜𝑢𝑡 = 𝑓𝐿 𝐶 =
2𝜋(3.3 × 103
+ 5.3 × 103 )(1 × 10−6 )
𝒇𝑳 𝒐𝒖𝒕 = 𝒇𝑳 𝑪 = 𝟏𝟖. 𝟓𝟎𝟔𝟑 𝑯𝒛
Solving for the cut-off frequency due to the bypass capacitor at the source terminal, we
have,
1
𝑓𝐿 𝑏 = 𝑓𝐿 𝑆 =
2𝜋𝑅𝑒𝑞 𝐶𝑆
Also, for this configuration,
𝑅𝑆
𝑅𝑒𝑞 =
𝑅 (1 + 𝑔𝑚 𝑟𝑑 )
1+ 𝑆
(𝑟𝑑 + 𝑅𝐷 ||𝑅𝐿 )
But since,
𝑟𝑑 = ∞ Ω
1
𝑅𝑒𝑞 = 𝑅𝑆 ||
𝑔𝑚
Hence,
1
𝑓𝐿 𝑏 = 𝑓𝐿 𝑆 =
1
2𝜋(1.8 × 103 || )(3.1 × 10−6 )
1.3108 × 10−3
𝒇𝑳 𝒃 = 𝒇𝑳 𝑺 = 𝟗𝟓. 𝟖𝟏𝟗𝟐 𝑯𝒛
Since, 𝑓𝐿𝑆 ≫ 𝑓𝐿𝐶 or 𝑓𝐿 𝐺 the bypass capacitor is determining the overall lower cutoff
frequency of the amplifier, that is,
𝒇𝑳 = 𝟗𝟓. 𝟖𝟏𝟗𝟐 𝑯𝒛
C. High Frequency Response
1. Determine the cut-off frequencies in the high frequency region and select the overall
higher cut-off frequency of the transistor amplifier network in B.2 with the following
parameters.
CCi = CS = 10 µF RB1 = 50 kΩ RC = 8 kΩ VCC = 25 V
CB = CE = 15 µF RB2 = 15 kΩ RL = 2.2 kΩ β = 100
CCo = CC = 0.5 µF RE = 5 kΩ ro = ∞ Ω RS = Rsig = 1 kΩ
Cbe = 36 pF Cbc = 4 pF Cce = 1 pF CWi = 6 pF
CWo = 8 pF
Solution:
From the same problem, we have,
𝛽𝑟𝑒 = 2.5645 𝑘Ω
And, using the gain without the effects of RS,
𝐴𝑣 = −67.2836
Solving for the higher cut-off frequency due to input capacitances, we have,
1
𝑓𝐻𝑖 =
2𝜋𝑅𝑇𝐻𝑖 𝐶𝑖
But,
𝑅𝑇𝐻𝑖 = 𝑅𝑆 ||𝑅𝑖
𝑅𝑖 = 𝑅𝐵 ||𝛽𝑟𝑒
1
𝑅𝑖 = = 2.0981 𝑘Ω
1 1 1
+ +
50000 15000 2.5645 × 103
(1 × 103 )(2.0981 × 103 )
𝑅𝑇𝐻 𝑖 = = 677.2286 Ω
1 × 103 + 2.0981 × 103
And,
𝐶𝑖 = 𝐶𝑤𝑖 + 𝐶𝑏𝑒 + 𝐶𝑀𝑖
𝐶𝑖 = 6 𝑝𝐹 + 36 𝑝𝐹 + (1 − (−67.2836))(4 𝑝𝐹)
𝐶𝑖 = 315.1344 𝑝𝐹
Hence,
1
𝑓𝐻𝑖 =
2𝜋(677.2286)(315.1344 × 10−12 )
𝒇𝑯𝒊 = 𝟕𝟒𝟓. 𝟕𝟒𝟐𝟕 𝒌𝑯𝒛
Solving for the higher cut-off frequency due to output capacitances, we have,
1
𝑓𝐻𝑜 =
2𝜋𝑅𝑇𝐻𝑜 𝐶𝑜
But,
𝑅𝑇𝐻𝑜 = 𝑅𝑜 ||𝑅𝐿
𝑅𝑜 = 𝑅𝐶 ||𝑟𝑜 ≅ 𝑅𝐶
(8 × 103 )(2.2 × 103 )
𝑅𝑇𝐻𝑜 = = 1.7254 𝑘Ω
8 × 103 + 2.2 × 103
And,
𝐶𝑜 = 𝐶𝑤𝑜 + 𝐶𝑐𝑒 + 𝐶𝑀𝑜
1
𝐶𝑜 = 8 𝑝𝐹 + 1 𝑝𝐹 + (1 − ) (4 𝑝𝐹)
−67.2836
𝐶𝑜 = 13.0594 𝑝𝐹
Hence,
1
𝑓𝐻𝑜 =
2𝜋(1.7254 × 103 )(13.0594
× 10−12 )
𝒇𝑯𝒐 = 𝟕. 𝟎𝟔𝟑𝟐 𝑴𝑯𝒛
Since, 𝑓𝐻𝑜 ≫ 𝑓𝐻𝑖 the input capacitors are determining the overall higher cutoff
frequency of the amplifier, that is,
𝒇𝑯 = 𝟕𝟒𝟓. 𝟕𝟒𝟐𝟕 𝒌𝑯𝒛
2. Determine the high cut-off frequencies for the network below and select the overall
higher cut-off frequency, using the following parameters:
CCi = CG = 0.05 µF Rsig = 11 kΩ RS = 1.8 kΩ VP = -7 V
CCo = CC = 1 µF RG = 1 MΩ RL = 3.3 kΩ VDD = 20 V
Cb = CS = 3.1 µF RD = 5.3 kΩ IDSS = 10 mA rd = ∞ Ω
Cgd = 2 pF Cgs = 4 pF Cds = 0.5 pF CWi = 5 pF
CWo = 6 pF
Solution:
From the similar problem, the formula for the gain at the middle frequency is,
𝑉𝑜
𝐴𝑣 = = −𝑔𝑚 (𝑅𝐷 ||𝑅𝐿 )
𝑉𝑖
𝐴𝑣 = −(1.3108 × 10−3 )(5.3 × 103 ||3.3 × 103 )
𝐴𝑣 = −2.6658
Solving for the higher cut-off frequency due to input capacitances, we have,
1
𝑓𝐻𝑖 =
2𝜋𝑅𝑇𝐻𝑖 𝐶𝑖
But,
𝑅𝑇𝐻 𝑖 = 𝑅𝑠𝑖𝑔 ||𝑅𝐺
𝑅𝑇𝐻𝑖 = (11 × 103 )||(1 × 106 ) = 10.8803 𝑘Ω
And,
𝐶𝑖 = 𝐶𝑤𝑖 + 𝐶𝑔𝑠 + 𝐶𝑀𝑖
𝐶𝑖 = 5 𝑝𝐹 + 4 𝑝𝐹 + (1 − (−2.6658))(2 𝑝𝐹)
𝐶𝑖 = 16.3316 𝑝𝐹
Hence,
1
𝑓𝐻𝑖 =
2𝜋(10.8803 × 103 )(16.3316 × 10−12 )
𝒇𝑯𝒊 = 𝟖𝟗𝟓. 𝟔𝟕𝟓𝟏 𝒌𝑯𝒛
Solving for the higher cut-off frequency due to output capacitances, we have,
1
𝑓𝐻𝑜 =
2𝜋𝑅𝑇𝐻𝑜 𝐶𝑜
But,
𝑅𝑇𝐻𝑜 = 𝑅𝑜 ||𝑅𝐿
𝑅𝑜 = 𝑅𝐷 ||𝑟𝑑 ≅ 𝑅𝐷
𝑅𝑇𝐻𝑜 = 𝑅𝐷 ||𝑅𝐿 = (5.3 × 103 ||3.3 × 103 ) = 2.0337 𝑘Ω
And,
𝐶𝑜 = 𝐶𝑤𝑜 + 𝐶𝑑𝑠 + 𝐶𝑀𝑜
1
𝐶𝑜 = 6 𝑝𝐹 + 0.5 𝑝𝐹 + (1 − ) (2 𝑝𝐹)
−2.6658
𝐶𝑜 = 9.2502 𝑝𝐹
Hence,
1
𝑓𝐻𝑜 =
2𝜋(2.0337 × 103 )(9.2502 × 10−12 )
𝒇𝑯𝒐 = 𝟖. 𝟒𝟔𝟎𝟏 𝑴𝑯𝒛
Since, 𝑓𝐻𝑜 ≫ 𝑓𝐻𝑖 the input capacitors are determining the overall higher cutoff
frequency of the amplifier, that is,
𝒇𝑯 = 𝟖𝟗𝟓. 𝟔𝟕𝟓𝟏 𝒌𝑯𝒛
D. Frequency Response of Cascaded Amplifiers
1. Cascade the BJT and FET amplifiers solved previously. What overall lower and higher
cut-off frequencies will be considered?
Solution:
The following cut-off frequencies are listed:
𝒇𝑳𝑩𝑱𝑻 = 𝟑𝟎𝟔. 𝟔𝟎𝟏𝟗 𝑯𝒛
𝒇𝑯𝑩𝑱𝑻 = 𝟕𝟒𝟓. 𝟕𝟒𝟐𝟕 𝒌𝑯𝒛
𝒇𝑳𝑭𝑬𝑻 = 𝟗𝟓. 𝟖𝟏𝟗𝟐 𝑯𝒛
𝒇𝑯𝑭𝑬𝑻 = 𝟖𝟗𝟓. 𝟔𝟕𝟓𝟏 𝒌𝑯𝒛
Cascading the two amplifiers, we must choose the highest lower cut-off frequency and
the lowest higher cut-off frequency to get the overall cut-off frequencies, hence
𝒇𝑳𝑺 = 𝟑𝟎𝟔. 𝟔𝟎𝟏𝟗 𝑯𝒛
𝒇𝑯𝑺 = 𝟕𝟒𝟓. 𝟕𝟒𝟐𝟕 𝒌𝑯𝒛
2. Cascading 5 identical BJT amplifiers solved previously, what would be the overall cut-
off frequencies?
Solution:
Using the formula for the lower cut-off frequency,
𝑓𝐿
𝑓𝐿𝑆 =
√2𝑛1 − 1
306.6019
𝑓𝐿𝑆 =
√215 − 1
𝒇𝑳𝑺 = 𝟕𝟗𝟓. 𝟏 𝑯𝒛
Using the formula for the higher cut-off frequency,
1
𝑓𝐻𝑆 = 𝑓𝐻 √2𝑛 − 1
1
𝑓𝐻𝑆 = (745.7427 × 103 )√25 − 1
𝒇𝑯𝑺 = 𝟐𝟖𝟕. 𝟓𝟔𝟗 𝒌𝑯𝒛
3. Cascading 10 identical FET amplifiers similar on the previously solved problems will
produce what cut-off frequencies?
Solution:
Using the formula for the lower cut-off frequency,
𝑓𝐿
𝑓𝐿𝑆 =
√2𝑛1 − 1
95.8192
𝑓𝐿𝑆 =
1
√210 −1
𝒇𝑳𝑺 = 𝟑𝟓𝟕. 𝟔𝟔𝟎𝟏 𝑯𝒛
Using the formula for the higher cut-off frequency,
1
𝑓𝐻𝑆 = 𝑓𝐻 √2𝑛 − 1
1
𝑓𝐻𝑆 = (895.6751 × 103 )√210 − 1
𝒇𝑯𝑺 = 𝟐𝟑𝟗. 𝟗𝟓𝟔𝟒 𝒌𝑯𝒛