3. The output can drive TTL and has a Ans.

Ans. (b) : In an 741 Op-amp PIN 2 & PIN 3 is the input

temperature stability of 80 parts per pin and PIN 6 is output pin there are total 8 pin in IC
million (ppm) per degree Celsius change in 741.
temperature or equivalently 0.008% º C.
Which of the above statements are not correct?
(a) 1 and 2 only (b) 1 and 3 only
(c) 1, 2 and 3 (d) 2 and 3 only
IES-2021
67. Which of the following is used in integrated
Ans.(c) :
circuits?
(a) microstrip line (b) coaxial line
(c) twin wire line (d) shielded cable
Mizoram PSC AE/SDO-2012 Paper-III
Ans. (a) : Micro strip line is used in integrated circuit.
555 timer- The 555 timer chip is extremely robust and For design the Micro strip line substrate should be
stable 8-pin device. grounded. Typical characteristic impedance of micro
For 555 timer IC
strip line is 50 Ω .
VCC = 5V to 18V
higher output current (Imax) = 200mA 68. In the process of fabricating monolithic
Temperature stability = 0.005% /ºC integrated circuits :
64. Which one of the following statements is (a) Only passive components are fabricated on
correct regarding integrated circuit the same chip
fabrication? (b) Active and passive components are fabricated
(a) IC offers increased reliability, improved on the separate chips
performance, high speed and lower power (c) The active and passive components are
consumption. fabricated on the same chip
(b) IC is a miniature, low cost electronic circuit (d) Only active components are fabricated on the
fabricated on a multi crystal chip of silicon. chip
(c) IC is a miniature, high cost electronic circuit KVS TGT (WE)- 2017, 2016
fabricated on a multi crystal chip of silicon. Ans. (c) : The monolithic fabrication process consist of
(d) IC offers decreased reliability, improved water preparation, epitaxial growth, diffused isolation, base
performance, low speed and higher power and emitter diffusion, pre-ohmic etch and final testing.
consumption. All the active and passive components required for the
IES-2021 circuit are fabricated on same chip.
Ans.(a) : Major advantage of integrated circuit- 69. Which one of the following requires additional
IC offers increases reliability, improved performance process steps in their fabrication?
high speed and lower power consumption. (a) Thin film resistor (b) Epitaxial resistor
More reliable because of the elimination of soldered
(c) Pinched resistor (d) Junction resistor
joints and the need for fewer interconnection.
ESE-2022
Increased operating speed because of on absence of
parasitic capacitance effect. Ans. (a) : Structure wise there are two types of resistors
IC is low cost electronic circuit fabricated on a like thin film and thick film resistors. The thin film
single crystal chip. resistors are a type of resistor that possess a thin
resistive layer sat on top of ceramic base. Thin film
65. Silicon has a preference in IC technology
because resistors are generally much more accurate, precise and
(a) it is an indirect semiconductor stable than thick film resistors.
(b) it is a covalent semiconductor 70. In monolithic integrated circuits, the
(c) it is an elemental semiconductor concentration of acceptor atoms in the region
(d) of the availability of nature oxides SiO2 between isolation islands will be
BSNL (JTO)-2006 (a) much higher than in the p-type substrate
Ans. (d) : Silicon has a preference in IC technology (b) much lesser than in the p-type substrate
because of the availability of nature oxide SiO2. (c) equal to the p-type substrate
66. In op-amp IC741, output is taken from the pin (d) not equal to the p-type substrate
number ESE-2022
(a) 3 (b) 6 Ans. (a): In monolithic integrated circuits the concentration
(c) 7 (d) 8 of acceptor atoms in the region between isolation Islands
Mizoram PSC Jr. Grade-2015, Paper-II will be much higher than in the p-type substrate.

Electronic Devices & Circuits 198 YCT

02.
Analog Electronics
Vs − Vz
(i) Diode Circuit = 10mA + IL
100
10 − 5
1. Determine the current I for the Network shown = 10mA + IL
below. 100
5
= 10mA + IL
100
50 mA = 10mA + IL
IL = 40mA
V 5
R L = z = × 103
IL 40
R L = 125Ω
(a) 5.45 mA (b) 6.95 mA Now
(c) 8.95 mA (d) 7.45 mA IS = Izmax +ILmin
UPPSC ITI Principal/Asstt. Director-09.01.2022
where ILmin →0
Ans. (b) : IS = Izmax
Pmin = Pmax
Pmax = Iz max × Vz max
Pmin = Pmax = 50mA × 5V
= 250 mW
3. Using a dc and ac voltmeter to measure the
output signal from a filter circuit, we have
obtain readings of 25 V dc and 1.5 V rms.
E1 − IR − 0.7 − 4 = 0
Calculate the ripple of the filter output voltage.
20 − 0.7 − 4 15.3 × 10−3 (a) 12% (b) 6%
I= = = 6.95mA (c) 4.24% (d) 8.48%
2.2 × 103 2.2
UPPSC ITI Principal/Asstt. Director-09.01.2022
I = 6.95mA
Ans. (b) : Ripple of the filter output voltage
2. In the circuit shown below, the knee current of V ( rms )
the ideal zener diode is 10 mA. To maintain 5V (γ) = r × 100
across RL, the minimum value of RL in Ω and Vdc
minimum power rating of the zener diode in 1.5
mW, respectively, are = ×100
25
=6%
4. What are the output voltage levels for the given
circuit? (Assume Si diode)

(a) 125 and 250 (b) 125 and 125

(c) 250 and 125 (d) 250 and 250
UPPSC ITI Principal/Asstt. Director-09.01.2022
Nagaland PSC (CTSE) Diploma-2017, Paper II
GATE-2013 (a) – 16 V, 3.3 V (b) 16 V, 3.3 V
Ans. (a) : Iz = knee current = 10 mA (c) 16 V, – 3.3 V (d) –16 V, – 3.3 V
Vs = 10V, Vz = zener voltage = 5V UPRVUNL AE -19.07.2021, Shift-II
RL = min? Ans. (b) : When
Pmin = ? Vi = +ve voltage → Diode R.B → V0 = Vi = 16V
Is = Iz + IL Vi =–ve voltage → Diode F.B → V0 = 4–0.7 = 3.3.

Analog Electronics 199 YCT

5. For given clamper circuit (Fig.1), find the value
of output voltage, between t1 to t2, Assume the
input as shown in (fig.2) and diode is Silicon
diode.

Now, apply KVL in loop-2

V2 = Vm + V0 .......... (ii)
Putting the value of V0 from equation (i) in equation
(ii) V2 = Vm + Vm V2 = 2Vm
(a) V0 (t1 - t2 ) =9.3 (b) V0 (t1 – t2) = 5.3 Parameter Half Centre Bridge
(c) V0 (t1 – t2) =2.0 (d) V0 ( t1 – t2) =1.3 wave wave
RPSC ACF & FRO 23.02.2021 Average voltage Vm 2Vm 2Vm
Ans. (d) : Diode in on for the negative half cycle π π π
10 - VC + 2 - 0.7 = 0 RMS voltage Vm Vm Vm
VC = 11.3 2 2 2
V0 = V I - VC = 10 - 11.3 PIV Vm 2Vm Vm
= - 1.3 No. of diode 1 2 4
Hence, V0 (t1 - t2) = 1.3 7.
6. In a centre-tap full wave rectifier, Vm is the
peak voltage between the centre-tap and one of
the secondary. The maximum voltage across
the reverse biased diode is
(a) Vm (b) 2 Vm
(c) Vm/2 (d) 3 Vm
APPSC POLY. LECT. 14.03.2020 For the circuit in above figure the zener
Nagaland PSC CTSE (Diploma)-2017, Paper-I
current Iz and power dissipation are
(a) 20.16mA and 151 mW
Nagaland PSC CTSE (Diploma)-2017, Paper-II
(b) 20.16A and 151 W
Kerala PSC Lecturer (NCA) 04.07.2017
(c) 2.016 mA and 151 W
CGPSC SO 14.02.2016
(d) 20.16mA and 151 W
TSPSC Manager (Engg.) - 2015
APPSC Poly. Lect. 15.03.2020
TNPSC AE-2014
Mizoram PSC AE/SDO 2012-Paper-I UPPCL AE-05.11.2019, TNPSC AE- 2019
GATE-2004 CGPSC SO 14.02.2016
IES - 2002, 1993 Ans. (a) :
Ans. (b) :

20 − 7.5
IZ = = 20.16 mA
620
Pz = Vz Iz = 20.16 × 10−3 × 7.5
Peak inverse voltage :- It is a voltage across the diode Pz = 151.2mW
when it is reversed biased. 8. Which of the following is the main application
for +ve half cycle. of Zener diode?
(a) Voltage regulator (b) Rectifier
D1 → F.B. (c) Multivibrator (d) Amplifier
D 2 → R.B. APPSC Poly. Lect. 15.03.2020
Apply KVL in loop-1 RRB JE-01.09.2019, 3:00 PM – 5:00 PM
RRB SSE-03.09.2015, Shift-III
V0 = Vm ...........(i)
RRB SSE 21.12.2014, (Red)
Analog Electronics 200 YCT
Ans. (a) : Zener diode are used for voltage regulation as Ans. (b) : Given data can be represented by circuit,
reference elements, surge suppressors and in switching
application and clipper circuits. The load voltage equals
breakdown voltage VZ of the diode.
9. Schottky diodes drop about 0.3 V when
conducting. This diode is connected in series
with a resistor of 1 kΩ and forward biased with
a battery of 1 V. Calculate the diode current. Here, Vs = 17V, f = 50 Hz
(a) 0.5 mA (b) 0.7 mA Now applying KVL.
(c) 0.3 mA (d) 1 mA VA = V S Vk = 12V
NLC GET -24.11.2020 So,
Ans. (b) : VAK > 0 ⇒ VA –VK > 0
VS – 12 > 0
17 2 sin ωt – 12 ≥ 0
Now, at ωt = 0
Diode ON .
17 2 sin θ = 12
 12 
By using KVL– θ = sin–1  
−1V + 1k × I + 0.3 = 0  17 2 
= 29.943
1000I = 0.7
So, Vs is greater than 12V only in the period of 29.943º
0.7 to 150.05.
I=
1000 So, the conduction period of diode is
I = 0.7mA π – 2θ = π – 2 × 29.943
= 120º
10. The efficiency of half-bridge rectifier under 12. The ripple frequency in a full-wave rectifier is
best condition is: (a) double the input frequency
(a) 25.5% (b) 35% (b) equal to the input frequency
(c) 40.6% (d) 81.2% (c) half of the input frequency
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (d) none of these
Mizoram PSC IOLM -2018, Paper II Nagaland PSC CTSE (Diploma)-2018, Paper-I
Nagaland PSC (CTSE) Diploma-2017, Paper II Nagaland PSC- 2018, Diploma Paper-II
RRB SSE 01.09.2015 Shit-I Mizoram PSC IOLM -2018, Paper II
TNPSC AE-2014 Nagaland PSC (CTSE) Diploma-2017, Paper II
IES - 2013 APGENCO AE- 23.04.2017
Ans. (c) : TNPSC AE-2013
BSNL(JTO)-2002, 2001
Parameters Half-wave Full-wave
Ans. (a) : The ripple frequency in a full-wave rectifier
Average Vm 2Vm is double the input frequency. fr = 2fi.
Voltage π π 13. The ripple factor in case of a full-wave rectifier
RMS Voltage Vm Vm is:
(a) 1.21 (b) 0.50
2 2 (c) 0.48 (d) 1.0
Voltage ripple 1.21 0.482 OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
factor Mizoram PSC IOLM -2018, Paper II
Rectifier 40.6% 81.06% Nagaland PSC (CTSE) Diploma-2017, Paper II
efficiency TSPSC Manager (Engg.) - 2015
11. A half-wave rectifier is used to charge a 12 V TSPSC (Manager) - 2013
battery through a resistance 'R'. The input IES - 2013, 2010, 1998
transformer is fed by 34 V AC with turns ratio Ans. (c) :
2 : 1. Calculate the conduction period of the Ripple factor :-
diode. The amount of AC present in the output the signal is
(a) 136º (b) 120º called as Ripple
(c) 173º (d) 137º •The ripple factor indicates the number of ripple present
ISRO Scientist December, 2017 in d.c output
Analog Electronics 201 YCT
 • Center taped full wave rectifier (PIV) = 2Vm
AC voltage or current for all Q Given, Vm = 300 (full wave rectifier)
components rms value Therefore, center tapped full wave rectifier,
Ripple factor =
Average (DC)value of voltage PIV =2Vm= 2×300 = 600V
or current
16. As compared to a full wave rectifier using 2
diodes, the four diode bridge rectifier has the
2
V  dominant advantage of
γ =  rms  − 1 (a) Higher current carrying
 VDC  (b) Lower peak inverse requirement
Full wave Rectifier γ = 0.48 (c) Lower ripple factor
For half wave Rectifier = 1.21 (d) Higher efficiency
14. A Zener diode in the circuit shown in below Nagaland PSC (CTSE) Diploma-2017, Paper II
figure has a knee current of 5 mA, and a GPSC Asstt. Prof. 11.04.2017
maximum allowed power dissipation of 300 ISRO Scientist Engg.-2011, 2008
mW. What are the minimum and maximum IES - 1993
load currents that can be drawn safely from the Ans. (b) : Given,
circuit, keeping the output voltage V0 constant Full wave rectifier (Center tapped) using number of
at 6 V? diode = 2
And bridge rectifier using diode = 4
Then advantage-
Bridge rectifier peak inverse voltage = Vm
full wave rectifier (Center tapped) PIV = 2Vm
17. The form factor for half wave rectified sine
wave is
(a) 0 mA, 180 mA (b) 5 mA, 110 mA (a) 1.0 (b) 1.11
(c) 10 mA, 55 mA (d) 60 mA, 180 mA (c) 1.44 (d) 1.57
TNPSC AE - 2018 Nagaland PSC (CTSE) Diploma-2017, Paper II
BARC Scientific Officer-2016 TNPSC AE-2014
ISRO Scientist Engg.-2011, 2007 ISRO Scientist Engg. - 2011
GATE-2002, 1996 BSNL (JTO)-2006
Ans. (c) : Given, RMS value V0 (rms)
Iz = 5mA, V0 = Vz = 6V Iknee = 5mA. Ans. (d) : Form Factor = =
Average value V0 (avg )
Rs = 50Ω, Vi = 9V
∴ Max power dissipation 300mW. For Half wave Rectifier
Pz( max ) 300 V /2
∴ I z(max) = = = 50mA FF = m = π/ 2
VZ 6 Vm / π
Vi − Vz 9 − 6 3 FF = 1.57
Q Is = = = = 60mA
Rs 50 50 18. Bridge rectifier are preferred because
Q I L(min) = Is − I z(max) = 60 − 50 = 10mA. (a) They require small transformer
And, I z(max) = Is − I z = 60 − 5 = 55mA (b) Less peak inverse voltage
(c) (a) and (b) both
15. In a full wave rectifier circuit with centre tap (d) None of these
transformer, if voltage between one end of
secondary winding and centre tap is 300V Nagaland PSC CTSE (Diploma)-2018, Paper-I
peak, then PIV (Peak inverse voltage) is RRB SSE 02.09.2015, Shift-I
(a) 300 V (b) 150 V Mizoram PSC IOLM-2010, Paper-II
(c) 600 V (d) 900 V Ans. (c) : Bridge rectifier requires comparatively small
TNPSC AE - 2018 transformers as required for centre tap full wave
Mizoram PSC Jr. Grade-2015, Paper-II rectifier and this is due to no requirement of centre
RRB SSE 01.09.2015, Shift-III tapping at all. Also PIV for diodes in bridge rectifier is
UPPCL AE-16.11.2013 Vm while in centre tap full wave rectifier it is 2Vm, so
ISRO Scientist Engg.-2012 less peak inverse voltage.
Ans. (c) : Q Peak inverse voltage- Peak inverse 19. A 5V reference is drawn from the circuit shown
voltage means that max voltage appears across the in the figure. Zener diode of 400mW and 5V
diode when it is in non conducting. with firing current of 5mA is used. The value of
• Half wave rectifier (PIV) = Vm RS is

Analog Electronics 202 YCT

 Given,
Voltage across AB is 6.2V
Q VAB = VAC + VCB
at 25º C:-
VAB (6.2V) = VAC (0.7V) + VCB(5.5V) at 65ºC
(a) 50 ohms (b) 500 ohms ∵ VCB = 100 × 55mA 
(c) 75 ohms (d) 470 ohms  
 VCB = 5.5V 
ISRO Scientist Engg. 2009
Ans. (a) : For every one degree rise in temperature - 2.5mV
decrease across AC (i.e. base to emitter junction).
2.5mV
VAC = 0.7 − × 40º C
1º C
VAC = 0.7V−0.1 V = 0.6 V
VAB = VAC + VCB
VCB = VAB − VAC
⇒ VCB = 6.2 − 0.6
Given Vz = 5V VCB = 5.6
Load current (IL) = 95 mA Current through - 100Ω
Q Unregulated input V = 10V V
I = I Z + IL I L = CB
R
I = 95mA + 5mA 5.6
I = 100mA IL =
100
Voltage drop across Rs, = 56 × 10 −3
Vs = 10 − 5 = 5V
I L = 56mA
5 5000
Therefore , R s = = = 50Ω 21. In this circuit, V is a sinusoid input with
100mA 100
frequency f, current I contains :
20. The zener diode shown in following figure is I
temperature compensated and current gain β
of transistor is very high. If current through
100 ohm resistor is 55 mA at 25ºC, what is the
approximate current through it at 65ºC

(a) Only f
(b) All harmonics of f
(c) Only even harmonics of f
(d) Only odd harmonics of f
ISRO Scientist Engg.-2012
Ans. (b) :

(a) 55 mA (b) 54 mA
(c) 56 mA (d) 100 mA
ISRO Scientist Engg.-2014
Ans. (c) :

Operation –
If D1 = forward bias
D2 = Reverse bias
Then D1 = diode will be allow the current flow.
If D1 = Reverse bias
D2 = Forward bias
Then, D2 diode will be allow the current flow.
Therefore, current I contain all harmonics of frequency.

Analog Electronics 203 YCT

22. Determine the Voltage transfer characteristics having the following periodical input signal
of the following circuit comprising of Zener 'Vi(t)'?
diodes having identical characteristics with
Zener Breakdown voltage Vz and Diode cut-in
voltage VT.

(Assume cut-in voltage of the Diode=0V;

Forward resistance of the Diode=2Ω)
(a) 1.25 V (b) 2.5 V
(c) 0 V (d) 0.1 V
ISRO Scientist Engg.-2018
Vp Np 1
Ans.(b): = =
Vs Ns 2
Vs = 2Vp
When diode is in forward bias then replaced by forward
resistance of diode = 2Ω
Voltage across 2Ω is
2
V2Ω = × 2 × 5.2 = 0.4V
50 + 2
ISRO Scientist Engg.-2018 Q voltage is connected is reverse polarity
So, V01 = –0.4V
Ans.(a): → ( VT + VZ ) > Vi > 0
When diode D1 is reverse biased
since VZ > Vi
therefore
V0 = Vi
When diode is reverse bias then
→ ( VT + VZ ) < Vi
D1 is reverse breakdown region
D2 is in forward biased with cut in voltage VT
∴ V0 = VZ + VT
→ 0 > Vi > − ( VT + VZ ) V02 = ( −2 × 5.2 ) = +10.4V
D2 acts as zener diode, D1 is in forward biased
So, V0 = − ( VT + VZ )

23. What will be the voltage reading of DC

Voltmeter placed across the terminals of the The DC voltage roads only average value of voltage,
Diode in the given circuit, VDC = Average value of V0,
1  π 2π
= ∫ V01dt + ∫ V02 dt 
2π  0 π 
1 1 1 
= × π× ( −0.4 ) + × π×10.4
2π  2 2 
1
= × 10π = 2.5V
4π

Analog Electronics 204 YCT

24. The output voltage (V0) of the circuit shown in IE = 0.93 A
the given figure is IE = IC + IB = (β + 1) IB
I
IB = E
1+ β
0.93 0.93
= =
1 + β 101
= 9.2 mA
So, the current through the 10 V zener diode is.
(a) Zero (b) 5.7 V
(c) 6.9 V (d) 12.6 V I Z = ( 20 − 9.2 ) mA
ISRO Scientist Engg.-2006 I Z = 10.8mA ≈ 10.3mA
IES - 1995 26. What could be the output current rating of
Ans. (c) : following shunt regulator?

IZ

IL

Zener diode will be forward bias and other will behave (a) 0 < IL < 100mA
as normal diode. (b) 20mA < IL < 100mA
So, voltage drop is 0.6 V and other zener diode will be (c) 0 < IL < 50mA
reverse bias and voltage drop will be 6.3V (d) 10mA < IL < 100mA
V0 = 6.3 + 0.6 ISRO Scientist Engg.-2013
V0 = 6.9 V Ans. (b) : Zener diode operate reverse is reverse bias,
25. Common emitter DC current gain of the Power rating of the diode,
transistor is 100. The current through the 10 V 0.4W = 5 × I (Where IZ = Imax)
max
Zener diode (assuming VBE of the transistor is
0.7 V) is: 0.4
I m ax = = 80mA
5
Q Apply KCL at circuit,
10 − 5
= IZ + IL
50
I Z + IL = 100mA
I L = 100 − 80 = 20mA
Since, IL will not be below 20 mA, the power rating of
(a) 10.3 mA (b) 19.3 mA diode will be broken and I will not be above 100 mA.
(c) 20 mA (d) 40 mA (no longer be in reverse bias).
ISRO Scientist Engg. -2015 So, 20 mA<IL<100mA.
Ans. (a) : Given β = 100 27. A PN junction is series with a 100 ohm resistor
is forward biased so that a current of 100 mA
flows. If the voltage across the combination is
instantaneously reversed to 10V at time t = 0,
the reverse current that flows through the
junction at t = 0 is approximately given by.
(a) 0 mA (b) 200 mA
IB
(c) 50 mA (d) 100 mA
ISRO Scientist Engg.-2011
IE Ans. (d) : The diode is forward biased so that a current
flow = 100 mA.
Applying KVL When immediately switched will be Reversed bias for
20 − 10 short time then allow the flow reverse current and
= I1 forward voltage. This is called reverse recovery time.
0.5 ×103 During this time diode allow current to flow in reverse
I1 = 20mA direction.
10 − 0.7 So t = 0, In reverse bias,
= IE
10 I = 100 mA.

Analog Electronics 205 YCT

28. Output response of a diode clipper circuit
shown in figure will be

(a) 1.2 k ohms (b) 80 ohms

(c) 50 ohms (d) 0 ohms
ISRO Scientist Engg.-2007
GATE-1992
Ans. (b) : Given that-
Vz = 6V, IZK = 5mA

10 − 6 4
I= = = 80mA
50 50
IL max = I–IZK
= (80 – 5) mA
IL max = 75 mA
(d) None of the above
VL 6V
ISRO Scientist Engg.-2016 So, R L min = = = 80Ω
IL max 75mA
Ans.(a): Condition-
(i) If diode is off, then output 30. The voltages at V1 and V2 of the arrangement
VB shown in the figure will be respectively
R

V0 = Vi − VB − IR
( Vi − VB − IR > 0 )
(ii) If diode is on
Vi − VB − IR < 0
V0 = 0
If R>>>0 then, ( I  0 ) , (R = very large)
IR  0 (a) 6 V and 5.4 V (b) 5.4 V and 6 V
(c) 3 V and 5.4 V (d) 6 V and 3 V
Vi − VB > 0
ISRO Scientist Engg.-2007
V0 = Vi − VB Ans. (d) : If we consider given diodes are ideal, then,
Vi − VB < 0 (
voltage VD2 = VD1 = 0 )
V0 = 0
Therefore, only option (b) valid, if IR  0
And option (a) is correct, because V0 never follows Vi
in the given circuit.
29. The 6V Zener diode shown in the figure, has
zero zener resistance and a knee current of
5 mA. The minimum value of R so that the
voltage across it does not fall below 6 V is

Analog Electronics 206 YCT

 VA 2 − VC2 = 3 – 6 = –3 < 0 R o × Vi 20 × 20
V0 = =
Hence D2 is off R o + R L 20 + 20
VA1 − VC1 = 6 – 3 = 3 > 0 20 × 20
V0 = = 10V
40
Therefore zener diode across voltage-
Vz = 10 + 0.2 = 10.2
V0 < 10.2
∴ Diode branch can not operate,
So, V0 = 10V
32. What is the output voltage across the 900 ohm
Hence, D1 is ON and V1 = 6V load in the circuit given below?
If we consider given diodes are practical, then cut-in
voltage across diode, = 0.6 V

(a) 10 V (b) 14.67 V

(c) 20 V (d) 9.47 V
ISRO Scientist Engg.-2010
Ans. (d) : When 20V D1 is ON AND 10V D2 is OFF.
Ω
V1 = 6V, V2 = 3 V
31. The Zener regulator circuit shown below
consists of Si based Zener diode and Ge diode. Ω
The cut-in voltage of Ge diode is 0.2 volts,
whereas cut-in voltage of Si-diode is 0.7 volts.
20 × 900
V0 = = 9.47V
900 + 1000
Output voltage V0 is less than breakdown voltage of D2,
that is 10V, therefore, our assumptions right if D2 is
OFF.
33. In the Voltage regulator circuit as shown
below, the maximum load current iL that can
be drawn is :
(V0) of the Zener regulator circuit is
(a) 10.2 V (b) 10 V
(c) 9.8 V (d) 0.2 V
ISRO Scientist Engg. -2020
Ans. (b) :

(a) 1.4 mA (b) 2.3 mA

(c) 1.8 mA (d) 2.5 mA
(e) 2.8 mA
CGPSC SO 14.02.2016
Operation- Ans. (a) :
Zener off in reverse bias and on in break down
condition.
Or
Vi < Vz = zener diode off
And Vi ≥ Vz = zener diode on
Apply voltage division

Analog Electronics 207 YCT

 30 − 9 Ans. (c) :
IS =
15 × 103
21
IS =
15 × 103
IS = 1.4mA
IS = IL +IZ
I L max = IS max − I Z min Apply KVL in loop,
I L max = IS Q( Iz min = 0 ) 12 − 0.3 − 0.7
RL = = 5.55 × 103 Ω = 5.5kΩ
2 × 10 −3
I L max = 1.4mA
38. If the input applied to circuit is sine waveform
34. In a half wave rectifier, the load current flows
for what part of the cycle. with amplitude 12 Vp-p sine waveform, then
(a) 40º (b) 90º output voltage is .(Assume ideal diode)
(c) 180º (d) 360º
Mizoram PSC IOLM -2018, Paper II
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (c) : In Half wave rectifier we know that the
current flow when diode in ON state. diode ON for
180º. (a) +6 Vp-p (b) +12 Vp
Hence current will flow for 180º (c) – 12 V p-p (d) +12 Vp-p
35. In a full wave rectifier, the current in each UPRVUNL AE -19.07.2021, Shift-II
diode flows for Ans. (b) :
(a) Whole cycle of the input signal
(b) Half cycle of the input signal
(c) More than half cycle of the input signal
(d) None of these
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (b) : In full wave rectifier, either bridge or centre
tapped, the current through each diode will flow for
half cycle. while load current will flow through over full
cycle.
36. To get a peak load voltage of 40V out of a
bridge rectifier. What is the approximate rms
For Vi = + Ve Diode F.B V0 = Vi = +12Vp
value of secondary voltage?
(a) 0V (b) 14.4V For Vi = – Ve Diode R.B V0 = 0.
(c) 28.3V (d) 56.6V 39. The RMS value of load current in a half-wave
Nagaland PSC (CTSE) Diploma-2017, Paper II rectifier is
Ans. (c) : Vm= 40V
(a) I m / 2 (b) Im/2
Vm
V0 (rms) = I I
2 (c) 2 m (d) m
π π
40
V0 (rms) = TNPSC AE - 2018
2
Ans. (b) : For Half wave rectifier–
V0 (rms) = 28.3V
37. What is the value of load resistance used in
circuit shown in the given figure?

Im 2 × π Im 2 I m
I rms = = =
2 × 2π 4 2
(a) 2k ohms (b) 7.5k ohms Im
(c) 5.5k ohms (d) 9k ohms Io( rms ) =
2
UPRVUNL AE -19.07.2021, Shift-II
Analog Electronics 208 YCT
40. The percentage regulation of Half-wave Vo = 11volt
rectifier is
11
V − Vload I D = Vo / R =
(a) no load × 100% 5.6 × 103
Vno load
I D = 1.96 mA
Vload − Vno load
(b) × 100% 43. When the input waveform and circuit of a
Vload Clamper is given as shown in figure and a dc
volt meter indicating the voltage across the
Vno load − Vload
(c) × 100% output A and B (Grounded) – will show
Vload
Vload − Vno load
(d) × 100%
Vno load
TNPSC AE - 2018
Vn − Vf (a) + 10 V (b) – 10 V
Ans. (c) : Voltage regulation = ×100%
Vf (c) + 20 V (d) –20 V
Vno load − Vload TNPSC AE - 2018
For rectifier ⇒ %V.R = × 100% Ans. (d) : Voltage contain by one capacitor = Vm
Vload Vo = – Vm – Vm = –2Vm
41. The output DC voltage of a full-wave rectifier Vo = – 2 × 10
is Vo = −20V
2Vm Vm
(a) Vdc = − Idc R f (b) Vdc = − Idc R f 44. The equivalent dc output voltage of a half wave
π π rectifier is ________ the equivalent dc output
(c) Vdc = 2Vm − Idc R f (d) Vdc = Vm − Idc R f voltage of a full wave rectifier.
TNPSC AE - 2018 (a) equal to (b) half
(c) double (d) not related to
Ans. (a) : For full wave rectifier–
TNPSC AE - 2018
2Vm
Vo(avg) = Ans. (b) : DC output voltage-
π V
When diode resistance is consider– For half wave rectifier VDC = m
π
2Vm 2Vm
V0(avg ) = − I dc × R f For full wave rectifier VDC =
π π
Hence dc output voltage of half wave rectifier is half of
42. For the circuit shown in Figure 1, the Vo and ID
full wave rectifier dc output voltage.
will be
45. For a 20V Zener diode, if temperature is
increased to 100ºC (boiling point of water).
The change in Zener potential will be
(Assume temperature coefficient = 0.072/ºC
and Room temperature = 25º C.)
(a) 0.51V (b) 4.12 V
(c) 1.08 V (d) 7.20 V
(a) Vo = 12 V and ID = 2.1 mA
RPSC ACF & FRO 23.02.2021
(b) Vo = 11.3 V and ID = 2.0 mA
T V
(c) Vo = 11 V and ID = 1.96 mA Ans. (c) : ∆VZ = C Z (T1 − T0 )
(d) Vo = 11.7 V and ID = 2.1 mA 100º C
TNPSC AE - 2018 (0.072/ºC) × 20
= × (100 − 25)
Ans. (c) : Equivalent circuit diagram – 100
∆VZ =1.08 V
46. RC time constant of a clamper circuit should
be
(a) Small enough that the capacitor will not
discharge during non-conducting period of
diode
(b) Large enough that the capacitor will
V0 = Vin – VSi – VGe discharge during non-conducting period of
= 12 – 0.7 – 0.3 diode.
Analog Electronics 209 YCT
 (c) Small enough that the capacitor will −5 + .7 + .7 + 2 ( I1 + I2 ) + 5 = 0
discharge during non-conducting period of
diode 2I1 + 2I2 = −1.4 ………(ii)
(d) Large enough that the capacitor will not 2I1 + 2I 2 = −1.4
discharge during non-conducting period of
diode. 2I1 + 4I 2 = 4.3
RPSC ACF & FRO 23.02.2021 −2I 2 = −10
Ans. (d) : τ = CR I 2 = −5 mA
Values of R and C should produce a time constant 2I1 + 2I2 = −1.4
which us large enough in ensure that capacity remains
almost fully charged during the time period of the 2I1 + 10 = −1.4
signed for good damping action, the RC time constant 2I1 = –11.4 mA
should be at least ten times the time period of the what I1 = –5.7 mA
signed voltage. According to above value
47. The diodes are used in series to
I1 = − ve No possible.
(a) increase current carrying capacity
(b) increase PIV D2 is on and D1 is off
(c) reduce PIV Hence diode D2 is off so
(d) reduce resistance
Mizoram PSC AE/SDO 2012-Paper-I
Ans. (c) : Diodes are connected together in series to
provide a constant DC voltage across the diode
combination the output voltage remain constant and it
decrease the PIV.
48. Consider the circuit shown below. Find the
output voltage V0 for input voltage Vi = 5V. Apply KVL – –10 + 2I2 + 0.7 + 2I2 + 5 = 0
Assume the voltage drop across a conducting 4I2 = 4.3
diode is 0.7 V. I2 = 1.075 A
V0 = 10 – 2I2
V0 = 7.85 Volt
49. In the circuit shown below the diodes are ideal.
Value of V0 is

(a) 8.65 V (b) 6.5 V

(c) 7.85 V (d) 5 V
UPPCL AE- 31.12.2018
(a) –0.8 V (b) 0.5 V
Ans. (c) : Consider both diode are ON
(c) 0.0 V (d) 0.6 V
UPPCL AE- 31.12.2018
Ans. (b) : From the circuit, it is clear that at a time only
diode is conduct, either both will be off.

Apply ground to ground KVL

Loop-1
−10 + 2I2 + 0.7 + 2 ( I1 + I 2 ) + 5 = 0 0.5 − 100I1 − 0.6 = 0 −0.8 − 100I 2 − 0.5 = 0
−10 + 2I2 + 0.7 + 2I1 + 2I2 + 5 = 0 −0.1 = 100I1 −1.3 = 100I2
4I 2 + 2I1 = 4.3 …….. (i) 0.1 1 1.3
I1 = − =− A I2 = −
Loop-2 100 1000 100

Analog Electronics 210 YCT

 I1 = − ve Not possible I 2 = − ve Not possible 53. In a diode clamping, when Rs = 0, the result is
(a) good impedance matching
Hence both diode will OFF so (b) the magnitude of discontinuity in input and
V0 = 0.5 V equal to source voltage. output waveforms is same
50. The circuit shown in the figure is best (c) large source current into the clamping circuit
described as a (d) no clamping operation
TNPSC AE-2014
Ans. (b) : A clamper is a network constructed of a
diode, a resistor, and a capacitor that shifts a waveform
to a different dc level without changing the appearance
of the applied signal.
In a diode clamping, when Rs = 0, the result is the
magnitude of discontinuity in input and output
(a) Bridge rectifier (b) Voltage doubler
waveforms is same.
(c) Ring modulator (d) Clamper
TNPSC AE-2014 54. Clamping circuit theorem is mathematically
GATE-2003 expressed in the standard notation as
Ans. (b) : Voltage Doubler– Af R Af R f
(a) = (b) =
Ar R f Ar R
Ar R f Ar R
(c) = (d) = 1+ f
Af R Af R
TNPSC AE-2014
Ans. (b) : The clamping circuit theorem states that
under steady state conditions, for any input waveform,
the ratio of the area under the output voltage curve in
the forward direction to that in the reverse direction is
If Vi = +Vm
equal to the ratio of Rf/R.
Then VAG = Vm + Vm = 2Vm
D2 operates in forward bias and C2 charges through D2 Af R f
=
upto voltage 2Vm. Ar R
51. At the break point of a clipping circuit, a diode
behaves as 55. A sinusoidal wave of amplitude Vm is applied as
(a) Short circuit and open circuit simultaneously an input to the parallel diode clipping circuit
(b) Short circuit shown in fig. What is its output voltage?
(c) Open circuit
(d) It is difficult to decide
TNPSC AE-2014
Ans. (a) : A clipping circuit requires a minimum of two
components i.e. a diode and a resistor, the input
waveform can be clipped at different levels by simply
changing the battery voltage and by interchanging the
position of various elements. We will use an ideal diode
which acts like a closed switch when forward-biased (a) Output is allowed in between VR and +Vm
and as an open switch when reverse biased. (b) Output is allowed in between –VR and +Vm
52. In the break region of clipping circuit, a diode (c) Output is allowed in between –VR and –Vm
behaves as (d) Output is allowed in between –Vm and VR
(a) fully on
TNPSC AE-2014
(b) it is difficult to decide
(c) fully off Ans. (a) :
(d) neither fully on nor fully off
TNPSC AE-2014
Ans. (d) : Clippers are networks that employ diodes to
"dip" away a portion of an input signal without
distorting the remaining part of the applied waveform.
At the break region of a clipping circuit, a diode
behaves as neither fully on nor fully off.

Analog Electronics 211 YCT

 59. Circuit shown in fig. is a basic

(a) clipping circuit (b) clamping circuit

(c) two level clipper (d) none of these
TNPSC AE-2013
Ans. (b) : This figure is a clamping circuit. A clamping
So, output is allowed in between VR and +Vm. circuit is a circuit that adds a dc level to an ac signal.
56. The effect of dc saturation in a rectifier
transformer is
(a) to decrease the output
(b) to increase the output
(c) to decrease the ac components of the output
(d) none of these 60. What will be the average value of V(t) in the
TNPSC AE-2013 circuit given below
Ans. (a) : A rectifier transformer is a transformer which
include diode or thyristor in the same tank. Voltage
regulation also be include the effect of dc saturation in a
rectifier transformer is to decrease the output.
57. The rectifier, which requires minimum amount
of filtering is (a) – Vm/π (b) – Vm/2π
(a) half-wave rectifier (c) – Vm/ 2 (d) 0
(b) full-wave rectifier MPPSC Forest Service Exam.-2014
(c) voltage doubler circuit Ans. (a) :
(d) SCR half-wave rectifier
TNPSC AE-2013
Ans. (b) : A full wave rectifier produce more output
voltage hence it requires minimum amount of filtering
circuit as compare to other single phase rectifier.
58. In the following circuit diagram, if the input
V1 ≤ VR1, the O/P V0 is Diode is connected from load to source. Hence
V
V0(avg) = − m
π
61. What type of diode circuit is used to add or
restore a dc level to an electrical signal?
(a) Clipper (b) Clamper
(c) Voltage Regulator (d) None of these
Nagaland PSC CTSE (Diploma)-2018, Paper-I
Ans. (b) : A Clamper is a network used to reinsert or
(a) VR1 (b) VR2
restore dc component into a waveform which has been
(c) V1 (d) VR2 – VR1 lost after passing through a processing network such as
TNPSC AE-2013 an amplifier. Hence a clamper is also called dc restorer.
Ans. (a) : When V1 ≤ VR1 diode D1 is ON and D2 is 62. Which type of diode circuit is used to clip off
portions of signal voltages above and below
OFF.
certain levels?
(a) Clipper (b) Clamper
(c) Voltage Regulator (d) None of these
Nagaland PSC CTSE (Diploma)-2018, Paper-I
Ans. (a) : Clippers are networks which employ diodes
to "clip" away a portion of an input signal without
distorting the remaining part of the applied waveform.
63. The RMS value of a half-wave rectified
V0 = VR 1
symmetrical square wave current of 2A is
Analog Electronics 212 YCT
 (a) 2A (b) 1A 40µF capacitor in parallel with a 250Ω resistor.
The diode and transformer resistances and
1 leakage reactance are neglected. If the power
(c) A (d) 3 A
2 line frequency is 50 Hz, the dc current in the
TRB Poly. Lect. -2012 circuit will be
Ans. (a) : (a) 132 mA (b) 144 mA
(c) 156 mA (d) 168 mA
IES-2020
Ans. (a) : Given value
Vrms = 35V, C = 40 µF
RL = 250Ω, f0 = 50 Hz
1 2π 2
2π ∫0
I 2rms = i dt
1  π 2 2π
= ∫ i dt + ∫ 0dt 

2π  0 π 
1 π Q DC output voltage in VDC = IDC × R L
2π ∫0
= 22 dt
VDC = 250 × IDC ......(i)
4π ∴ Single phase full wave rectifier,
= =2
2π I DC
I rms = 2 A VDC = Vm − .......(ii)
4f 0C
64. The circuit shown in the figure is a So,
From equation (i) and (ii)
I
250 × I DC = Vm − DC
4f 0C
I DC
I DC × 250 = 35 2 −
( 4 × 50 × 40 ×10 )
−6

(a) positive clamper (b) negative clamper I DC × 250 = 35 2 − 125I DC

(c) positive clipper (d) negative clipper
DMRC AM S&T-2020 35 2
I DC = = 0.132A
RPCS Lect.-2011 375
Ans. (a) : The circuit shown is a positive clamper. IDC = 132mA
67. A three-phase full wave rectifier with resistive
load has a ripple factor
(a) 0.482 (b) 1.000
(c) 0.055 (d) 0.500
IES-2020
The positive clamper is made up of a voltage source Vi
capacitance C, diode D and load resistance RL, in the Ans. (c) :
above circuit diagram the diode is connected in parallel Ripple factor single phase full wave Rectifier = 0.482
with the output load. So the positive clamper passes the Ripple factor three phase half wave Rectifier = 0.17
input signal to the output load when the diode is reverse Ripple factor for single-phase half-wave rectifier =1.21
biased and blocks the input signal when the diode is Value of ripple factor in three phase Rectifier with
forward biased. resistive load is very less than single phase Rectifier
65. In a zener diode Hence, correct option (c)
(a) Only the P region is heavily doped 68. Crest factor for an alternating current source
(b) Only the N region is heavily doped is the ratio of
(c) Both P and N regions are heavily doped (a) Maximum value of RMS value
(d) Both P and N regions are lightly doped (b) RMS value to maximum value
Nagaland PSC CTSE (Degree)- 2016, Paper-I (c) RMS value to average value
Ans. (c) : A zener diode is a silicon semiconductor (d) Maximum value to average value
device that permit current in reverse direction. It is a IES-2020
heavily doped p-n junction diode.
Peak Value
66. A single phase full wave rectifier uses Ans. (a): Crest factor =
semiconductor diodes. The transformer voltage RMS Value
is 35V rms to center tap. The load consists of a Crest factor for an alternating current source is ratio

Analog Electronics 213 YCT

 of maximum value of RMS value. 70. The components of full-wave voltage doubler
Maximum value of crest factor is half wave Rectifier circuit are
is (a) 2 diodes and 1 capacitor
Type Wave R.M.S Crest (b) 4 diodes and 1 capacitor
wave form value factor (c) 2 diodes and 2 capacitors
(1) Sine (d) 4 diodes and 2 capacitors
1
= 0.707 2 = 1.414
wave IES-2019
2
Ans. (c) :
(2) Full- Full wave voltage doubler circuit diagram
1
= 0.707 2 = 1.414
wave
2
Rectifier
(3) Half 1 2
wave = 0.5
2
Rectifier
69. The input to a bridge rectifier is 230 V (r.m.s),
50 Hz. The d.c. output voltage and the ripple
factor with RL of 100Ω and capacitor filter of
1000µF are
(a) 207 V and 0.028 (b) 325 V and 0.028 Half wave Full wave
(c) 207 V and 0.020 (d) 325 V and 0.020 Parameters
voltage doubler voltage doubler
IES-2019 Ripple content High Low
Ans. (a) : Given, Better than
VS = 230 (rms) Voltage
Poor half-wave •
f = 50 Hz regulation
voltage doubler
C = 1000 µF
PIV Rating 2Vs max 2Vs max
RL = 100Ω
The maximum
voltage across 2Vs max Vs max
each capacitor
The circuit consists of 2 capacitor and 2 diode
71. The peak-to-peak ripple voltage for a half-
wave rectifier and filter circuit operating at 60
Hz, which has a 680 µF reservoir capacitor, an
Vm average output of 28 V and 200Ω load
Bridge rectifier, Vrms = resistance, will be nearly.
2 (a) 2.5 V (b) 3.4 V
Vm = 2 Vrms .....(i) (c) 4.3 V (d) 5.2 V
IES-2019
2Vm
Q VDC = Ans. (b) Given-
π
2 × 2 × Vrms
=
π
2 × 1.41× 230
=
3.14 R L = 200Ω
= 206.56 Volt f = 60Hz
VDC = 207 Volt C = 680µF
Ripple factor, Vdc = 28V
1
Rf = • Peak to peak ripple voltage-
4 × 3f CR L I Vdc 28
Vr = dc = =
1 f C f C ⋅ R L 60 × 680 × 10−6 × 200
=
4 × 3 × 50 × 1000 × 10−6 ×100 28
Vr = = 3.43Volt
Ripple factor (Rf) = 0.0288 6 × 104 × 68 × 10−6 × 2
Analog Electronics 214 YCT
72. The voltage transfer characteristics as shown in 75. A full wave rectifier uses 2 diodes. The internal
the figure will relate to a resistance of each diode is 20Ω. The
transformer RMS secondary voltage from
centre tap to each end of secondary is 50 V and
the load resistance is 980Ω. Mean load current
will be
(a) 45 A (b) 4.5 A
(c) 45 mA (d) 45µA
IES-2015
1. Voltage regulator Ans. (c) : Given,
2. Half-wave rectifier
3. Full-wave rectifier
Which of the above is/are correct?
(a) 1 only (b) 2 only
(c) 1 and 2 (d) 1 and 3
IES-2018
Ans. (a) : Voltage Regulator- A transformer having its
primary winding in shunt and its secondary winding in RL = 980Ω , Rf = 20Ω
series with alternating-current circuit the voltage of
which may be regulated by varying of which may be Vrms = 50V Vm = 50 2
regulated by varying the voltage ratio of transformation. Vm1 = Vm2 = Vm = 50 2
73. The capacitance of a full wave rectifier, with
rectifier, with 60 Hz input signal, peak output Vm 50 2 2
Im = = =
voltage Vp = 10 V, load resistance R = 10kΩ R f + R L 20 + 980 20
and input ripple voltage Vr = 0.2V, is
2 Im 2 × 2
(a) 22.7µF (b) 33.3µF IDC = = = 45mA
(c) 41.7µF (d) 83.4µF π 20 × π
IES-2016 76. A full wave rectifier with a centre tapped
transformer supplies dc current of 100 mA to a
Ans. (c) Given
load resistance of 20Ω. The secondary
f = 60Hz, Vp = 10V, R = 10kΩ resistance of transformer is 1Ω. Each diode has
Ripple voltage Vr = 0.2V a forward resistance of 0.5Ω. What are rms
Full-wave rectifier with capacitor filter values of signal voltage across each half of the
secondary as well as dc power supplied to the
VP 10
Ripple voltage = = load ?
2fCR 2 × 60 × 10 ×103 × C (a) 2.39 V and 0.2 Watt
(b) 23.9 V and 2 Watts
10 10 (c) 0.239 V and 20 Watts
0.2 = ,C = = 41.67µF
120 × 10 × 103 × C 0.2 × 120 × 10 ×103 (d) 2.39 V and 2 Watts
74. A power supply uses bridge rectifier with TSGENCO AE-2015, IES - 2014
capacitor input filter. If one of the diodes is Ans. (a) :
defective, then Given,
1. The dc load voltage will be lower than its Rf = 0.5Ω , IL = 100 mA RL = 20Ω
expected value.
I = 100mA
2. Ripple frequency will be lower than its DC
expected value I m = 157mA
3. The surge current will increase manifold. load resistance(R L ) = 20Ω
Which of the above statements are correct?
R F = 0.5Ω
(a) 1 and 2 only (b) 1 and 3 only
(c) 1 and 3 only (d) 1, 2 and 3 R sec = 1Ω
IES-2015
Ans. (d) : Power supply uses bridge rectifier with
capacitor input filter if one of the diodes is defective
then results occurs.
• DC load voltage will be lower than its expected value.
• Ripple frequency will be lower.
• Surge current will increase manifold.
All of the above statements are correct.
Analog Electronics 215 YCT
 2I m When diode is forward biased, if can be Replaced by
Idc = dynamic resistance Rd
π In a half-wave Rectifier, an output d.c voltage is given
π Idc by
Im =
2 Vdc = Idc × R L
I π Idc π × 100 
I rms = m = = mA Im Vm 
2 2 2 2 2 Vdc = × RL ∵  Im = 
π  Rd + RL 
I rms = 111.072 mA
Vm
Vrms = I rms × ( R L + R I + R sec ) Vdc = × RL
π (Rd + RL )
= 111.072 × ( 20 + .5 + 1) Where,
= (111.072 × 21.5) mV R L → load Resistance
= ( 2388.048 ) mV R d → forward diode Resistance
Vrms = 2.39 Volt Vm → maximum supply voltage
PDC = D.C power supply to the load Idc → output d.c current
= IDC 2 × R L Given,
= 100 × 100 × 10 −6 × 20 R d = 25Ω, R L = 800Ω, Vdc = 50V
= 10 −2 × 20 V
Output dc voltage = m ×
800
20 π 800 + 25
= = 0.2W
100 V 800
50 = m ×
PDC = 0.2W π 825
77. A bridge rectifier uses a 9 V a.c. input voltage. 50 × π × 825
The diodes are ideal. What is the d.c. output Vm = 800
voltage ?
(a) 12.726 V (b) –12.726 V V m = 51.562 π Volt
(c) 9 V (d) 8.1 V 79. A 40 V dc supply is connected across - the
IES – 2016, 2014 network comprising of Zener and silicon diodes
as shown. The regulated voltages V01, V02 and
Ans. (d) : Given, source current Is are
Input voltage ( Vrms ) = 9V
Vm
Vrms =
2
Vm = Vrms × 2 = 9 2
2Vm
Output voltage =
π
(a) 2.4 V, 5.1 V and 21.7 mA
2× 9 2 (b) 3 V, 6 V and 22.7 mA
= = 8.1V
π (c) 33 V, 9.3 V and 20.5 mA
78. A half-wave rectifier is used to supply 50 V d.c. (d) 4 V, 10 V and 20 mA
to a resistive load of 800Ω. The diode has IES - 2012
resistance of 25 Ω. What is the required a.c. Ans. (d) :
voltage ?
(a) 50π (b) 51.5π
(c) 25.7π (d) 25π
IES - 2014
Ans. (b) : Given,
RL = 800Ω , Rd = 25Ω
Cut in voltage of Si = 0.7 V
V01 = ( Si + Zener ) in cuting voltage
= 0.7V + 3.3V = 4.0 Volt
V02 = 4V + 6V
= 10V

Analog Electronics 216 YCT

 40 − V02 82. Consider the following statements :
IS = When compared with a bridge rectifier, a
1.5 × 10 3
centre-tapped full wave rectifier:
40 − 10 30
IS = = = 20 mA 1. Has larger transformer utilization factor.
1.5 ×103 1.5 × 103 2. Can be used for floating output terminals i.e.
80. For a full wave rectifier, with sinusoidal input no input terminal is grounded.
and inductor as filter, ripple factor for
maximum load current and minimum load 3. Needs two diodes instead of four.
current conditions are respectively 4. Needs diodes of a lower PIV rating.
(a) 0.1 and 1 (b) 0.1 and 0.47 Which of the above statements are correct ?
(c) 0 and 0.47 (d) 0 and 0.22 (a) 1 and 2 only (b) 1, 2, 3 and 4
IES-2012 (c) 3 only (d) 3 and 4 only
Ans. (c) (For full wave Rectifier) Ripple factor of the IES - 2010
inductor filter is given Ans. (c) :
2 1 (1) Bridge Rectifier are needed four diode but center
γ= × (RL )
3 2  1 + 4ω2 L2  tapped FWR only two diodes
  (2) Center tapped PIV is 2Vm but bridge it is only Vm.
 R2  We need PIV as small as possible.
(1) For maximum load current should be o For center tapped and bridge (FWR)
Put R L = 0, in equation (i) Ripple factor = 0.482%
γ=0 (ii) efficiency = 81.2%
(2) For minimum load current 83.
R L = ∞ open circuit
2
γ=
3 2
2
γ= = 0.4714
4.2426
81. For the circuit shown below, using ideal diode,
the values of voltage and current are The output Vdc from the above circuit is:
(a) 12 2 (b) 12/π
(c) 24/π (d) 12 / 2
IES - 2010
Ans. (a) :

(a) –3 V and 0.6 mA (b) 3 V and 0.0 mA

(c) 3 V and 0.6 mA (d) –3 V and 0.0 mA
IES-2011
Ans. (a) : As diode is forward biased then it will act
like a short circuit (S.C)

For Vi = VmSinωt
Vin = 12V ( Rms value )
Here Vo = Vm
Vm
Vrms =
+3V − ( −3V ) 2
I=
10k Vm = Vrms 2
=
( ) V = 6 = 0.6mA
3 + 3
= 12 2
10 × 103 10 × 103
V = −3V and I = 0.6 mA Vo = Vm = 12 2

Analog Electronics 217 YCT

84.

IES - 2010
Ans. (a) : For (+) half cycle D1 will behave as a open
Consider the above circuit, for Vi = Vm sin ωt, circuit and D2 will behave as a short circuit.
the output voltage V0 for RL → ∞ will be : +Ve half cycle
(a) Zero (b) Vm
(c) 2Vm (d) –Vm
IES - 2010
Ans. (c) :

6.6 || 2.2
Vo = Vi
2.2 + ( 6.6 || 2.2 )
6.6 × 2.2
= 6.6 + 2.2 Vi
6.6 × 2.2
Given circuit is voltage doubler. 2.2 +
6.6 + 2.2
Hence, V0 = 2 Vm
1.65
85. = Vi
2.2 + 1.65
= 0.4285 ×10
V0 = 4.3sin ωt
-Ve half cycle Q for (–) half cycle D2 will behave as a
open circuit while D1 will behave as a short circuit.
Now V0

The correct wave form for output (Vo) for the

above network is :
Vo =
( 6.6 || 2.2 ) V
2.2 + ( 6.6 || 2.2 )
i

= .4285 × 10
V0 = 4.3sin ωt

86. Which of the following does not show non-

linear V-I characteristics ?
(a) Schottky diode
(b) Tunnel diode
(c) Thermistor, at a fixed temperature
(d) p-n junction diode
IES-2009
Analog Electronics 218 YCT
Ans. (c) : Thermistor, At a fixed temperature → It is Positive half cycle-
shows linear V-I characteristics as it simply behaves as Capacitor C1 will charge to Vm
a resistor.
→ Schottky diode, tunnel diode, p-n junction diode are
shows non-linear V-I characteristics.
87. Which of the following components are chosen
to construct a d.c. power supply to supply 6 V
d.c. voltage from 230 V a.c. to operate a tape
recorder ? Negative half cycle-
Capacitor C2 will be charge upto Vm
1. Step down transformer
2. Diodes
3. Resistors and capacitors
4. Three-pin voltage stabilizer
Select the correct answer using the code given
below :
(a) 1, 2 and 3 only (b) 1 and 4 only
(c) 3 and 4 only (d) 1, 2, 3 and 4 Vo = VC1 + VC2 = Vm + Vm = 2Vm
IES - 2008 89. The figure given below shows the transfer
Ans. (d) : characteristics of which one of the following

(1) Step-down Transformer

A step-down transformer is type of transformer that
convert high voltage and low current from the primary
(a) Peak clipper (b) Bottom clipper
side of the transformer to the low voltage and high
(c) Clamper (d) Two level clipper
current on the secondary side.
IES - 2008
(2) Rectifier – A Rectifier is an Electrical device that
converts alternating current (A.C), to rippled D.C. Ans. (a) :
(3) Voltage Stabilizer –Three pin voltage stabilizer
used to convert pulsating d.c. voltage into constant d.c.
voltage to the load.
88. The figure shown is a circuit of which one of
the following ?

Supper position of the wave form is clipped.

if Vin > Vi
Vo = Vf
• So the circuit is a peak clipper.
(a) Bridge rectifier (b) Voltage doubler • Clipper circuit can remove certain portions of an
(c) Rectifier with filter (d) Comparator arbitary wave form near the positive or negative peaks.
IES - 2008 90. Silicon diodes are less suited for low voltage
Ans. (b) : rectifier operation because.
(a) it cannot withstand high temperatures
(b) its reverse saturation current is low
(c) its cut-in voltage is high
(d) its breakdown voltage is high
IES - 2009
Ans. (c) : For Ge = 0.3V cut- in voltage
Si = 0.7 V cut-in voltage

Analog Electronics 219 YCT

 93. A half-wave rectifier having a resistance load
of 1kΩ rectifies an a.c. voltage of 325 V peak
value and the diode has a forward resistance of
100Ω. What is the RMS value of the current ?
(a) 295.4 mA (b) 94.0 mA
(c) 147.7 mA (d) 208.0 mA
IES - 2005
Ans. (c) :
Since cut-in voltage of Ge is low as compare to Si,
while silicon is high cut-in voltage. So it is not suitable
for low voltage Rectifier.
91. In the given circuit, D1 is an ideal germanium
diode and D2 is a silicon diode having its cut-in
voltage as 0.7 V, forward resistance as 20Ω and Given,
reverse saturation current (Is) as 10 nA. What R = 1000Ω
L
are the values of I and V for this circuit,
respectively ? ( Vin )P = 325V, R d = 100Ω
For half wave rectifier Vo
( Vin )max ( Vin )p  325 
( Vo )rms = =  V = 162.5V
2 2  2 
( Vo )rms 162.5 162.5
( Io )rms = = = = 147.7mA
Rd + RL 100 + 1000 1100
94. Select the correct output (Vo) wave shape for a
(a) 60 mA and 0 V (b) 50 mA and 0 V given input (Vi) in the clamping network given
(c) 53 mA and 0.7 V (d) 44 mA and 1.58 V below :
IES - 2006
Ans. (a) :

D1 is Ideal germanium diode.

Hence Vf = 0 when D1 is ON (FB)
Hence voltage across D2 is 0V
And V2 can not be ON, because (as it requires 0.7 V to
be ON)

IES - 2005
Ans. (d) : Positive half cycle-
6 6 ×1000 Vi = +10V, diode is F.B
V = 0, I= = = 60mA
100 100 × 1000 Therefore, Vo = 2V
92. In a half-wave rectifier, if an a.c. supply is 60
Hz, then what is the a.c. ripple at output ?
(a) 30 Hz (b) 60 Hz
(c) 120 Hz (d) 15 Hz
IES - 2005
Ans. (b) : (1) Half wave Rectifier input frequency fin is Here resistance became open because current always
60 Hz, then output frequency fo = 60 Hz. follow shortest path
Then full wave Rectifier frequency Fo = 2 fin Apply KVL in output loop-
• Half wave rectifier ripple factor = 1.21
V0 = 2V
• Full wave rectifier ripple factor = 0.482
Analog Electronics 220 YCT
Negative half cycle- 10 × Vi
Vo =
Vi = −10V 10 + 10
Diode is Reverse bias. Apply KVL at the given 10 × Vi
Vo =
20
Vi
Vo =
2
96. For a full-wave rectifier with shunt capacitor
filter, the peak to peak ripple voltage is
–Vi + VC + Vo = 0 (where f = fundamental power line frequency,
IDC = DC current)
− ( −10 ) + 8 + Vo = 0 (a) 2IDC/f C (b) IDC/f C
Vo = −18V (c) IDC/2f C (d) IDC/4f C
IES - 2003
Ans. (c) : For full wave Rectifier: Capacitor charge
and discharge once half cycle of the time period.
Total charge Transfer
∴ Ripple voltage =
Capacitor
 I ( T 2) 
=  DC 
95. Consider the following circuit  C 
I DC ⋅ T 1
= ∴ T=
2C f
Put value
I DC
Vr =
2fC
For the circuit shown above, which one of the
following is a correct statement ? 97. The average value of the full-wave rectified
(a) D2 does not conduct for any value of Vi. sine wave with period π, and a peak value of
(b) Vo = 10 V for all values of Vi > 10 V. Vm is
(a) 0.707 Vm (b) 0.500 Vm
(c) Vo = 0 V for all values of Vi < 0 V
(c) 0.637 Vm (d) 0.318 Vm
(d) Vo = 10 V for all values of Vi > 0 V
IES - 2003
IES - 2004
Ans. (c) : Full wave Rectifier sine wave
Ans. (c) : Case (I)

2Vm 2 × Vm
When Vin < 0 Average value = =
π 3.14
= 0.637 Vm
→ Ripple factor full wave Rectifier = 0.482
→ Efficiency of full wave rectifier = 81.2% .
98. Consider the following statements :
The function of bleeder resistance in filter
circuit is to
Case (II) 1. maintain minimum current necessary for
When 0 < Vin < 10 optimum inductor filter operation.
2. work as voltage divider in order to provide
variable output from the supply.
3. provide discharge to capacitors so that
output becomes zero when the circuit has
been de-energized
Which of these statements are correct ?
Analog Electronics 221 YCT
 (a) 1 and 2 (b) 2 and 3 Ans. (c) Full wave rectifier circuit with capacitor filter:
(c) 1 and 3 (d) 1, 2 and 3
Nagaland PSC (Degree) 2018, Paper-II
IES - 2001, 1995
Ans. (d) : Bleeder resistor : Bleeder resistor is
connected in parallel with the output of a high voltage
power supply circuit for purpose of discharging the
electric charge stored in power supply’s filter capacitors
when the equipment is turned off, for safety regions. the shunt capacitor filter used with half-wave rectifier
It provides safety to operator by providing discharge prolongs the time period during which the current
path to the capacitor. passes through the load resistance and the ripple is very
much reduced. This situation is further improved
towards the reduction of ripple level Vr when the shunt
capacitor filter is used with a full wave rectifier circuit.
in a full wave rectifier some use a large value of
capacitor filer-
99. Consider the following rectifier circuits : • Low conduction period for the diode rectifier.
1. Half-wave rectifier without filter • Increased peak current rating of the diode.
2. Full-wave rectifier without filter
3. Full-wave rectifier with series inductance 102. The input voltage of Zener regulator varies
filter from 20 V to 30 V. The load current varies
4. Full-wave rectifier with capacitance filter. from 10 mA to 15 mA. If the Zener voltage is 5
The sequence of these rectifier circuits in V, the value of series resistor will be
decreasing order of their ripple factor is (a) 1 kΩ (b) 1.5 kΩ
(a) 1, 2, 3, 4 (b) 3, 4, 1, 2 (c) 1.66 kΩ (d) 2.5 kΩ
(c) 1, 4, 3, 2 (d) 3, 2, 1, 4 IES - 2000
IES - 2001
Ans. (a) :
Ans. (a) : Ripple factor in HWR is greater than in
FWR. Full wave Rectifier does not clip negative cycle
again series inductance or parallel capacitance are used
as filter.
For full wave Rectifier = 0.48
For half wave Rectifier = 1.21 Given,
100. The use of rectifier filter in a capacitor circuit Vin( max ) = 30V I L( max ) = 15mA
gives satisfactory performance only when the
load Vin( min ) = 20V, IL( min ) = 10mA
(a) current is high (b) current is low
I = I Z( min ) + I L( max )
(c) voltage is high (d) voltage is low
IES - 2001 = 0 + 15
Ans. (b) : The use of rectifier filter in a capacitor circuit = 15mA
gives satisfactory performance only when the load
Vin ( min ) − VZ
current is low. Series Resistance Rs =
The minimum ripple factor capacitor filter is used for I
high load resistance so load current will be low. 20 − 5 15
101. Consider the following statements in relation to = = = 1kΩ
15 15mA
a large value of capacitor filter used in a full-
wave rectifier : 103. In order to rectify sinusoidal signals of mili volt
It gives the : range (< 0.6 V).
1. low conduction period for the diode rectifier (a) Bridge rectifier using diodes can be employed
2. increased peak current rating of the diode (b) Full - wave diode rectifier can be used
3. large peak inverse voltage rating of the (c) A diode is to be inserted in the feedback loop
diode.
of an OP-AMP
Which of these statements are correct ?
(a) 1, 2 and 3 (b) 2 and 3 (d) A diode is to be inserted in the input of an
(c) 1 and 2 (d) 1 and 3 OP-AMP
IES - 2000 IES - 1998
Analog Electronics 222 YCT
Ans. (c) D3 will not conduct because this diode is Reverse bias
only D2 diode conduct

eo = 5V

The input voltage exceeds 0V, there is a small 105. For an input of Vs = 5 sin ωt, (assuming ideal
difference between the inverting input (which is diode), circuit shown in the figure will behave
as a
grounded) and the non inverting input. The Op-Amp
very high gain causes the output to saturate at the
positive cycle for this purpose, diode is used in
feedback of op-amp.
This configuration is also known as super diode.
104. In the circuit shown in the figure, if e1 = 2 V,
e2 = 5V, e3 = 1 V and E = 2V, then which one of
the diodes will be conducting and what will be
(a) clipper, sine wave clipped at – 2 V
the e0 ?
(b) clamper, sine wave clamped at – 2 V
(c) clamper, sine wave clamped at zero volt
(d) clipper, sine wave clipped at 2 V
IES - 1997
Ans. (b) :

(a) D3;1V (b) D1;2V

(c) D2;5V (d) D1;5V
IES - 1998 Positive half cycle-
Ans. (c) :

= − VS + VC − 2V = 0
VC = VS + 2V
= 5V + 2V
= 7V
Negative half cycle-

Let us assume, one of the diode are conducting then

Vo = 2V
Q current flow only when there exist a potential Vo = VS − VC
difference. V0 = 5sin ωt –7
∴ D1 does not conduct Clamper, sine wave clamped at –2V

Analog Electronics 223 YCT

106. If the input ac is 10V (rms), the maximum I = I
Z( max ) I L( min )
voltage that will appear across the diode of a
half-wave rectifier with a capacitor input filter V − VZ 32 − 24
I = in =
will be R R
(a) 10 V (b) 14 V
8
(c) 20 V (d) 28 V I =   ……………………………..(i)
IES - 1997 R
Ans. (b) : Q PZ( max ) = VZ( max ) ⋅ I Z( max )
600mW = VZ(max ) ⋅ I Z(max )

600mW 600 × 10−3

I Z( max ) = =
VZ( max ) 24
I Z(max) = 25mA ……………………(ii)
Case(I) I = I Z(max ) + I L( min )
Negative half cycle
From equation (i) and (ii)
8
= 25mA + 0
R
8 8 × 103
R= = = ⋅32 × 103 Ω
as we know that 25mA 25
PIV of half wave rectifier is Vm = 320Ω
Again
PIV = Vm
I = I Z(min ) + I L(max )
Vm
Vrms = I L(max ) = I − I Z( min )
2
Given, Vrms = 10V = 25 − 10
Vm = 10 2V I L( max ) = 15mA
= 10 ×1.414 108. Consider the following statements :
= 14.14V A clamper circuit
107. A 24 V, 600mW Zener diode is to be used for 1. adds or subtracts a dc voltage to or from a
providing a 24 V stablized supply to a variable waveform.
load. Assume that for proper Zener action, a
2. does not change the shape of the waveform.
minimum of 10 mA must flow. What is the
value of series resistance and maximum value 3. amplifies the waveform.
of load current ? Which of the statements give above are
correct?
Of these statements
(a) 1 & 2 are correct (b) 1 & 3 are correct
(c) 2 & 3 are correct (d) 1, 2 & 3 are correct
Mizoram PSC Jr. Grade-2015, Paper-II
(a) 300 Ω, 10 mA (b) 400 Ω, 15 mA IES - 1996
(c) 400 Ω, 10 mA (d) 320 Ω, 15 mA Ans. (a) : Clamper is a circuit, it is made with the help
IES - 1996 of resistor, a diode, and a capacitor, which is shift the
Ans. (d) : input signal into difference D.C level, that means the
clamper circuit adds the positive or negative dc value in
the input signal, it cannot amplify the wave form.

Given – 109. The piecewise linear V-I characteristic of a

Input voltage = 32 V diode is shown in the given figure. When the
Zener voltage = 24 V supplied voltage is 6V, the current through the
I → total current diode will be

Analog Electronics 224 YCT

 (a) 42 mA (b) 48 mA
(c) 51 mA (d) 54 mA
IES - 1996
Ans. (d) : IES - 1995
Ans. (d) :

When Vin > 5V then

Slope of V.I characteristics,
diode is forward biased
I −I 34mA − 14mA 20mA
M= 2 1 = =
V2 − V1 ( 4 − 2) 2V
= 10mA / volt
given, supply voltage = 6V
I − I 2 = m ( V − V2 )
I = M ( V − V2 ) + I 2
10mA
= ( 6V − 4V ) + 34mA
volt
10mA
= × 2V + 34mA
volt Vo = 5V
I = 54mA
When Vin < 5V then, diode is Reverse biased
110. For the circuit given in figure below, assuming
ideal diode, the output waveform V0 is

Vo = Vin = Vo = 10V
111. In an L-Section filter, a bleeder resistance
connected across the load
(a) provides good regulation for all values of
load.
(b) ensures lower PIV of the diodes.
(c) ensures lower values of Capacitance in the
filters.
(d) reduces ripple content.
IES - 1994
Ans. (a) : (i) L-section filter : Choke filter consists of
an inductor in series with rectifier output circuit and
capacitor connected in parallel with load Resistor.
(ii) The input is fed through the inductor, so it is also
known as the choke input filter.

Analog Electronics 225 YCT

Bleeder Resistor :- A bleeder resistor is a resistor
connected in parallel with the output of a high-voltage
power supply circuit.
Hence a bleeder resistor provides good regulation for all
value of load and improves voltage regulation.
112. Consider the following statements regarding
the circuit given in the figure, where the output
voltage is constant;
1. Vin > the Voltage at which the Zener breaks
down.
2. IL < the difference between I and Iz the
current at which the Zener breaks down. V0 + 0.01R 2
(a) Greater than
3. Rs < the Zener normal resistance. ( Vin − V0 ) R 2
(b) Greater than
( Vin − V0 ) R 2
V0 + 0.01R 2

(c) Less than

( Vin − V0 ) R 2
V0 + 0.01R 2
Of these statements V + 0.01R 2
(d) Less than 0
(a) 1, 2 and 3 are correct (b) 1 and 2 are correct ( Vin − V0 ) R 2
(c) 2 and 3 are correct (d) 1 and 3 are correct IES - 1993
IES - 1994 Ans. (c) :
Ans. (b) :

Given, I z = 10mA
Q Vin > then zener voltage at which the zener break
down, I ≥ I z + I L .............(i)
Vin > V0 Vo
KCL apply At node A. IL =
R2
I = IZ + IL
IL = I − IZ Vin − Vo  V 
OR ≥ 10mA + o 
R1  R 2 
Rs and zener normal resistance have no relation.
113. The ideal characteristic of a stabilizer is V − Vo V
OR in ≥ 10×10 –3 + o
(a) Constant output voltage with low internal R1 R2
resistance.
Vin − Vo V
(b) Constant output current with low internal ≥ 0.01 + o
resistance. R 1 R 2

(c) Constant output voltage with high internal

resistance. R1 ≤
( Vin − Vo ) R 2
(d) Constant internal resistance with variable ( 0.01R 2 + Vo )
output voltage.
115. The wave shape of V0 in figure is
IES - 1994
Ans. (a) : Ideal characteristics of a stabilizer-
• Ideal, Rz = 0
• Voltage stabilizer is always connected in parallel with
load, so ideally its internal resistance must be zero.
• Lower the value of Rz gives better constant voltage.
114. The Zener diode in the circuit shown in figure-I
has the characteristics shown in figure-II. If R2
is the lowest load resistance to be used in the (a)
regulated supply, then to get load regulation,
R1 must be
Analog Electronics 226 YCT
 Ans. (a) : Ebers-Moll Model:- It is an Ideal model for
(b) BJT that can used in forward or Reverse active Mode
operation, as well as in both saturation and cut-off mode
also. Analysis the two diode represent Base emitter and
base collector diode.
(c) ●The Ebers-Moll equation are based on two exponential
diode plus two current-controlled current source.
117. For small signal ac operation, a practical
(d) forward biased diode can be modeled as
(a) A resistance and a capacitance
GATE-1993 (b) An ideal diode and resistance in parallel
(c) A resistance and an ideal diode in series
Ans. (a) :
(d) A resistance
GATE-1998
Ans. (d) : For small signal ac operation, a practical
forward biased diode can be modeled as resistance

Case (I) positive half cycle

Diode DA is Forward bias, so D A is short circuit Diode
D B is Reverse bias so D B is conducting 118. For full wave rectification, a four diode bridge
rectifier is claimed to have the following
VO = 10 − 4.1 advantages over a two diode circuit.
= 5.9 V 1. Less expensive transformer
Vin > 4.1 2. Smaller size transformer and
3. Suitability for higher voltage application
of these
(a) only (1) and (2) are true
(b) only (1) and (3) are true
(c) only (2) and (3) are true
(d) (1), (2), as well as (3) are true
Case (II) Negative half cycle GATE-1998
Diode D B is forward bias so D B is short circuit. Ans. (d) : A four diode bridge rectifier uses the smaller
Diode D A is Reverse bias so D A is conducting state size of transformer, which is less expensive transformer
and these rectifiers are suitable for higher voltage
Vin > 4.1 applications, because of low PIV rating of each diode.
VO = −10 + 4.1 119. A dc power supply has a no-load voltage of 30
= −5.9 V V, and a full-load voltage of 25 V at a full-load
current of 1 A. Its output resistance and load
regulation, respectively, are
(a) 5 Ω and 20% (b) 25 Ω and 20%
(c) 5 Ω and 16.7% (d) 25 Ω and 16.7%
GATE-1999
Ans. (a) : Given, VNL = 30
Then total output voltage from DA and DB is VFL = 25 V
VNL − VFL
Voltage regulation = ×100
VFL
30 − 25 1
= × 100 = ×100 = 20%
25 5
116. The Ebers Moll model is applicable to V − VDCFL
(a) Bipolar junction transistors R D = DCNL
I DC
(b) NMOS transistors
(c) Unipolar junction transistors 30 − 25
=
(d) Junction field-effect 1
GATE-1995 = 5Ω
Analog Electronics 227 YCT
120. The transistor shunt regulator shown in the IC = 99 I Z
figure has a regulated output voltage of 10V, = 99 × 0.01
when the input varies from 20V to 30V. The
= .99A
relevant parameters for the zener diode and
PC = VC ⋅ IC
the transistor are: VZ = 9.5, VBE = 0.5 V, β = 99.
Neglect the current through RB. Then the = 10 × 0 ⋅ 99
maximum power dissipated in the zener diode PC = 9.9 watt
(PZ) and the transistor (PT) are
121. A.C. is converted into D.C. by
(a) Dynamo (b) Motor
(c) Transformer (d) Rectifier
RRB SSE 02.09.2015, Shift-II
Ans. (d) : The electric power available is usually an ac
supply. The supply voltage varies sinusoidal and has a
(a) PZ = 75 mW, PT = 7.9 W frequency. Frequency of 50Hz. It is used for lighting,
(b) PZ = 85 mW, PT = 8.9 W heating and electric motors when a dc supply is
(c) PZ = 95 mW, PT = 9.9 W required.
(d) PZ = 115 mW, PT = 11.9 W The mains ac supply is rectified by using semiconductor
GATE-2001 diodes. This is known as rectification.
Ans. (c) : (i) Half –wave rectifier
(ii) Full wave rectifier
122. The output voltage of the regulated power
z
supply shown in the figure is

Vin( max ) − Vo
I1max =
20
30 − 10
= = 1 Ampere
20
( i.e. when Iz = 0 )
(a) 3 V (b) 6 V
I E = IB + IC ............(1) (c) 9 V (d) 12 V
IB = I Z ( as no current flow ) GATE-2003
Ans. (c) :
IC = βI B
IC IC
β= =
IB I Z
From equation (i)
I E = βI Z + I Z
= I Z ( β + 1)
Zener diode voltage is 3V,
= I Z ( 99 + 1) Non inverting terminal voltage is 3V according to Zener
= 100I Z diode voltage at importing terminal will be 3V because
of virtual ground.
I E = I1 = 100 I z So, current in 20kΩ
I1 = 100 I Z 3 3
I= = mA
I1 20kΩ 20
IZ = RT = 40kΩ + 20 kΩ
100
= 60kΩ
PZ = VZ I Z 3
V0 = × 60kΩ
= 9.5 × .01 20kΩ
PZ = 95m watt V0 = 9V

Analog Electronics 228 YCT

123. In the voltage regulator shown in the figure, Given V = 5.8V
Z
the load current can vary from 100 mA to 500
I Z( min ) = 0.5mA
mA. Assuming that the Zener diode is ideal
(i.e., the Zener knee current is negligibly small 20 − 5.8
and Zener resistance is zero in the breakdown I = 1kΩ
region), the value of R is = 14.2mA
I = I Zmin + I L(max)
14.2 − 0.5mA = I L( max )

(a) 7 Ω (b) 70 Ω I L( max ) = 13.7mA

70 125. For the circuit below, assume that the zener
(c) Ω (d) 14 Ω
3 diode is ideal with a breakdown voltage of 6
GATE-2004 volts. The waveform observed across R is
Ans. (d) :

Given, zener voltage Vz = 5V

Load current I L = (100 to 500 ) mA (a)
Input voltage
Vin = 12V (b)
I = I Z + IL
= I Zmin + I Lmax
(c)
= 0 + 500mA
I = 500mA
V − Vz 12 − 5 (d)
R = in =
I 500mA
= 14Ω GATE-2006
Ans. (b) :
124. The Zener diode in the regulator circuit shown
in the figure has a Zener voltage of 5.8 volts
and a Zener knee current of 0.5 mA. The
maximum load current drawn from this circuit
ensuring proper functioning over the input
voltage range between 20 and 30 volts, is
Given, VR = 12sin ωt
Zener voltage VZ = 6V
Zener diode work as normal diode in forward bias
When Vin < 0, VR = Vin
For positive half cycle diode in reveres bias so it will be
(a) 23.7 mA (b) 14.2 mA
in conduction ⇒ VR = Vin − Vz
(c) 13.7 mA (d) 24.2 mA
GATE-2005 VR = 12 − 6 = 6V
Ans. (c) : For Negative half cycle diode in forward bias so it will
be worked like normal diode
( VR = −Vin )
VR = −12V
z

I = I Z + IL

Analog Electronics 229 YCT

126. The correct full wave rectifier circuit is Ans. (c) :

(a)

(b)

I z knee = 0
Zener resistance rz = 10Ω
Vz = 7 Volts
(c)
Vin − Vz Vin − 7
I= =
R s + rz 210
Vo = Vz + I ( rz )
Vin − 7
Vo = × 10 +7
210
(d) V −7
Vo = in +7………(i)
21
When Vin = 10V
GATE-2007
10 − 7 3
Ans. (c) : In positive half cycle- Vo min = + 7 = + 7 = 7.14 Volts
D2 , D4 are ON 21 21
D1, D3 are OFF When Vin = 16V
And Vout = Vin 16 − 7 9
Vo max = + 7 = + 7 = 7.42 Volts
In negative half cycle- 21 21
D2 , D4 – OFF Range of Vo = 7.14 to 7.42 Volts
D1, D3 – ON 128. In the following limiter circuit, an input voltage
Vout = –Vin Vi = 10 sin 100 πt is applied. Assume that the
diode drop is 0.7 V when it is forward biased.
The zener breakdown voltage is 6.8 V

127. For the Zener diode shown in the figure, the

Zener voltage at knees is 7V, the knee current The maximum and minimum values of the
is negligible and the Zener dynamic resistance output voltage respectively are
is 10Ω. If the input voltage (Vi) range is from (a) 6.1 V, –0.7 V (b) 0.7 V, –7.5 V
10 to 16V, the output voltage (V0) ranges from (c) 7.5 V, –0.7 V (d) 7.5 V, –7.5 V
GATE-2008
Ans. (c) :

(a) 7.00 to 7.29 V (b) 7.14 to 7.29 V

(c) 7.14 to 7.43 V (d) 7.29 to 7.43 V
GATE-2019, 2007
Analog Electronics 230 YCT
Given, Vi = 10sin100πt 130. The diodes and capacitors in the circuit shown
are ideal. The voltage v(t) across the diode D1 is
Zener breakdown voltage = 6.8V
(1) For positive half cycle Vi
Zener diode is break down state and D1 is forward
Biased and D2 is Reverse bias
Vo = 0.7 + 6.8
= 7.5V
(2) Negative half cycle of Vi,
D2 is forward, D1 is reverse biased so we got the total (a) cos(ωt) – 1 (b) sin (ωt)
output voltage (c) 1–cos (ωt) (d) 1–sin (ωt)
Vo = −0.7 volt GATE-2012
Ans. (a) :
129. In the circuit below, the diode is ideal. The
voltage V is given by

When supply is +Ve half cycle then capacitor C1 is

charged in maximum Vm voltage =1V and Diode D2 is
open circuit. When – Ve half cycle then diode D1 is
(a) min (Vi' 1) open circuit and replace the output voltage Vt.
(b) max (Vi' 1)
(c) min (–Vi' 1)
(d) max (–Vi' 1)
GATE-2009
Ans. (d) :
(i) Let Vi = +Ve − cos ωt + 1 + Vt = 0
Diode reverse bias, then
Vt = cos ( ωt ) − 1
Q V = 1×1 = 1Volt
131. A voltage 1000 sin ωt volts is applied across YZ.
Assuming ideal diodes, the voltage measured
across WX in volts, is

When Vi = Negative
(ii) Diode will be forward bias, diode short circuit
Using KVL,
–Vi –V– Vd = 0
–Vi = V (Vd = 0)
(a) sin ωt
(b) (sin ωt + |sin ωt|)/2
(c) (sin ωt – |sin ωt|)/2
(d) 0 for all t
GATE-2013
Ans. (d) :

Analog Electronics 231 YCT

Case-I ABCDEF apply kvl
During the positive half cycle, then all diode is OFF −10V + 1000I + 20I + 0.3V = 0
1020 I= 10 − 0.3
Hence
9.7
I= = 0.0095
1020
= 9.5mA
ABEFA
Apply KVL
−10V + 1000 × 9.5mA + VD1 = 0
−10V + 9.5V + VD1 = 0
VD1 = 10 − 9.5
VD1 = 0.54V
V1 = V2 We got VD1 value is 0.5V, but we need more voltage
than 0.7V to turn on the D1 so that’s why D1 is off and
V = 0 Volt D2 is ON.
Case-II 133. The diode in the circuit shown has Von = 0.7 V
Negative half cycle; diode is short circuit but is ideal otherwise. If Vi = 5 sin( ωt) volts, the
minimum and maximum values of V0 (in volts)
are, respectively,

V = 0 Volt

132. In the figure, assume that the forward voltage

drops of the PN diode D1 and Schottky diode
D2 are 0.7 V and 0.3 V, respectively. If ON
denotes conducting state of the diode and OFF
denotes non-conducting state of the diode, then (a) –5 and 2.7 (b) 2.7 and 5
in the circuit, (c) –5 and 3.85 (d) 1.3 and 5
GATE-2014, Set-II
Ans. (c) :

(a) Both D1 and D2 are ON

(b) D1 is ON and D2 is OFF
(c) Both D1 and D2 are OFF
(d) D1 is OFF and D2 is ON
GATE-2014, Set-I
If Vin = −5V ⇒ diode is OFF
Ans. (d) :
Vin = −5V = Vo
When Vin = 5V then, diode is ON

Vo =
( Vi − 0.7 − 2 ) ×1K + 0.7 + 2
Assume D1 = OFF, D 2 = ON
(1 + 1) ×103
=
( 5 − 2.7 ) ×1×103 + 2.7
2 ×103
= 1.15 + 2.7 = 3.85 V
134. Two silicon diodes, with a forward voltage drop
of 0.7 V, are used in the circuit shown in the
figure. The range of input voltage Vi for which
the output voltage V0 = Vi' is

Analog Electronics 232 YCT

 Ans. (c) :

(a) –0.3 V < Vi < 1.3 V (b) –0.3 V < Vi < 2V

(c) –1.0 V < Vi < 2.0 V (d) –1.7 V < Vi < 2.7 V
GATE-2014, Set-IV
Ans. (d) :

Case (I)
Positive half cycle, both diode are forward biased and
Negative half cycle both diode are Reverse biase.

(1)
Case (I)
Vi <-1.7V, D1 is ON, D 2 is OFF

(2)

V0 = 0V
Case (II)
−1.7 < Vi < 2.7
Diode D1 and D 2 both are OFF
136. If the circuit shown has to function as a
clamping circuit, then which one of the
following conditions should be satisfied for the
sinusoidal signal of period T?

Vi = Vo
135. For the circuit with ideal diodes shown in the
figure, the shape of the output (Vout) for the (a) RC << T (b) RC = 0.35 T
given sine wave input (Vin) will be
(c) RC ≈ T (d) RC >> T
GATE-2015, Set-II
Ans. (d) :

(a) (b)
Where R is resistance, C is capacitance, T is time period
of the input signal.
(c) (d) The voltage at the capacitor during discharge is given as
t
−

GATE-2015, Set-I VC ( t ) = Vo e RCdis

Analog Electronics 233 YCT

Suppose at t = T 2 138. The circuit shown in the figure is used to
T 2 provide regulated voltage (5V) across the 1 kΩ
−
VC ( t ) = Vo = Vo e RC
............(1) resistor. Assume that the zener diode has a
constant reverse breakdown voltage for a
and at t = T at the voltage will be
current range, starting from a minimum
−T
VC ( t ) = 0.99Vo =Vo e ⋅ RC ..........(2) required Zener current, IZmin = 2 mA to its
maximum allowable current. The input voltage
Q From equation (2), we get V1 may vary by 5% from its nominal value of 6
−T
V. The resistance of the diode in the
0.99 = e RC
breakdown region is negligible.
T
−0.01 = −
RC
RC = 100T
This implies that
RC >> T
The value of R and the minimum required
137. The I-V characteristics of the zener diodes D1 power dissipation rating of the diode,
and D2 are shown in figure I. These diodes are respectively, are
used in the circuit given in figure II. If the (a) 186 Ω and 10 mW (b) 100 Ω and 40 mW
supply voltage is varied from 0 to 100 V, then
breakdown occurs in (c) 100 Ω and 10 mW (d) 186 W and 40 mW
GATE-2018
Ans. (b) :

(a) D1 only (b) D2 only Given

(c) Both D1 and D2 (d) None of D1 and D2 Zener voltage VZ = 5V
GATE-2016, Set-III
load resistance R L = 1kΩ
Ans. (a) :
R =?
Vi = 6V ± 5%
= 6V ± .3V
= ( 5.7 to 6.3) V
5
IL = = 5mA
1kΩ
Is( min ) = IL + I Z( min )
Breakdown voltage of D1 = 80V
Breakdown voltage of D2 = 70V = 5mA + 2mA
When Vin exceed 80V then D1 is in breakdown region = 7mA
the circuit become VI( min ) − VZ
Is( min ) =
R
VI( min ) − VZ ( 5.7 − 5 ) V 0.7V
R= = =
Is( min ) 7mA 7mA
700
So, R = = 100Ω
7
∴ Vin max = 100V, then VD2 = (100 − 80 ) V
When R = 100Ω
VD2 = 20V 6.3 − 5
Is( max ) = A = 13mA
= 20 < Vbreakdown 100
∴ So only D1 enters into Breakdown region. Is( max ) = I z( max ) + I L

Analog Electronics 234 YCT

So I z( max ) = Is( max ) − I L 141. Calculate the maximum current that can be
passed through a 1N755 Zener Diode at a
= 13mA − 5mA
temperature of 50°C. For 1N755 Zener Diode,
= 8mA VZ = 7.5V and PD = 400 mW at 50°C.
Pz( min ) = Vz I z( max ) (a) 53.33mA (b) 63.33mA
= ( 5 × 8 ) m watt (c) 73.33mA (d) 93.33mA
= 40mW APPSC POLY. LECT. 14.03.2020
139. As with other two terminal devices, diodes can Ans. (a) : VZ = 7.5 V
be placed in series (or in parallel). Determine Power of Zener = 400 mW
which one of the following configurations can Maximum power (P) = V Imax
conduct current from A → C ? 400 mW
I max =
7.5V
Imax = 53.33 mA
142. The equivalent DC output voltage of a full-
wave rectifier is ______ the equivalent DC
output voltage of a half-wave rectifier.
(a) equal to (b) not related to
(c) half of (d) double
RPSC VP/Suptd. ITI 05.11.2019 APPSC POLY. LECT. 14.03.2020
Ans. (a) : As with other two terminal devices, diode can Ans. (d) : DC output voltage-
be placed in series
V
For half wave rectifier VDC = m
π
In this type of configurations diode can conduct current 2Vm
from A → C. For full wave rectifier VDC =
π
140. The circuit shown in figure is a Hence dc output voltage of full wave rectifier is double
(a) positive peak clipper (b) positive clamper of half wave rectifier dc output voltage.
(c) differentiator (d) negative clamper
143. When a capacitor is connected across the
output terminals of a full-wave rectifier, the
output voltage :
(a) nearly becomes a DC voltage.
(b) becomes sinusoidal.
(c) exhibits sharp spikes.
TSPSC Manager (Engg.) - 2015 (d) is shifted up and down.
Ans. (b) : APPSC POLY. LECT. 14.03.2020
Ans. (a) : Rectifier convert AC voltage into DC
voltage. When a capacitor is connected across the
output of a full wave rectifier, the output voltage nearly
becomes a DC voltage.
144. Diodes are used to clip voltages in circuits
because they act as :
Let Vi = ± Vm (a) current sources under certain bias conditions.
(i) If Vi is − Vm : (b) voltage sources under certain bias conditions.
Diode is in F.B. (c) inductors that can remove spikes.
C charges upto −Vm (d) dependent current sources.
(ii) If Vi is + Vm APPSC POLY. LECT. 14.03.2020
Diode is in R.B Ans. (b) : Diodes are used to clip voltages in circuits
Capacitor can discharge through R because they act as : Voltage sources under Certain bias
conditions.
Vi V0 max 145. A half-wave rectifier made with a single diode
and a load resistor converts an AC voltage into :
+ Vm 0V
(a) a constant DC voltage.
−Vm 2Vm (b) a sinusoidal voltage that has a DC offset.
Analog Electronics 235 YCT
 (c) a waveform that has only the positive or
negative half-cycle of the input sinusoidal.
(d) Another AC voltage that is phase shifted by
180° (c) (d)
APPSC POLY. LECT. 14.03.2020
Ans. (c) : A half wave rectifier made with a single
diode and a load resistor converts an AC voltage into a APPSC Poly. Lect. 15.03.2020
waveform that has only the positive or negative half Ans. (b) : Diode Transfer the voltage below the
cycle of the input sinusoidal. (reference level) (–V)
146. Circuits that are used to eliminate portions of a
signal that are above or below a specified level
are called:
(a) Clampers (b) Clippers
(c) Voltage doublers (d) Detectors
UPSC [Link].10.03. 2019
Ans. (b) : The circuit that are used to eliminate the
portion of a signal that are above or below a specific
level are called limiter or clipper circuit.
147.
149. Without a dc source, a clipper acts like a
(a) Clamper (b) Chopper
(c) Rectifier (d) Demodulator
LMRC AM (S&T)-13.05.2018
Nagaland PSC (Degree) 2018, Paper-II
For the series diode configuration of above Ans. (c) : In a clipper circuit, If the dc source is set to
figure, employing the diode characteristics zero voltage, then the circuit acts as a rectifier.
shown below :
ID (mA)
20
18
16
14
12 • Basic clipping devices is the half-wave rectifier
10
8
6
4
2
0.5 0.8 VD (V)
The value of VR is :
(a) ≈ 9.2V (b) ≈ 0.7V
(c) ≈ 2.5V (d) ≈ 12V
APPSC Poly. Lect. 15.03.2020 150. The tunneling process in a Tunnel diode is due
to
Ans. (a) : From graph :- VD = 0.8V
(a) Physical behavior (By possession of large
VR = E − VD = 10 − 0.8 = 9.2V energy)
(b) Quantum-mechanical behaviour
(c) The presence of smaller amounts of impurity
148. atoms
(d) Subjecting to very large voltage (in forward
and reverse biases)
The output of the given circuit, assuming ideal TNPSC AE- 2019
diode, is :
Ans. (b) : Tunneling is an effect that is caused by
quantum mechanical effect when electrons pass through
(a) (b) a potential barrier. The tunneling only occurs under
certain conditions. It occurs within tunnel diodes
because of the very high doping levels employed.

Analog Electronics 236 YCT

151. The capacitance of a Varactor diode can be Vm I
changed by I= So, IDC = m
(a) Increasing its doping level R F + R L π
(b) Changing its forward bias Vm
(c) Changing its barrier potential I DC =
π(R F + R L )
(d) Changing the reverse voltage
TNPSC AE- 2019 155. The diode in circuit has cut in voltage V cut in
Ans. (d) : The capacitance of varactor diode can be is 0V. Choose the option for the waveform of
changed by changing the reverse voltage. Varactor output voltage Vo
diode is known as varicap or voltcap or voltage variable
capacitance. It always works in reverse bias condition.
152. The current of a certain Si-diode, when
measured with a large reverse bias is found to
be 10nA. What would be the current be if a
forward bias of 2V is applied ? Assume that
T=3000K, η = 2.
(a) 6.2×108A (b) 6.2×10-8A (a)
(c) 0.62×10 A8
(d) 0.62×10-8A
TNPSC AE- 2019
Ans. (a) :
 VD 
I = I0  e ηVT − 1 (b)
 
 
 VD  T
I = I0  e ηVT  Q VT =
  11600
  (c)
 2
 300
I = 10 × 10−9  e 2× 0.02586
 VT =
  11600
(d)
I = 6.2 ×108 A VT = 0.02586
153. The biggest disadvantage of the IMPATT diode
is its
(a) high noise
(b) lower efficiency (e)
(c) inability to provide pulsed operation
(d) low power-handling capability
TNPSC AE- 2019 CGPSC SO 14.02.2016
Ans. (a) : It has high noise figure due to avalanche
Ans. (e) :
process and higher operation current. The shot noise is
generated in the device due to high operation current. +ve Half cycle
Typically noise figure of IMPATT diode is about 30dB.
154. A half-wave rectifier uses a diode with a
forward resistance Rf. The voltage is
Vm sinωt and the load resistance is RL. The d.c.
current is given by
Vm V –20 + 2.2I + 5 = 0
(a) (b) m
2R L RL 2.2I = 15
2Vm Vm 15
(c) (d) I=
π π(R f + R L ) 2.2
BPSC Polytechnic Lecturer-2014 Vo = IR + 5
I 15
Ans. (d) : For a half wave rectifier the IDC = Iavg = m Vo = × 2.2 + 5
π 2.2
V sin ωt Vo = 20V
I= m = I m sin ωt
( F L)
R + R –Ve Half cycle

Analog Electronics 237 YCT

Diode is reverse bias For negative half cycle
Vin Diode Vout
0 − 16V ON 4V

So Vo = 5V

157.
156. Which of the five waveforms of Vout predicts
the correct output of circuit for Vin as shown
below:
Vin (Volts)

For the above given waveform as input Vi to

the given circuit of a clipper. Maximum and
minimum values of output V0 will be
(a) +16V and +4V (b) +16 and -4V
(c) +4V and -16V (d) +16V and -12V
Vout (Volts) UPPSC ITI Principal/Asstt. Director-09.01.2022
Vout (Volts)
Ans. (a) :

Vi = +16 V0 = 16 diode off

Vout (Volts) Vout (Volts)
V0 max = 16 V
Vi = –16 then diode on V0 = +4V
V0min = 4V
158. The zener diode breakdown voltage is 2.5V.
Find voltage across 2kΩ

Vout (Volts)

(e)
(a) 2.14V (b) 2.2V
(c) 2.5V (d) 3V
CGPSC SO 14.02.2016 BARC Scientific Officer-2016
Ans. (e) : For positive half cycle Ans. (a) : If we calculate voltage across 3 kΩ .
10
Vin Diode Vout V3kΩ = 3k × = 3V
10k
0 − 4V ON 4V
So it is greater than VZ in this situation Zener diode
4V − 16V OFF 16V will be behave like battery.

Analog Electronics 238 YCT

 V0 = −5V

At the graph screen we will get this type of wave shape.

160. Which of the Current (i) – Voltage (v) graphs
10 − 2.5 15 represents a p-n junction diode characteristics?
I= = mA
7 14
15 (a) (b)
V2kΩ = 2k × mA
14
15
V2kΩ = V
7
V2kΩ = 2.14V (c) (d)
159. Find V0 if Vi = 5sin 200πt

RRB SSE 21.12.2014, (Green)

Ans. (c) : PN junction diode V-I characteristics

(a) 161. Assume that D1 and D2 in figure are ideal

diodes. The value of current-l is

(b)

(a) 0.58 mA (b) 0.5 mA

(c) 0. mA (d) 0.633 mA
(c) RRB SSE 01.09.2015 Shit-I
Ans. (c) : D1 and D2 are ideal diodes so in this
condition D1 in forward bias and behaviour short
circuited. On the other hand D2 will in reverse bias and
(d) None behave as a open circuited. Circuit so in this situation
TNPSC AE- 2019 current flow from D2 will 0mA. We can redraw circuit
BARC Scientific Officer-2016 like this.
Ans. (a) :

Q When Vin > 2 than diode forward bias and output

voltage V0 = +2V
–Ve half cycle diode is open circuit and output voltage
V0= –Vin

Analog Electronics 239 YCT

162. A __________ is an electronic circuit that 2I1+I2 = 2……….. (ii)
changes the DC level of a signal to the desired By solving (ii) & (iii)
level without changing the shape of the applied
signal.
(a) Rectifier (b) Clamper
(c) Slicer (d) Limiter
RRB JE- 31.08.2019, 10 AM-12 PM −4
I2 =
Ans. (b) : A clamper is an electronic circuit that uses a 3
signal without changing the shape of the signal applied put the value I in equation (ii)
2
to the DC level changes to desired level. There are two
type of clamper- 2I 1 + ( −4 / 3 ) = 2
(i) Positive clamper 4 10
(ii) Negative clamper 2I1 = 2 + =
3 3
10 5
I1 = =
6 3
5 4 1
I= − =
3 3 3
1
V0 = −2 × = −0.671
3
165. The zener diode shown in the circuit has a
reverse breakdown voltage of 10 volts. The
power dissipation in Rs would be
163. Gun diode is made of-
(a) Gallium Arsenide (b) Germanium
(c) Silicon (d) Selenium
RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (a) : Gun diode are fabricated from a single piece
of n-type semiconductor, the most common material are
gallium Arsenide, (GaAs) and Indium Phosphide, (InP).
However other materials including Ge, CdTe, InAs, In
Sb and others have been used.
164. For the circuit shown in the figure below, the
voltage V0 is (here D is an ideal diode) (a) 4W (b) 2W
(c) 3.5W (d) 1W
RRB SSE 01.09.2015, Shift-II
Ans. (a) : Given that,
Zener voltage =10 volts
(a) –1V (b) 1V I L = 50mA
(c) 2V (d) None of the above R S = 100Ω
BPSC Polytechnic Lecturer-2014
VS = 30V
Ans. (d) :
VS − VZ
Source current IS =
RS
30 − 10
=
100
20
Let diode in ON- IS =
100
I1+I2 =I Power dissipation in Rs
4 = 2I1 + 2I 2+2I2+2I = 0
P = IS 2 × R S
I 2 + I = −1
20 20
I1 + I = 2 …………….. (i) I2+I1+I2 = –1 = × ×100
100 100
I1 + I1 + I 2 = 2 I1+2I2 = –1 ………..(iii) P = 4W

Analog Electronics 240 YCT

166. Assuming that diode in the given circuit is (c) The instantaneous current depends only on
ideal, the voltage V0 is the diode
(d) The energy stored in the capacitor can never
decreases with time
BSNL (JTO)-2001
Ans. (d) : A peak detector comprises a capacitor and an
ideal diode and an ac source in series then the energy
stored in the capacitor can never decreases with time
(a) 2V (b) 3V because the capacitor gets charged to the most positive
(c) 3.5 V (d) 1 V value of the input.
RRB SSE 02.09.2015, Shift-I 169. A diode D1, under certain biasing conditions,
Ans. (a) : Positive half circuit diode is reverse bias then has a forward voltage drop VDi = 0.7 V and IDi
output voltage. = 5.6 mA. Under the same external conditions,
another diode D2 whose doping levels NA and
ND are both twice that of D1 has the same
forward voltage VD2 = .7 V. Assuming the same
ideality factor for both the diodes ID2 is :
(a) 1.4 mA (b) 2.8 mA
(c) 5.6 mA (d) 11.2 mA
2 DRDO-2009
V0 = × 4 = 2.64V Ans. (b) : We know that,
2 +1
When diode is forward bias then if is behaves as a short Reverse saturation current-
circuit.  Dp Dn  2
I0 = Aq  +  n i
L N
 p D Ln N A 
Diode current
 V 
I D = I0  e ηVT − 1
 
The voltage forward biase-  
Output voltage- Q Ideality factor is same for both diode.
1 I
V0 = × 4 = 2V So, I D2 = D1 because the doping NA and ND in diode
1+1 2
D2 are twice as that in diode D1.
167. What is the voltage across the 1Ω register?
I 5.6
So, I D2 = D1 = = 2.8mA
2 2
170. The correct match between the following two
columns is :
(A) Tunnel diode 1. Microwave ampli-
fication
(B) Zener diode 2. Voltage regulation
(a) 4.7 V (b) 4.3 V (C) PIN diode 3. Photo detection
(c) 4 V (d) 5 V (D) Schottky diode 4. High speed switch-
RRB SSE 02.09.2015, Shift-II ing
Ans. (a) : Given- A B C D
V = 5, R = 1Ω, Ge = 0.3 (a) 1 4 2 1
(b) 1 3 2 4
5 − 0.3
I= = 4.7 (c) 4 2 1 3
1 (d) 1 2 3 4
I= 4.7 Amp DRDO-2009
V = IR = 4.7 ×1 Ans. (d) :
V = 4.7 Volt (A) Tunnel diode → Microwave amplification
168. A peak detector comprises a capacitor and an (B) Zener diode → Voltage regulation
ideal diode and an ac source in series. (C) PIN diode → Photo detection
The following is true of the circuit. (D) Schottky diode → High speed switching
(a) The instantaneous current depends only on 171. The I-V characteristics of devices can be
the instantaneous source voltage divided into quadrants as shown in figure
(b) The diode voltage is always zero below.
Analog Electronics 241 YCT
 0.4 0.8
(a) mA (b) mA
π π
0.4 0.8
(c) mA (d) mA
2 2
BSNL(JTO)-2009
Ans. (a) :
Photodiodes and solar cells are normally
operated in quadrants :
(a) Q3 and Q4, respectively
(b) Q1 and Q1, respectively
(c) Q1 and Q3, respectively
(d) Q2 and Q3, respectively
DRDO-2009
Ans. (a) : Photodiodes and solar cells are normally
operated in quadrants Q3 and Q4, respectively.
172. The cut-in voltage Vγ and thermal voltage VT
for the diode D in figure shown below are 0.498
V and 2 mV, respectively. Im
Iavg =
π
0.4
= mA
π
174. Assume D1 and D2 to be ideal diodes

If the value of resistor R is 20 Ω, the current

flowing through the diode is :
(a) 275 mA (b) 250 mA
(c) 200 mA (d) less than 200 mA
DRDO-2009
Ans. (b) :

Which one of the following statements is true?

Given Vr = 0.498 (a) Both D1 and D2 are ON
R = 20Ω (b) Both D1 and D2 are OFF
Here VT has no use then, (c) D1 is ON and D2 is OFF
(d) D2 is ON and D1 is OFF
5.5 − Vr
I= DRDO-2008
R
Ans. (d) : As D2 anode has more potential, it will ON
5.5 − 0.498
I= first and D1 the become OFF.
20
I = 250.1mA 175. If cut-in voltage and forward resistance of each
diode (in the adjoining figure are 0.7 V and
I  250 mA
1ohm respectively, the current through the 48
173. In the circuit shown in figure, assume the ohm resistor is
diodes are ideal and the ammeter is an average
indicating meter with zero internal resistance.
The ammeter reading is

(a) 132 mA (b) 160 mA

(c) 0 mA (d) (1/6) A
BSNL (JTO)-2006
Ans. (a) : In this circuit only two diodes ON rest two
diodes OFF.

Analog Electronics 242 YCT

 –Vi + Vc +V0 = 0
– 10 + (–25)+V0 = 0
V0 = 35V

Hence, V0 = +35V, + 5V
So, current through 48Ω resistance
8 − 0.7 − 0.7 177. What is the value of current I through the ideal
I= diode in the circuit?
1 + 48 + 1
8 − 1.4
I=
50
6.6
I= = 0.132
50
I = 132 mA
176. Find VO for the given circuit. (Assume ideal (a) 100 mA (b) 150 mA
diode) (c) 200 mA (d) 250 mA
IES-2016
Ans. (c) : Note → (i) Higher positive potential and
negative potential will decided the behaviour of diode.
In given circuit ideal diode will be forward bias/short
circuit/ON state.
Now circuit becomes-

(a) +35 V, 0 V (b) +35 V, +5 V

(c) 0 V, –5 V (d) –35 V, –5 V
UPRVUNL AE -19.07.2021, Shift-II
Ans. (b) : Condition -I
10
If Vi = –20V, then I=
50
Diode is forward biased and circuit is short circuited.
= 0.2 A
Apply KVL in the circuit = 200 mA.
–Vi + VC +V = 0
178. What is the output voltage V0 for the circuit
– (–20) +VC + 5 = 0 shown below assuming an ideal diode?
VC = –25V
then –Vi + VC +V0 = 0
–(–20) + (–25) +V0 =0
V0 = 25 –20
V0 = 5V

18 18
(a) − V (b) V
5 5
13 13
Condition - II (c) − V (d) V
5 5
If Vi = 10V then diode is reverse biased and
circuit is open circuited. IES-2016
Ans. (a) : Note → (i) Higher positive potential and
negative potential will decide the behaviour of diode.
In the given circuit diode behaviour will decide 5V
potential (due to Negative sign)
Then diode will be forward bias/ON state/ short circuit.
Apply KVL in the circuit, Now circuit becomes–

Analog Electronics 243 YCT

Apply Nodal analysis. (a) VR = –5 (b) VR=+5
V0 + 5 − 1 V0 + 3 (c) 0 ≤ VR < 5 (d) –5 <VR< 0
+ =0
2kΩ 3kΩ GATE-2006
V0 + 4 −V0 − 3 Ans. (a) : at t < 0
=
2kΩ 3kΩ
3V0 +12 = –2V0 – 6
5V0 = –18
at 0 < t < ts
−18
V0 = V
5
179.

When switch is instantaneously position 1 to 2 then

diode is instantaneously switched from a conduction
state it needs some time to return a non-conduction state
at this time reverse current starts flow through the
diode. so behaviour of diode is short circuit for a small
time is reverse direction.
apply KVL at (0 < t < ts)
The light Emitting diode (LED), shown in the
above figure has a voltage drop of 2 V. The –VR – 5 = 0
current flowing through LED is VR = −5V
(a) 11.8 mA (b) 0.0147 mA
181. The i-v characteristics of the diode in the
(c) 2.941 mA (d) 0.0176 mA circuit given below are
IES-2013  v - 0.7 
 A V ≥ 0.7V 
Ans. (a) : i =  500 
 0 A V < 0.7V 

The current in the circuit is

Apply KVL- (a) 10 mA (b) 9.3 mA
−10 + 680I + 2 = 0 (c) 6.67 mA (d) 6.2 mA
680I – 8 = 0 OPSC Poly. Lect. (Instrumentation)-2018, Paper I
8 GATE-2012
I=
680 Ans. (d) : Apply kirchhoff's voltage law-
= 0.01176 –10+1000I +V = 0
V = 10 – 1000I .......(i)
I = 11.74 mA  11.8mA
there is 10V is greater then 0.7V
180. In the circuit shown below, the switch was
then diode current will be-
connected to position 1 at t < 0 and at t = 0, it is
changed to position 2. Assume that the diode V − 0.7
I= .....(ii)
has zero voltage drop and a storage time ts. For 500
0 < t ≤ t s .VR s given by (all in Volts) put value equation (ii) in equation (i)

Analog Electronics 244 YCT

 ( V − 0.7 ) 184. In half wave rectifier, if Vi to the diode is 20
V = 10 − 1000 × sin ( ωt), Vdc is
500
(a) 6.37 V (b) 10 V
V = 10 –2 (V– 0.7)
(c) 14.2 V (d) 20 V
V= 10 – 2V + 1.4
Mizoram PSC AE/SDO 2012-Paper-I
3V = 11.4
Ans. (a) : For half wave rectifier-
11.4 V 20
V= V = 3.8V Vdc = Vo(avg ) = m =
3 π 3.14
3.8 − 0.7 = 6.37 Volt
I=
500 185. Which rectifier requires four diodes?
3.1 (a) full-wave bridge circuit
= (b) half-wave voltage doubler
500
(c) voltage quadrupler
I = 6.2mA (d) full-wave voltage doubler
182. In the following limiter circuit, an input voltage Mizoram PSC IOLM -2018, Paper II
V1 = 10 sin 100 πt applied. Assume that the RRB SSE 01.09.2015, Shift-II
diode drop is 0.7 V when it is forward biased. Ans. (a) : Full wave bridge rectifier requires four diode
The Zener breakdown voltage is 6.8 V. as shown in fig.

The maximum and minimum values of the output

voltage respectively are
(a) 6.1 V1 – 0.7 V (b) 7.5 V1 – 0.7 V
(c) 7.5 V1 – 0.7 V (d) 7.5 V1 – 7.5 V
NIELIT Scientists- 2017 186. An AC supply of 230 V is applied to a half-
Ans. (c) : during +ve part of Vi wave rectifier circuit through a transformer
D1 will be forward biased zener will be reverse biased. having primary to secondary turn's ratio 12:1.
Net voltage = 6.8 + 0.7 = 7.5 V The peak inverse voltage is
during –Ve Half cycle. (a) 8.62 V (b) 12 V
D1 will reverse D2 will be forward (c) 19.17 V (d) 27.11 V
biased thus net voltage = 0.7 V RPSC LECTURER-10.01.2016
183. Which is the correct waveform across capacitor Ans. (d) :
in the following circuit?

N 2 V2
(a) =
N1 V1
(b) 1 V
= 2
12 230
(c) V2 = 19.1667
∴ Vm = 19.1667 × 2
(d)
In half wave rectifier PIV = Vm= 27.11V
ISRO Scientist Engg.-2013 187. If the PIV rating of a diode is exceeded,………
Ans. (d) : This diagram show the full wave rectifier (a) the diode conducts poorly
with capacitor filter. For positive half cycle capacitor (b) the diode is destroyed
charged to the peak value and negative half cycle it (c) the diode behaves like a zener diode
discharged but not zero and charged again. (d) none of the above
From the given option correct option is (d) Nagaland PSC CTSE (Diploma)-2017, Paper-I

Analog Electronics 245 YCT

Ans. (b) : Peak inverse voltage rating of a diode may be 192. Transformer utilization factor of half wave
defined as the maximum value of the reverse voltage rectifier is
that a P-N-junction can withstand without damaging. (a) 0.287 (b) 0.693
When the voltage applied to a diode is more than PIV, it (c) 0.812 (d) 0.48
is likely to result in breakdown at the junction and the TNPSC AE- 2019
diode gets destroyed. Ans. (a)
188. The r.m.s. value of half wave rectified current Type of rectifier Half Centre Bridge
is 50A. Its r.m.s. value for full wave wave tapped full
rectification would be wave
(a) 100A (b) (50/π)A Ripple factor 1.21 0.482 0.482
(c) (100/π)A (d) 70.7A Transformer 0.287 0.693 0.812
utilization factor
Mizoram PSC Jr. Grade-2015, Paper-I
Ripple f 2f 2f
I frequency
Ans. (d) : For half wave rectifier I rms = m
2 193. The disadvantage of half wave rectifier circuit
Irms = 50 A is that
Im = 100 Amp (a) Diode must have high PIV rating
I m 100 (b) Diode must have high power rating
For full wave rectifier I rms = = = 70.7 A (c) Output voltage is difficult to filter
2 2
(d) Diode must have high current rating
189. Ripple factor of an ideal rectifier is
Nagaland PSC- 2018, Diploma Paper-II
(a) Zero (b) Unity
Ans. (c) : An half wave rectifier has more ripple in
(c) Infinity (d) None of these output. Hence it is difficult to filter these ripple in
Mizoram PSC Jr. Grade-2015, Paper-II output.
Ans. (a) : In ideal rectifier has constant dc voltage, 194. Precision diode can be used as
hence there is no ripple in output voltage. So ripple (a) Half wave rectifier (b) Full wave rectifier
factor will be zero. (c) Clipper and clamper (d) all of the above
190. If one of the diode in a full wave bridge Nagaland PSC (Degree) 2018, Paper-II
rectifier opens, the output is Nagaland PSC CTSE (Degree)-2017, Paper-II
(a) 0 V Ans. (d) : Half wave rectifier is a diode circuit which is
(b) One-fourth the amplitude of the input voltage used to transform alternating voltage (ac supply) to
(c) A half wave rectifier voltage direct voltage (dc supply). Half wave rectifier circuit
(d) 120 V allows the one half cycle of the ac supply wave form to
pass and blocks the other half cycle.
Mizoram PSC Jr. Grade -2018, Paper-I
Full wave rectifier is defined as a type of rectifier that
Ans. (c) : If one of the diodes is a full wave bridge converts both halves of each cycle of an alternating
rectifier opens, the output is a half wave rectified wave (ac signal) into a pulsating dc signal. Full wave
voltage. rectifiers are used to convert ac voltage to dc voltage
requiring multiple diodes to construct. Clipper and
clamper circuits are electronic circuits used for the
modification of ac signals. The clipper circuit can clip a
portion of the ac waveform while the clamper shifts the
191. The dc voltage of a Half-wave rectifier is dc level of the ac signal.
I R I R 195. The main advantage of a bridge rectifier over
(a) Vdc = dc L (b) Vdc = m L full wave rectifier with centre tapped
π π transformer is
I R I R (a) less ripple
(c) Vdc = m L (d) Vdc = dc L (b) No transformer is needed
2π 2π
(c) peak inverse voltage of each diode is half
TNPSC AE- 2019 (d) PIV of each diode is double
Ans. (b) : Half –wave rectifier RRB SSE 21.12.2014, (Yellow)
VLm I m R L Ans. (c) : The main advantage of a bridge rectifier over
VL(dc) = = = 0.318VLm
π π full wave rectifier with centre tapped transformer is the
PIV is one-half that of the centre. Tap (for same I/P,
IL O/P) and the output is twice that of the centre tap circuit
I L = m = 0.5 I Lm
2 for the same secondary voltage.

Analog Electronics 246 YCT

 Ans. (b) : CB CE and CC configuration
(ii) BJT Amplifiers voltage gain and current gain
Voltage gain Current gain
1. The configuration of cascode amplifier is CB High Less than unity
(a) CE – CC (b) CE – CB CE Medium high
(c) CC – CB (d) CC – CC CC low High
UPPSC ITI Principal/Asstt. Director-09.01.2022 5. The voltage gain of amplifier stage is lowest in
TNPSC AE - 2018 (a) CB
Nagaland PSC (Degree 2018, Paper-II) (b) CE
GPSC Asstt. Prof. 11.04.2017 (c) CC
RPSC Vice Principal ITI-2016 (d) Same in all configurations
TSPSC Manager (Engg.) - 2015
UPRVUNL AE-19.07.2021, Shift-II
DRDO-2008
GATE-2005, 1997 UPPCL AE-05.11.2019
Ans. (b) : TNPSC AE-2019
The configuration of cascode amplifier = CE –CB Nagaland PSC- 2018, Diploma Paper-II
The configuration of cascade amplifier = CE – CC Nagaland PSC- 2018, Diploma Paper-I
The configuration of Darlington pair = CC – CC IES-2007, 2006, GATE-2003
• The cascode connection is used to obtain large Ans. (c) :
output Impedance. Characteristic CB CE CC
• Darlington connection used to obtain high current Input impedance Low Medium High
gain.
output impedance High Medium Low
• The Voltage gain of Amplifier can be increased by
using cascading connection of individual stages. Voltage gain High Medium Low
2. The addition of the emitter resistor to the dc Current gain Low Medium High
bias of the BJT ____stability of the circuit. Phase shift 0º 180º 0º
(a) Degrades (b) Does not affect 6. Common collector transistor configuration in
(c) Improves (d) Destabilize used for
UPPSC ITI Principal/Asstt. Director-09.01.2022 (a) voltage amplification
Ans. (c) : The addition of the emitter resistor to the dc (b) current amplification
bias of the BJT improves stability of the circuit. (c) impedance matching
3. In CE configuration of transistor, the output (d) rectification
UPRVUNL AE-19.07.2021, Shift-II
"Volt-amp." characteristics is plotted as
UPPCL AE-16.11.2013
(a) VCB Vs IC for constant values of IE Mizoram PSC AE/SDO 2012-Paper-I
(b) VCC Vs IC for constant values of IB
Ans. (c) : Used for the purpose of impedance
(c) VCE Vs IC for constant values of IB matching.
(d) VCB Vs IC for constant values of IB
Parameter Common Common Common
UPPSC ITI Principal/Asstt. Director-09.01.2022 base emitter collector
Ans. (c) : CE configuration at transistor 1 output Current I I I
gain α dc = C βdc = C γ= E
IE IB IB
Voltage high medium <1
gain
7. In order to operate a CE amplifier in
saturation region, which of the following
conditions should be satisfied?
(a) The emitter resistor must be connected
(b) IB > IC(sat)/ β(DC)
(c) IB = IC(sat)
(d) Vcc must be at least 10 V
UPRVUNL AE -19.07.2021, Shift-II
VCE v/s IC for constant value of IB TNPSC AE- 2019
4. Among CB, CE and CC configurations of the Ans. (b) : Condition to operate CE amplifier in
amplifiers, which is having low voltage gain saturation region
and high current gain?
(a) All of the above (b) Only CC IC( sat )
(c) CB and CC (d) Only CE IB >
β ( DC )
UPPSC ITI Principal/Asstt. Director-09.01.2022
Analog Electronics 247 YCT
8. An ideal value of input resistance of trans 14. For a single stage CE amplifier, if Ai = –49.32,
resistance amplifier is. R1 = 1093 ohms, RC = 1k Ω and RL = 1.2 kΩ ,
(a) infinity (b) zero then the voltage gain is .
(c) low (d) high
UPRVUNL AE -19.07.2021, Shift-II
Ans. (b) : Input resistance of transresistance amplifier
should be zero & the output resistance of transresistance
amplifier should be infinite.
9. What is the typical range of the output
impedance of a common-emitter configuration?
(a) 40 KΩ to 50 KΩ (b) 1 KΩ to 5 KΩ
(c) 500 KΩ to 1 KΩ (d) 10 Ω to 100Ω
UPRVUNL AE -19.07.2021, Shift-II (a) – 24.61 (b) – 20
Ans. (a) : Output impedance of CE configuration, (c) 20 (d) 24.6
UPRVUNL AE -19.07.2021, Shift-II
ZO = RC Range (40 KΩ to 50 KΩ)
Ans. (a) : Voltage gain,
10. If α DC = 0.99, I C = 6mA and I CBO = 15µA, what
A R'
is the value of IB ? Av = i L R'L = R L R C
(a) 45 µA (b) 60 µA Ri
(c) 50 µA (d) 55 µA 6
−49.32 × × 103
UPRVUNL AE -19.07.2021, Shift-II
11 1.2kΩ ×1kΩ
Ans. (a) : α dc = 0.99, IC = 6mA and ICBO = 15µA = R 'L =
1093 1.2kΩ + 1kΩ
I C = α dc I E + ICBO 6
= A v = −24.61 R 'L = kΩ
⇒ I C = 0.99 ( I B + I C ) + 0.015 11
⇒ 6 = 0.99 ( I B + 6 ) + 0.015 15. Stability factor S of a self bias circuit depends
on
⇒ 6 − 0.015 = 0.99 ( I B + 6 )
(a) β alone (b) β, Rb and Re
⇒ I B + 6 = 6.045 (c) β, Rb and Rc (d) Rb and Rc
⇒ I B = 6.045 − 6 = 0.045 mA APPSC Poly. Lect.14.03.2020
Nagaland PSC CTSE (Diploma)-2017, Paper-II
⇒ I B = 45 µA
IES-2016
11. An amplifier using transistor has a voltage gain Mizoram PSC AE/SDO 2012-Paper-I
of 100. If the input voltage is 65 mV, the output Ans. (b) : The stability factor should be as low as
voltage is: possible so that collector current does not get affected.
(a) 6.5 V (b) 1.33 V
β +1
(c) 13.3 V (d) 4.15 V S=
UPRVUNL AE -19.07.2021, Shift-II  ∂I 
1− β B 
Ans. (a) : Av = 100, Vi = 65 mV, V0 = ?  ∂IC 
Av = 0
V 1+ β
The stability factor of self bias is s =
Vi  RE 
1+ β 
⇒ V0 = 100×65×10–3 = 6.5 V
 R th + R E 
12. For an amplifier, which parameter is In self bias, stability factor is depend to R , R , β
E th
calculated with VS = 0?
(a) A1 (b) R0 According to above definition option ‘(b)’ is correct.
(c) Ri (d) AV IB and IC depends on RB and RE so S depends on β, RB
UPRVUNL AE -19.07.2021, Shift-II and RE .
Ans. (b) : To find output Resistance of an amplifier, 16. Which of the following holds FALSE for BJTs?
source voltage should be short circuited or VS = 0. (a) The quantity beta (β ) provides an important
13. What is the collector current for a CE relationship between the base and collector
configuration with a β of 100 and a base currents, and is usually between 50 and 400.
current of 30 µA? (b) The impedance between terminals of a
(a) 4.330 mA (b) 3 mA forward-biased junction is always relatively
(c) 6 µA (d) 330 µA large, whereas the impedance between
UPRVUNL AE -19.07.2021, Shift-II terminals of a reverse-biased junction is
Ans. (b) : IC = βIB usually quite small.
= 100×30µA (c) The dc beta is defined by a simple ratio of dc
IC = 3mA currents at an operating point.
Analog Electronics 248 YCT
 (d) The quantity alpha (α) relates the collector 20. Introducing a resistor in the emitter of a
and emitter currents and is always close to common emitter amplifier stabilizes the dc
one. operating point against variation in
APPSC Poly. Lect. 15.03.2020 (a) only the temperature
Ans. (b) : In forward Bias → Rf (Small) (Ω) (b) only the β of the transistor
(c) both temperature and β
Reverse Bias → Ro (Very large) (MΩ) (d) none of the above
17. Current amplification factor for a common Nagaland PSC (Degree) 2018, Paper-II
base connection is 0.5. What is the value of base UPSC JWM-2016, BPSC Poly. Lect-2014
current if emitter current 1 mA?: GATE-2000
(a) 0.5 mA (b) 0 mA Ans. (c) : DC operating point or quiescent point or Q
(c) 0.1 mA (d) 1 mA point depend on the following parameter-
APPSC Poly. Lect. 15.03.2020 1. ICBO or ICO
Ans. (a) : Given as- 2. Temperature
Current amplification factor, α = 0.5 3. Current gain factor ( β )
Emitter current IE = 1 mA As temperature increases, the values of ICE, β , VBE gets
IC affected
0.5 =
IE T ↑ ICBO↑ ICEO ↑ IC↑ T ↑
0.5 × 1 = IC • I CBO gets doubled for every 10ºC rise.
• VBE decrease by 2.5mV every 1ºC rise.
IC = 0.5 mA
21. A transistor works in three regions:
I B = I E − IC 1. Cut-off 2. Active
= 1 − 0.5 = 0.5mA 3. Saturation
18. For a transistor amplifier to be inherently While used as switch in digital logic gates, the
stable against thermal runaway, the condition regions it works in are:
is (a) 1 and 2 only (b) 2 and 3 only
(a) VCE < (VCC/2) (b) VCE > (VCC/2) (c) 1 and 3 only (d) 1, 2 and 3
(c) VCE = (VCC/2) (d) none of these Mizoram PSC Jr. Grade-2015, Paper-I
RPSC VP/Suptd. ITI 05.11.2019 ISRO Scientist May-2017, IES-2010
Mizoram PSC Jr. Grade -2018, Paper-II Ans. (c) : In digital circuit, transistor works on two
Nagaland PSC CTSE (Degree)-2017, Paper-II levels
IES-2000 1- high logic
Ans. (a) : Thermal runaway takes place when 0- low logic
1 These high and low logic obtained by switching the
VCE > Vcc . So to eliminate thermal runaway we transistor ON and OFF mode.
2
Transistor work in OFF mode in cut-off region, and
1 ∂P ∂P
should have VCE < VCC and C < D work is ON mode in saturation mode.
2 ∂TJ ∂TS Saturation - ON mode
19. A transistor is operating in the active region. Cut-off - OFF mode
Under this condition In saturation region both EB and CB is forward biasing,
(a) both the junction are forward-biased. in cut-off region both EB and CB is reverse bias.
(b) both the junction are reversed biased. 22. In a common emitter amplifier, the unbypassed
(c) Emitter-base junction is forward biased and emitter resistor provides
collector-base junction is reversed biased. (a) voltage-shunt feedback
(d) None of these (b) current-series feedback
Nagaland PSC CTSE (Diploma)-2018, Paper-I (c) negative-voltage feedback
Mizoram PSC IOLM-2018, Paper-I (d) positive-current feedback
GPSC Asstt. Prof. 11.04.2017 TNPSC AE-2018
Mizoram PSC Jr. Grade-2015, Paper-I GPSC Asst. Prof.- 11/04/2017, TNPSC AE-2008
IES-2016, 2015, 2009 Ans. (c) : In an common emitter amplifier, the un-
Mizoram PSC AE/SDO 2012-Paper-I bypassed emitter resistor provides the negative voltage
Ans. (c) feedback. It decrease the gain to a desired value.
Mode Emitter base Collector-base 23. The emitter follower configuration is an
junction junction example of
Cut-off Reverse bias Reverse bias (a) Voltage-series feedback
Active Forward bias Reverse bias (b) Current series feedback
(c) Current shunt feedback
Saturation Forward bias Forward bias
(d) Voltage shunt feedback
Reverse active Reverse bias Forward bias Nagaland PSC CTSE (Diploma)-2018, Paper-I
Analog Electronics 249 YCT
 ISRO Scientist Engg.2018 IP
RPSC LECTURER-10.01.2016 I rms =
Ans. (a) : It has voltage series negative feedback. Its 2
voltage gain is less than 1 and current gain is high, due I P = 2 I rms
to its high input impedance and low output impedance,
its impedance matching. Common collector is also 12.5
IP = 2 × = 2.4899
known as emitter follower. 4
24. If α = 0.98, I CO = 6 µA and I B = 100µA for a IP = 2.50 A
transistor, then the value of IC will be 2
Idc = I P
(a) 2.3 mA (b) 3.1 mA π
(c) 4.6 mA (d) 5.2 mA Pdc = VCC Idc
ISRO Scientist Engg.-2016
2
Ans.(d): Given value, α = 0.98 = 15 × × 2.5
ICO = 6µA π
P
I B = 100µA, ICO = ICBO η = ac ×100
Pdc
Q IC = βI B + (1 + β ) ICBO
12.5
α 0.98 = × 100
β= = = 49 2
15 × × 2.5
1 − α 1 − 0.98 π
(Where, IC = collector current, ICBO = leakage current) η = 52.36%
IC = 49 × 100 × 10 −6 + 50 × 6 × 10−6 η 52%
= 4.9 × 10 −3 + 300 × 10 −6 26. In the circuit given below, assume that
VCC = 15V; Z1, Z2, Z3 & Z4 are identical Zener
IC = 4.9 ×10 −3 + 0.3 × 10 −3
diodes with breakdown voltage of 5V; R1 = R4
IC = 5.2 × 10 −3 = 5kΩ, R2=R3=10kΩ
IC = 5.2 mA Find V0 when Q1 is OFF.
25. It is required to design a class B output stage
(as shown below) to deliver an average output
power of 12.5W to a load of 4Ω. The power
supply is selected so that VCC is 5V greater than
the peak output voltage. Determine the power
conversion efficiency of the circuit.

(a) 7.5 V (b) 5V

(c) 10V (d) 8.33V
ISRO Scientist Engg.-2010
(a) 48% (b) 50% Ans. (c) : Given,
(c) 52% (d) 54% VCC = 15V
ISRO Scientist Engg.-2010 Z1, Z2, Z3, Z4 are identical zener diodes
Q1 is off (∴ IC = 0)
Ans. (c) : V rms = P × R = 12.5 × 4 = 50
2
Apply KCL at collection node-
Vrms = 50V
V0 − 15 V − 5 V0 − 5
VP = 2 × 50 = 10V +0+ 0 + =0
5kΩ 10kΩ 10kΩ
 VL  2V − 30 + V0 − 5 + V0 − 5
Q Vrms =  = 0
 2 10kΩ
VCC = 5 + VP = 5 + 10 = 15V ⇒ 4V0 = 40
12.5 12.5 V0 = 10V
I 2 rms = = 27. The base resistor method is generally used in
R 4
(a) Amplifier circuits (b) Switching circuits
12.5
I rms = (c) Rectifier circuits (d) None of the above
4 Nagaland PSC (CTSE) Diploma-2017, Paper II

Analog Electronics 250 YCT

Ans. (b) : The base resistor method is generally used in (a) 20 (b) 30
switching circuit. Base bias is not suitable for high (c) 40 (d) 50
emitter current. Nagaland PSC (CTSE) Diploma-2017, Paper II
28. In a particular biasing circuit, the value of RE Ans. (c) :
is about……….
(a) 10 kΩ (b) 1 MΩ
(c) 100 kΩ (d) 800 Ω
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (d) : In a particular biasing circuit, the value of RE
is about to few hundred ohms. Alone option (d) 800Ω is
correct option.
29. In voltage divider bias, operating point is 3 V, 2
mA. If VCC = 9 V, RC = 2.2 kΩ, what is the
value of RE? β=∞
(a) 2000 Ω (b) 1400 Ω IC = IE
(c) 800 Ω (d) 1600 Ω VE = 500 × 1× 10−3
Nagaland PSC (CTSE) Diploma-2017, Paper II
VE = 0.5V
Ans. (c) : For voltage divider circuit-
VCE = VCC − IC (RC + RE) VB = 0.7 + 0.5
3 = 9 −2mA (RC+RE) VB = 1.2V
6 For Thevenin theorem
= RC + RE R2
2 3× = 1.2
3 = 2.2kΩ + R E 60 + R 2
R E = 0.8kΩ R 2 = 40KΩ
R E = 800Ω 33. In the circuit, current gain of the ideal
30. In a transistor amplifier circuit VCE = VCB +…. transistor, is 10. The operating point of the
(a) VBE (b) 2 VBE transistor (VCC, IC) is
(c) 5 VBE (d) None of the above
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (a) : VCE = VCB + VBE
VCE = VC −VB + VB−VE
VCE = VC − VE
31. What is the main factor governing the
maximum power rating (PTOT) of a (a) 40 V, 4 A (b) 40 V, 5 A
transistor?
(c) 0 V, 4 A (d) 15 V, 4 A
(a) The maximum collector voltage.
TNPSC AE - 2018
(b) The temperature of the base/emitter junction
(c) The maximum collector current Ans. (b) : IB = 0.5 A IC = β.IB
(d) The temperature of the base/collector junction IC = 10×0.5
Nagaland PSC (CTSE) Diploma-2017, Paper II IC = 5A
Ans. (d) : The maximum power rating of a transistor is
largely governed by the temperature of collector to base And VCC = 40V
junction.
32. In the circuit shown below, the silicon npn 34. In the circuit given, collector to ground voltage
transistor Q has a very high value of β. The is +20V. Which of the following is the probable
required value of R2 (in kΩ) to produce Ic = 1 error?
mA is

(a) Collector – Emitter terminals shorted

(b) Emitter to ground connection open
(c) Base resistor open
(d) Collector base terminal shorted
TNPSC AE - 2018
Analog Electronics 251 YCT
Ans. (b) : VB = 10 V, VCC = 20V 0.995 995
10 − 0.7 β= = = 199
IB = = 0.19 mA 1 − 0.995 5
47kΩ ICEO = (1 + β) ICBO
= (1 + 199) × 0.5 × 10–6
= 200 × 0.5 × 10–6
ICEO = 100 µA
38. Emitter bypass capacitors cause a
(a) High frequency pole in the transfer function
(b) A high pass response
(c) A low pass response
(d) A high frequency zero in the transfer function
Hence the probable error is to emitter ground GPSC Asstt. Prof. 11.04.2017
Ans. (b) : The major function of emitter by pass
connection open. because when emitter ground is open
than IE = 0 IC ∝ IE IC = 0 so, IB = 0 Capacitance is to increase gain.
Emitter bypass capacitors cause a high pass response.
35. The current gain and voltage gain of the 39. The common emitter short circuit gain β of a
Emitter follower circuit given in figure are transistor
(Assume that RS = 500 Ω, R1 = R2 = 50 KΩ, (a) Increases with collector current IC
RL = 2KΩ, hfe = 100 and hie = 1.1 KΩ) (b) Decreases with collector current IC
(c) Increase, become maximum and decrease
with increase of IC
(d) Is not a function of IC
GPSC Asstt. Prof. 11.04.2017
Ans. (c) : The common emitter short circuit Current
(a) 101, 0.1146 (b) 0.9946, 101 gain (β) of a transistor, increasing with IC. For low
(c) 101, 0.9916 (d) 0.9946, 105 value of IC, reaches a maximum value and then
TNPSC AE - 2018 decreases with further increase in IC.
Ans. (c) : Current gain = 1 + hfe 40. Reverse saturation current in the collector
= 1 + 100 region of a transistor
(a) Increases with temperature
β = 101 (b) Decreases with temperature
Now we know that for emitter follower circuit voltage (c) Is not affected by temperature
gain is about to unity. (d) Is affected by base current
Hence α = 0.9946 GPSC Asstt. Prof. 11.04.2017
Ans. (a) : An ideal diode equation-
36. Two transistors have the same value of α but
different gain bandwidth products. One of  ηqVKTD 
I = I S e − 1
them is a germanium transistor and the other is D  
a silicon transistor. Both the transistors have  
similar geometries and base width. The Where IS − reverse saturation current
transistor with lower GB product q − is the charge on the electron
(a) Is the germanium
VD − applied forward-bias voltage across diode
(b) Is the silicon
(c) Both are same η = Ideality factor
(d) Cannot be identified unless more information K = Boltzmann' constant
is available T = temperature in Kelvin
ISRO Scientist Engg.-2008 KT
Ans. (b) : Compare to germanium, silicon transistors = VT also known as thermal voltage
q
having less gain bandwidth product.
KT
37. If α = 0.995, IE = 10 mA and ICO = 0.5 µA, then at 300K= 25.9 26mV
ICEO will be q
(a) 100 µA (b) 10.1 mA  VD 
(c) 25µA (d) 10.5 mA Now, I D = IS  e ηVT − 1
 
ISRO Scientist Engg.-2008  
Ans. (a) : Given, Note- that the saturation current is not a constant for a
given device, it varies with temperature: this variance is
α = 0.995, IE = 10 mA, ICO = 0.5 µA the dominant term in temperature coefficient for a
α diode. A common rule of thumb is that it double for
β=
1− α every 10ºC rise in temperature.

Analog Electronics 252 YCT

41. For the lower Q-point operation of a diode ac 45. The emitter resistor RE is bypassed by a
resistance is capacitor in order to
(a) high (b) low (a) Stabilize the Q point
(c) very low (d) reduced (b) Cause thermal runaway
Mizoram PSC AE/SDO 2012-Paper-I (c) Increase the voltage gain
ηVt (d) Reduce the voltage gain
Ans. (a) : Dynamic resistance rd =
ID Mizoram PSC IOLM -2018, Paper II
from the given graph, for a lower Q-point operation, do Ans. (a) : The main function of the emitter resistor RE
will be lower. bypassed by a capacitor is to improve the stability of the
transistor.
46. The current ICBO flows in the
(a) Emitter and base leads
(b) Collector and base leads
(c) Emitter and collector leads
1 (d) None of these
rd ∝ , for lower Q-point, rd will be high. Mizoram PSC IOLM -2018, Paper I
ID
Ans. (b) : The ICBO is a collector to base reverse
42. For 1 volt emitter bias what is RE if saturation current. This current is amplified by I
CBO to
IE = 300mA
Produced additional collector current.
(a) 1Ω (b) 3.33Ω
(c) 6.667Ω (d) 33.3Ω 47. For what kind of amplifications can the active
Mizoram PSC AE/SDO 2012-Paper-I
region of the common-emitter configuration be
used?
Ans. (b) : VE = IE. RE
(a) Voltage (b) Current
VE (c) Power (d) All of these
RE =
IE Mizoram PSC IOLM -2018, Paper I
1 Ans. (d) : Voltage, current and power amplification can
RE = be used in active region of the common emitter.
300 mA
48. BJT is three terminal device which stands for
10
RE = bipolar junction transistor. Which of the
3 following are true about BJT.
R E = 3.33Ω 1. Base has smallest area to reduce the transit
time.
43. In a amplifier, variation in β causes 2. collector is provided with the largest area to
(a) Bias unstability (b) Bias stability withstand heat dissipation.
(c) Zero bias (d) None of these 3. BJT is a current controlled device.
Mizoram PSC IOLM -2018, Paper II 4. BJT is a voltage controlled device.
Ans. (b) : In fixed biased circuit, β is dependent there (a) 1, 2 and 3 (b) 1, 2 and 4
is any change in circuit parameter the value of β will be (c) only 1 and 2 (d) only 2 and 4
change, hence β will change due to change in bias UPPCL AE-16.11.2013
stability.
Ans. (a): A BJT is stands for Bipolar junction transistor
44. In a transistor circuit IB remains constant but it is a three terminal device. It's base has smallest area
β increases
to reduce the transit time and it is a CC device.
(a) Operating point will go down
49. A Silicon BJT has leakage current ICBO of 10
(b) Operating point will go up
nA at 30ºC. If the temperature rises to 60ºC,
(c) Operating point will not change it position calculate the leakage current-
(d) Operating point will shift as per value of base
(a) 80 nA (b) 40 nA
current IB
Mizoram PSC IOLM -2018, Paper II (c) 60 nA (d) 20 nA
UPPCL AE-16.11.2013
Ans. (b) : Given that-
I B = constant Ans. (a) : For an increment of 10º, current will be
double. Hence.
β = increases
at 30º → current 10 nA
IC at 40º → current 20 nA
β= ↑ β ∝ IC ↑
IB at 50º → current 40 nA
So operating point will go up. at 60º → current 80 nA

Analog Electronics 253 YCT

50. Operating point 'Q' of the given circuit in Ans. (c) : In CE configuration its power gain is the
figure is- highest.
It is only configuration providing phase inversion.
It provides voltage and current gains more than unity.
52. What is the Q-point for a fixed-bias transistor
with IB = 75 µA; βDC = 100, VCC = 20 V, RC =
1.5 kΩ
(a) VC = 20.25 V (b) VC = 11.25 V
(c) VC = 8.75 V (d) VC = 2.75 V
UPSC JWM-2016
Ans. (c) : IB = 75 µA βDC = 100
VCC = 20 V RC = 1.5 kΩ
VC = VCC – β IB × RCC
= 20 − 100 × 75 × 10 −6 × 1.5 × 103
(a) (4.833V, 1.03 mA) (b) (6V, 1.03 mA)
(c) (5V, 2mA) (d) (4.833V, 1mA) = 20 − 11.25
UPPCL AE-16.11.2013 V C = 8.75 V

Ans. (a) : Apply KVL in base loop. 53. The voltage across load resistor of a capacitor
coupled CE amplifier is
(a) DC & AC (b) DC only
(c) AC only (d) Neither DC nor AC
UKPSC Assistant Radio Officer Screening Exam.-2011
Ans. (c) : For capacitor coupled CE amplifier the
output voltage is cascaded to the next step via capacitor
coupling with ensure DC biasing point should not be
effected for the next state site where as input is given in
–10 + 900 IB + 0.7 = 0 base terminal.
9.3 54. Under steady state, thermal runaway in a CE
IB = amplifier is avoided if
900 ×103
∂Pc 1 ∂Pc 1
I B = 0.01033 mA (a) = (b) <
∂Tc θ ∂Tc θ
9.3
IC = β.I B = 100 × ×10−3 ∂Pc 1 ∂Pc
900 (c) > (d) =θ
∂Tc θ ∂Tc
9.3
IC = mA = 1.033mA TNPSC AE-2014
9 IES-2001
IE = IB + IC = 1.03 + 0.0103 Ans. (b) : We know obtain the restrictions to be met if
IE = 1.043mA thermal runaway is to be avoided. The required
Apply kVL in collector loop condition is that the rate at which heat is released at
–10 +1.03 × 5 + VCE = 0 collector junction must not exceed the rate at which heat
can be dissipated;
VCE = 4.83V
∂Pc ∂PD
Q point (VCE, IC) = (4.83, 1.03 mA) < ( ∆T = θPD )
∂Tj ∂Tj
51. Consider the following statements about CE
configuration: ∂Pc 1
1. Its power gain is highest <
∂Tj θ
2. It is only configuration providing phase
inversion 55. In the transistor clipping circuit, the transistor
3. Its output resistance is very high is operated in its
4. It provides voltage and current gains more (a) Break down region
than unity (b) Either in cut-off or in saturation or in both
Which of the above statements are correct? regions
(a) 1, 2 and 3 only (b) 3 and 4 only (c) Along the load line
(c) 1, 2 and 4 only (d) 1, 2, 3 and 4 (d) Active region
UPSC JWM-2016 TNPSC AE-2014
Analog Electronics 254 YCT
Ans. (b) 60. If the base current of a BJT is 250 µA and
emitter is 15 mA, then the common base
current gain will be
(a) 0.98 (b) 0.41
(c) 59 (d) 55
RPSC LECTURER-10.01.2016
Ans. (a) : QI E = IB + IC
In the transistor clipping circuit, the transistor is 15×10-3 = 250 ×10-6 +IC
operated in its either in cut-off or in saturation or in IC = 15×10-3 - 250 × 10-6
both regions. IC= 5×10-3 (3 - 50×10-3)
56. While using a bipolar junction transistor as an 5 295
amplifier, the collector and emitter terminals IC = ×
got interchanged mistakenly. Assuming that 1000 100
the amplifier is a common emitter amplifier IC = 0.01475 A
and the biasing is suitably adjusted, the IC
interchange of terminals will results into which Common base current gain ( α ) =
one of the following? IE
(a) Infinite gain 0.01475
α=
(b) Zero gain 15 ×10−3
(c) No change in gain at all α = 0.98
(d) Reduced gain
TNPSC AE-2014 61. The signal handling capacity of an amplifier
Ans. (d) : While using a bipolar junction transistor as will be high when the operating point is
selected
an amplifier, the collector and emitter terminals get
interchanged mistakenly. Assuming that the amplifier is (a) Close to saturation region
a common emitter amplifier and the biasing is suitable (b) Close to cut-off region
adjusted, the interchange of terminals will result into (c) At the extremities of the active region
reduce gain. (d) In the middle of the active region
57. The Q point of a voltage divider bias circuit is Nagaland PSC CTSE (Degree)-2016, Paper-II
(a) sensitive to change in current gain Ans. (d) : The signal handling capacity of an amplifier
(b) totally insensitive to change in current gain will be high when 'Q-Point' lies in the middle of active
(c) insensitive to change in temperature region.
(d) insensitive to change in emitter resistor 62. For good stablised biasing of the transistor of
TNPSC AE-2013 the CE amplifier we should have
Ans. (b) : The Q-point of a voltage divider bias circuit (a) R e << 1 (b) R e << h FE
is totally insensitive to change in current gain. Q point Rb Rb
is the point on the output characteristic that shows the
Re Re
DC collector emitter voltage and collector current (Ic) (c) >> 1 (d) >> h FE
with no input signal applied. Rb Rb
58. Unique features of a CC amplifier circuit is Nagaland PSC CTSE (Degree)-2016, Paper-II
that it Ans. (c) : For good stabilized biasing of transistor of the
(a) steps up the impedance level R
(b) does not increase signal voltage CE amplifier we should have e >> 1
Rb
(c) acts as an impedance matching device
(d) all the above 63. In a transistor if β = 100 and collector current
TNPSC AE-2013 is 10 mA, then IE is…………
Ans. (d) : Common collector (CC) amplifier provide (a) 100 mA (b) 10.10 mA
the stepping up to the impedance level and does not (c) 110 mA (d) none of the above
increase signal voltage and common collector is used Nagaland PSC CTSE (Diploma)-2017, Paper-I
for impedance matching.
Ans. (d) : β = 100
59. The power dissipation of the transistor equals
IC = 10 mA IE = ?
the collector-emitter voltage times the
(a) Base Current (b) Load Current I
α= C
(c) Zener Current (d) Fold back Current IE
Mizoram PSC Jr. Grade-2015, Paper-II β 100
TNPSC AE-2013 α = = = 0.99
1 + β 101
Ans. (b) : Power dissipation in transistor
I 10 × 10−3
P = VCE × IL IE = C = = 10.10 mA
α 0.99
Analog Electronics 255 YCT
64. The relation between β and α is……….. 68. In BJT, DC load line joins
(a) β = 1/ (1 − α) (b) β = (1 − α)/α (a) IC(more) and VCC (b) IC and VCE
(c) β = α / (1 − α) (d) β = α / (1 + α) (c) IC(Max) and VBE (d) IB and VCE
Nagaland PSC CTSE (Diploma)-2018, Paper-I Nagaland PSC CTSE (Diploma)-2018, Paper-I
Nagaland PSC CTSE (Diploma)-2017, Paper-I Ans. (b) : The gap between collector current and
Ans. (c) : As we know - collector to emitter voltage is known as load line
I E = IC + I B characteristic.
I E IC I B
= + (Both side divided IC)
IC IC IC 3

2
1 1  IC IC 
= 1+  α = I ,β = I  1
α β  E β 
IB0
1 β +1
=
α β 69. The early effect in a bipolar junction transistor
is caused by
β (a) Fast turn-on
α=
1+ β (b) Fast turn-off
(c) Large collector base reverse bias
α
or β= (d) Large emitter-base forward bias
1− α Nagaland PSC CTSE (Diploma)-2018, Paper-I
65. The Q point in a voltage amplifier is selected in Ans. (c) : The early effect in a bipolar junction
the middle of the active region because transistor is caused by large collector base reverse bias
(a) it gives a distortion less output due to early effect there is an increment of collector
(b) the operation point then becomes very stable. current.
(c) the circuit requires less number of resistors 70. The dc current gain of BJT is 50. Assuming
(d) none of these that the emitter injection efficiency is 0.985, the
Nagaland PSC CTSE (Diploma)-2018, Paper-I base transport factor is
MPPSC Forest Service Exam.-2014 (a) 0.980 (b) 0.985
Ans. (a) : Q-point is the operating point of the (c) 0.990 (d) 0.995
transistor. It is selected in the middle of the active Nagaland PSC CTSE (Diploma)-2018, Paper-I
region because Ans. (d) : β = 50 Base transport factor
(1) It gives or provides maximum possible amplification
to input sinusoidal signal without any distortion. β α
α= B=
(2) The stability of the operating point depends on the 1+ β y
type of bias used and not on the Q point. Voltage 50 50 1
divider bias has better stability than a simple fixed bias α= B= ×
circuit. 51 51 0.985
V1 = 0.985 B = 0.995
66. Largest current flow of a bipolar transistor
occurs 71. A voltage divider biased amplifier has its Q
(a) In emitter point at the middle of the DC load line. What is
the maximum unclipped peak to peak output
(b) In base
voltage?
(c) In collector (a) VCEQ (b) ICQ RC
(d) Through emitter - collector (c) 2 I R (d) 2 V
CQ C CEQ
Nagaland PSC CTSE (Diploma)-2018, Paper-I
Mizoram PSC Jr. Grade-2015, Paper-II
Ans. (a) : We know that for both transistor (npn or pnp) Ans. (a) : The voltage polarities and current are show
IE=IB+IC for the input voltage.
Hence current through emitter is more as compare to
base and collector current.
67. If the temperature increases then the Q point in
dc load line will be moving towards
(a) Cut-off region
(b) Saturation region
(c) Active region
(d) does not depend on temperature 72. In a BJT, the Ic = 30mA. If β = 100, the base
Nagaland PSC CTSE (Diploma)-2018, Paper-I current approximately equals
Ans. (b) : If the temperature increases then the Q point (a) 0.03 mA (b) 300 mA
in dc load line will be moving towards saturation (c) 0.3 mA (d) 30 mA
region. RPSC Vice Principal ITI-2016

Analog Electronics 256 YCT

Ans. (c) : For BJT IE = IC + IB Tj − TA
I Pd =
and IB = C θ j− A
β 200º −50º
Pd =
30 mA 100º C
So, IB = = 0.3mA
100 150
Pd =
73. Consider the following circuit configurations 100
1. Common emitter Power dissipation Pd = 1.5 watt
2. Common base 76. An amplifier has a signal input voltage Vi of
3. Emitter follower 0.25 V and draws 1 mA from the source. If the
4. Emitter follower using Darlington pair amplifier delivers 8 V to a load of 10 mA, the
The correct sequence in increasing order of the power gain is
input resistances of these configuration is (a) 340 (b) 320
(a) 2, 1, 4, 3 (b) 1, 2, 4, 3 (c) 250 (d) 150
(c) 2, 1, 3, 4 (d) 1, 2, 3, 4 IES-2019
RPSC Vice Principal ITI-2016 Ans. (b) : The ratio of output power and ratio of input
Ans. (c) : Increasing order of the input resistance is power is called as power gain,
mainly depend on type of configuration, so order is So the given,
Common base < Common emitter < Emitter follower < Vi = .25V
Emitter follower using Darlington pair. Ii = 1mA
74. The voltage gain of CE amplifier circuit can be and Vo = 8V
approximated for an ideal input ac source and
is given by Io = 10mA
re' re' VI
(a) A Vs = (b) A Vs = − Power gain = o o
(RC × RL ) (RC RL ) Vi Ii
8 × 10 × 10−3
(c) A Vs = −
( RC RL )
(d) A Vs = −
( RC × RL ) Po =
25 × 10−3
× 100
' '
re re
8 × 10 × 100
Where: RL = Load resistance Po =
25
RC = Collector resistance
Po = 320
re = Effective resistance at input of transistor
from emitter resistance RE 77. In the case of small BJT model with common
IES-2020 emitter, the collector current ic is 1.3 mA,
Ans. (c) : The most common amplifier configuration for when the collector-emitter voltage is vce of 2.6
V. The output conductance of the circuit is:
an NPN transistor is that of the common emitter
amplifier circuit. (a) 2.0 mΩ (b) 2.0 m
(c) 0.5 mΩ (d) 0.5 m
R C || R L IES-2017
A Vs = −
re' Ans. (d) : Conductance is the ratio of current and
voltage so the output conductance of the BJT circuit is,
Where R L = Load resistance
i
R C = Collecter Resistance gm = c
v ce
re' = effective resistance at input of transistor from
The given as, i c = 1.3 mA
emitter resistance RE
I ≤ I Bβ given ( β=50 )
75. If TA = 50ºC, Tj = 200ºC and θj – A = 100ºC/W, C(sat )
the power that a transistor, 2N1701 can safely i
dissipate in free air will be So, g m = c
(a) 0.5 W (b) 1.5 W v ce
(c) 2.5 W (d) 3.5 W 1.3 × 10−3
IES-2020 =
2.6
Ans. (b) : Given, TA = 50º C g m = 0.5 m
Tj = 200º C and θj – A = 100ºC/W 78. Assuming VCE(Sat) = 0.3 V for Silicon transistor
So we know that at ambient temperature of 25ºC and hFE = 50,
Tj − TA the minimum base current IB required to drive
θ j− A = the transistor into saturation for the circuit
Pd shown is
Analog Electronics 257 YCT
 β = 250
and find αdc
β h
α dc = = fe
1 + β 1 + h fe
(a) 64µA (b) 78µA 250
(c) 94µA (d) 140µA =
1 + 250
IES-2016 250
Ans. (c) : = = .996
251
81. A transistor circuit is shown in the figure
Assume β = 100 RB = 200 kΩ, RC = 1kΩ, VCC =
15V, VBEact = 0.7V, VBEsat = 0.8V and
VCEsat = 0.2V.

Applying KVL in CC to EB
5 − 1kΩ × IC − VCE ( sat ) = 0
5 − VCE ( sat ) 5 − 0.3
IC = =
1kΩ 1×103
IC = 4.7mA
For transistor operate in saturation The transistor is operating in
IC(sat ) ≤ I Bβ given ( β=50 ) (a) Saturation (b) Cut-off
4.7 (c) Normal active (d) Reverse active
IB = mA IES-2016
50
Ans. (c)
I B = 0.094mA
I B = 94µA
79. Which of the following regions of operation are
mainly responsible for heating of the transistor
under switching operation?
1. Saturation region
2. Cut-off region
3. Transition from saturation to cut-off
4. Transition from cut-off to saturation According the question
Select the correct answer using the codes given β = 100, R B = 200kΩ, R C = 1kΩ
below:
(a) 1, 2 and 4 only (b) 1, 3 and 4 only VCC = 15V, VBE( act ) = 0.7V VBE sat = 0.8V
(c) 2 and 3 only (d) 1 and 3 only VCE(Sat ) = 0.2V
IES-2016
Ans. (b) : Saturation region transition from saturation to Appling KVL in 1.
cut-off and transition from cut-off to saturation region VCC − IB R B − VBE = 0
of operation are mainly responsible for heating of the
V − VBE
transistor under switching operation. I B = CC
80. The value of hFE (the hybrid parameters) of a RB
Common-Emitter (CE) connection of a Bipolar 15 − 0.7
Junction Transistor (BJT) is given as 250. I B =
200k
What is the value of αdc (ratio of collector
current to emitter current), for this BJT? I B = 71.5µA ........(i)
(a) 0.436 (b) 0.656 I
(c) 0.874 (d) 0.996 β= C
IB
IES-2016
IC
Ans. (d) : For a BJT the value of αdc=? 100 =
hfe = forward current gain is 250 71.5 × 10−6
IC IC = 100 × 71.5 × 10−6
= h fe = 250 ( h fe = β ) IC = 7.15mA
IB

Analog Electronics 258 YCT

 VCC − VCEsat 25 ×103
= VCCsat − IC R C − VCE = 0, IC = 1.9 = I B + ( I B + IC ) ×103 ( I E = I B + IC )
RC 3
1.9 25
VCC − VCEsat = IB + ( I B + IC )
ICsat = 103 3
RC 28I B
15 − 0.2 1.9 ×10−3 = + IC
IC(sat ) = = 14.8 mA. 3
1kΩ I B << IC
ICsat > IC IC 1.9 × 10 −3
So the transistor is work in normal active region. IC 1.9mA
82. A transistor used potential divider method of
83. In biasing of BJT, the slope of load line can be
biasing. R1 = 50 kΩ, R2 = 10 kΩ and RE = 1 kΩ. calculated using
If VCC = 12V and VBE = 0.1 V, then IC is
(a) Operating base current
(a) 19 mA (b) 2 mA (b) Operating collector current
(c) 1.9 mA (d) 0.19 mA (c) Operating point co-ordinates
IES-2015 (d) Minimum and maximum values of collector
Ans. (c) : current
IES-2015
Ans. (d) : In biasing of BJT, the slope of load line can
be calculated using minimum and maximum value of
collector current.
I −I
Slope = c max cmin
VCC
84. Leakage current approximately doubles for
every 10ºC increase in temperature of a silicon
transistor. If a silicon transistor has ICBO = 1000
nA at 30ºC, what is its leakage current at 90ºC?
(a) 32 µA (b) 64 µA
(c) 16 µA (d) 128 µA
IES-2015
IC = ? Ans. (b) : Leakage current of BJT
 t 2 − t1 
 
R2 10 I t 2 = I t1.2  10 
Vth = VCC = × 12
R1 + R 2 50 + 10
I t1 = 1000 × 10 −9
10
Vth = ×12 t 2 = 90
60
t1 = 30
Vth = 2V
I t 2 = leakage current at temperature t2
R th = R 1 || R 2
I t1 = leakage current at temperature t1
1 1 1
= + 90 −30
R th 10 50 I t 2 = 1000nA.2 10

1 5 +1 6 I t 2 = 1000 ×10 −9 × 64
= ⇒
R th 50 50 I t 2 = 64 µA
50 25 85. Which of the following statements are correct?
R th = = kΩ
6 3 1. ICO for germanium is much greater than
for silicon.
2. The steady-state temperature rise at the
collector junction is proportional to the
power dissipated at the junction.
3. To avoid thermal runaway the required
condition is that the rate at which heat is
released at the collector junction must
exceed the rate at which the heat can be
dissipated under steady-state conditions.
(a) 1, 2 and 3 (b) 2 and 3 only
25 (c) 1 and 3 only (d) 1 and 2 only
2 − 0.1 − ×103 × I B − IE ×103 = 0
3 IES-2015

Analog Electronics 259 YCT

Ans. (d) : • ICO of germanium is much greater than 5 − 0.2 4.8
Silicon. IC = = × 10−3
1.2kΩ 1.2
• The steady state temperature rise at the collector IC = 4 mA
junction is proportional to the power dissipated at the
IC
function both (1) and (2) are correct. β=
Leakage current in germanium is µA and leakage IB
current in silicon is nA. IC 4
IB = = ×10−3
86. Transistor is in saturation when β 120
I I B = 0.0333 ×10 −3
(a) IB = IC (b) I B > C
βdc I B = 33.3 × 10−6
IC I B = 33.33 µA
(c) I B = 0 (d) I B <
βdc 88. Thermal runaway in a transistor biased in the
Mizoram PSC IOLM -2018, Paper I active region is due to
IES-2015 1. heating of the transistor.
Ans. (b) : In saturation mode both EB and CB is 2. change in β due to increase in temperature.
forward bias so, if collector voltage drops below the 3. change in reverse collector saturation current
base voltage and emitter voltage is below the base due to rise in temperature.
voltage. The transistor is in saturation mode.
4. base emitter voltage VBE which decreases with
IC rise in temperature.
IB >
βDC Which of the above statements is/are correct?
This is the saturation region. Saturation region when its (a) 1 and 2 (b) 2 and 3
collector current is not dependent on the base current (c) 3 only (d) 4 only
and it reached a maximum value. IES-2014, 2012
87. The transistor switch as shown in figure has Ans. (c) : Thermal runaway in transistor is due to
β = 120, VCE(sat) = 0.2V, RC = 1.2 kΩ, and change reverse collector saturation current (ICO).
VCC = 5V This current ICO gets doubled with every 10ºC rise in
temperature.
IO = IS 2( T2 −T1 ) /10
And if transistor heated, which is known as thermal
runaway.
89. If VCC = 18 V, voltage divider resistances R1=
4.7 kΩ and R2 = 1500Ω, what is the base bias
voltage?
(a) 8.70 V (b) 4.35 V
(c) 2.90 V (d) 0.70 V
The output voltage when transistor switch is
IES-2014
closed and the minimum base current needed
to close the switch are, respectively Ans. (b)
(a) 0.2 V and 3.33µA (b) 2 V and 3.33 µA
(c) 0.2 V and 33.3 µA (d) 2 V and 33.3 µA
IES-2014
Ans. (c)

R2
According to question, Vth = VCC
R1 + R 2
Given as,
1500
Transistor in saturation = × 18
4700 + 1500
VO = VC = VCE (sat ) = 0.2v
1.500
= ×18
VCC − V0 6.200
IC =
RC Vth = 4.35V

Analog Electronics 260 YCT

90. The rise time of a transistor switch is the time 5 − 0.7
for the current to rise from : IB = = 430 µA
(a) Zero value to peak value 10 × 103
(b) 10% of peak value to peak value I 0.96 ×10−3
β= C =
(c) 10 % of peak value to 90% peak value I B 430 × 10−6
(d) 10% of peak value to 80% peak value β = 2.232
IES-2013
Ans. (c) : 10% of peak value to 90% peak value. β is less than 50.
Rise time (tr)- The time taken for the collector current So, transistor is working is saturation region.
to reach from 10% of its initial to 90% of its final value 93. If I
CEO = 410µA, ICBO = 5µA and IB = 30µA
is called as the rise time.
then the collector current is:
91. A CE amplifier has a resistor RF connected
(a) 415µA (b) 440µA
between collector has a resistor RF = 40 kΩ, RC
= 4 kΩ. Given hfe = 50, rπ = 1kΩ, the output (c) 445µA (d) 2.84mA
resistance is: IES-2013
(a) 40 kΩ (b) 20 kΩ Ans. (d) : Given in question
(c) 4 kΩ (d) 0.66 kΩ ICEO = 410µA
IES-2013 I
CBO = 5µA
Ans. (c) : Given- IB = 30µA
R f = 40kΩ , R c = 4kΩ , h fe = 50 , rπ = 1kΩ
ICEO = (1 + β ) ICBO
R o = R c || R f
I
4 × 40 160 1 + β = CEO
= = ICBO
4+4 44
R o = 3.64k R o ≃ 4kΩ 410
1+ β =
5
92. The transistor as shown in the circuit is
operating in: 1 + β = 82
β = 82 − 1
β = 81
Take the value β
We know
IC = βI B + ICEO
IC = 81 × 30 × 10 −6 + 410 × 10 −6
IC = ( 2430 + 410 ) × 10−6
(a) Cut-off region
(b) Saturation region IC = 2840 × 10−6
(c) Active region 2840 × 10−3
IC =
(d) Either in active or saturation region 1000
IES-2013
IC = 2.84 mA
Ans. (b) :
94.

The trans-conductance gm of the transistor

used in the CE amplifier shown in the above
According to figure
circuit, operating at room temperature is
R C = 5kΩ , R B = 10kΩ , VB = 5V , VCC = 5V (a) 92 mA/V (b) 46 mA/V
5 − 0.2 4.8 × 10−3 (c) 184 mA/V (d) 25 mA/V
IC = = = 0.96mA
5 × 103 5 IES-2013

Analog Electronics 261 YCT

Ans. (a) 97. A bipolar junction transistor with forward
current transfer ratio α = 0.98, when working
in CE mode, provides current transfer ratio β
as
(a) 98 (b) 0.02
(c) 49 (d) 0.49
IES-2012
Ans. (c) : According to question,
Given α = 0.98
Given that, β=?
β = 100 α
β=
VBE = 0.7 1− α
VT = 25mV ( at room temperature) β=
0.98
VBB − VBE 3 − 0.7 1 − 0.98
IB = = 0.98
RB 100 × 103 β= = 49
0.02
I B = 2.3 × 10 −5 98. A BJT is biased with a power supply of 12V.
I B = 23 µA For minimum heat dissipation, the drop across
the transistor will be
IC
We know that β = (a) 6 V (b) 9 V
IB
(c) 12 V (d) > 9V but < 12 V
IC = 100 × 23 × 10 −6 = 2.3mA IES-2012
IC −3
2.3 × 10 Ans. (a) : Thermal runaway in transistor is due to
∴ transconductance (gm) = = = 92mA/V reverse collector saturation current (ICO)
VT 25 × 10−3
When transistor heated, which is known as thermal
95. If an npn silicon transistor is operated at runaway.
VCE = 5V and IC = 100 µA and has a current To avoid thermal runaway
gain of 100 in the CE connection, then the input V
resistance of this circuit will be VCE ≤ CC
2
(a) 250 Ω (b) 25 kΩ
12
(c) 250 kΩ (d) 2500 kΩ VCE ≤
IES-2013 2
Ans. (b) : VCE = 5V VCE ≤ 6
IC = 100 µA VCE = 6V
Current gain (hfe) = 100 99. For the transistor circuit shown in the figure,
h fe h fe .VT  IC  when:
Ri = =  gm = 
gm IC  VT 

100 × 25 × 10−3
= (VT = 25 mV at room temperature)
100 ×10−6
R i = 25kΩ
96. A transistor is said to be useful to be
configured as an amplifier when its β is
(a) Less than 0 (b) Between 0 and 1
(c) Between 1 and 50 (d) > 50 1. Vin > 0, transistor is OFF
IES-2012 2. Vin ≤ 0, transistor is OFF
Ans. (d) : For the current gain of the common emitter I
3. I B > C , transistor is ON
amplifier to be large the value of β needs to be very h FE
high. IC
4. I B ≤ , transistor is ON
I h FE
β= C
IB Which of the statements are correct?
(a) 1, 2, 3 and 4 (b) 1 and 2 only
Thus the β > 50 in CE amplifier in thus cases, we can
(c) 2 and 3 only (d) 3 and 4 only
say that it work as a current amplifier. IES-2011
Analog Electronics 262 YCT
Ans. (c) : Vin ≤ 0 transistor is off 102. The collector and Emitter current levels for a
I transistor with Common base dc current gain
I B > C , transistor in ON of 0.99 and base current of 20µA are
h FE respectively.
Above both condition turn on the transistor. (a) 2 mA and 1.98 mA (b) 1.98 µA and 2 mA
When IC = [Link] then transistor operate in active region. (c) 1.98 mA and 2 mA (d) 2 mA and 1.98 µA
And IC < h fe .I B then transistor operate saturation region. IES-2011
100. A small signal voltage amplifier in common Ans. (c) : According to question
emitter configuration was working Given,
satisfactorily. Suddenly its emitter- bypass α = 0.99
capacitor (CE) got disconnected. Its: I B = 20 × 10−6 = 20 µA
1. Voltage gain will decrease
2. Voltage gain will increase α 0.99
β= =
3. Bandwidth will decrease 1 − α 1 − 0.99
4. Bandwidth will increase 0.99
Which of these statements are correct? β= = 99
0.01
(a) 1 and 4 only (b) 2 and 3 only β = 99
(c) 3 and 4 only (d) 1, 2, 3 and 4
IES-2011 IC
BSNL (JTO)-2001 β = I
B
Ans. (a) : When emitter bypass capacitor is
disconnected, we used feedback connection for 99 × 20 ×10 −6 = IC
established to emitter resistance 1980 × 10 −6 = IC
Also we know
1.98 mA = IC
Gain ×Bandwidth = constant
Thus, the gain of the feedback amplifier decrease the IC = 1.98 mA
above formula For common collector
When we decrease gain, then Bandwidth increase. I E = IB + IC
101. What is the name of the circuit shown below?
I E = 0.020 + 1.98
IE = 2mA
103. The biasing of an IC in BJT is done by the
following biasing scheme.
(a) Potential-divider biasing scheme
(b) Fixed biasing scheme
(c) Current mirror biasing scheme
(d) Collector to base feedback biasing scheme
(a) Miller sweep
IES-2011
(b) Bootstrap sweep
Ans. (c) : In IC amplifiers BJT biasing is used by the
(c) Schmitt trigger
current mirror scheme. Since the output current is a
(d) Triangular wave generator mirror image of the input current, the circuit is known a
IES-2011, 2004, 1996 current mirror.
Ans. (a) : A current mirror biasing scheme is used in an IC BJT
to reduce the fabrication spacing.
A current mirror is also used as an active load in IC
amplifiers to achieve greater voltage gain.
104. Biasing is used in transistor amplifiers to
1. Stabilize the operating point against
temperature variations
2. Place the operating point in the linear
The above given circuit is a miller sweep circuit region of the characteristics.
application.
3. Make α, β and ICO of the transistor
Miller sweep circuits are the most commonly used independent of temperature variations.
integrator circuit in many devices. It is a widely used 4. Reduce distortion and increases dynamic
saw tooth generator. range.
The transistor miller time base generator circuit is the (a) 1, 2, 3 and 4 (b) 1, 2 and 4 only
popular miller integrator circuit that produce a sweep (c) 1, 2 and 3 only (d) 2, 3 and 4 only
wave form. IES-2011
Analog Electronics 263 YCT
Ans. (b) : Biasing is used in transistor to- 108. Consider the following statements:
● Stabilize the operating point against temperature To draw a.c. equivalent circuit of a transistor, all
variations. 1. d.c. sources are shorted
● Place the operating point in the linear region of the 2. a.c. sources are shorted
characteristics . 3. d.c. sources are opened
• Reduce distortion and increases dynamic range. 4. a.c. sources are connected to d.c. sources
Which of the above statements is/are correct?
105. Why npn-transistors are preferred over pnp-
(a) 2 and 4 (b) 1 and 2
transistors?
(c) 1 only (d) 3 and 4
(a) Leakage current in npn-transistors is less than IES-2009
pnp-transistors
Ans. (c) : To draw a.c equivalent circuit of a transistor
(b) Mobility of majority carrier in npn-transistors d.c source are shorted.
is greater than the mobility of majority carrier
109. Operating point shift can occur in an amplifier
in pnp-transistors.
due to which one of the following?
(c) Bias voltage required in npn is less than in (a) Input frequency variation
pnp-transistors (b) Noise at the input
(d) Bias voltage required in npn is greater than in (c) Parasitic capacitances
pnp-transistors. (d) Power supply fluctuation
IES-2009 IES-2008
Ans. (b) : A NPN transistor has electrons as majority Ans. (d) : Operating point of a device, also known as a
charge carriers where as the PNP transistor has holes as bias point, quiescent point or a point.
majority charge carriers the mobility of electron is Operating point which is obtained from value of the Ic
better than holes, NPN transistor is faster than PNP and Vce when no signal is given to the input operating
transistor so we preferred npn transistor over pnp point shift can occur in an amplifier due to lower supply
transistor. fluctuation. If the power supply change the operating
106. Consider the following statements: point change.
The bias stability of an emitter-bias amplifier The operating point can be easily obtained by dc load
circuit improves by line method.
1. decreasing the value of RB
2. increase the value of RE
3. decreasing the value of RE
4. increasing the value of RB.
5. Increasing the value of RC.
Which of the above statements are correct? 110. Consider the following statements:
(a) 1 and 2 (b) 2 and 3 Bias stabilization in a BJT circuit is very
(c) 3 and 4 (d) 4 and 5 important, because it
IES-2009 1. provides high voltage and current gain
Ans. (a) : The bias stability of a emitter bias circuit can 2. ensures large bandwidth of the amplifier
be improved by decreasing the value of RB and increase 3. keeps the operating point unchanged with
the value of RE. change of temperature.
Because RE is used for negative in Amplifier. Which of the above statements (S) is/are
107. Which of the following will be true for a CE correct?
transistor amplifier if the emitter resistor value (a) 1 and 2 (b) 2 and 3
is made equal to zero? (c) 3 only (d) 1 and 3
IES-2008, 2007
1. Its gain will increase
2. Its stability will increase Ans. (c) : Bias stabilization is a process to making Q-
point or operating point independent/unchange of
3. Its gain will decrease changes in temperature and change in transistor
4. Its stability will decrease. parameter.
Select the correct answer from the codes given 111. CE configuration is the most preferred
below: transistor configuration when used as a switch
(a) 1 and 2 (b) 2 and 3 because
(c) 3 and 4 (d) 1 and 4 (a) it requires only one power supply
IES-2009 (b) it requires low voltage or current for
Ans. (d) : In CE transistor amplifier, if the emitter operating the switch
resistor value is made equal to zero the value of gain (c) it is easily understood every one
will increase and stability will be decrease RE provide (d) it has small ICEO
negative feedback and improved the stability IES-2016, 2008, 2000

Analog Electronics 264 YCT

Ans. (b) : CE configuration is the most preferred Ans. (a) : The d.c load line of CE amplifier is drawn in
transistor because it require low voltage and current for
IC versus VCE for a given value of (RC+RE)
operating the switch. CE has low input impedance and D.C. load line analysis significance-
high output impedance. It is used for audio frequency • By using the direct correct load line concept. We can
application. In CE configuration phase shift between obtain the linear analysis of the circuit for non-linear
input and output is 180º. elements such as diodes or transistors.
I • The D.C load line analysis main intention is find the
β is the ratio of IC and IB β = C quiescent point (Q-point).
IB
112. Cascode amplifier when compared with a 115. Consider the following parameters of a hybrid-
simple common-emitter amplifier provide π equivalent circuit of BJT:
which of the following? 1. Trans conductance (gm)
(a) Higher voltage gain and same bandwidth 2. hfe
(b) Same voltage gain but higher bandwidth 3. hie
(c) No change in either voltage gain or Which of the above parameters vary with
bandwidth temperature in similar manner (all of them
(d) Voltage gain less than one but bandwidth decrease or all of them increase)? Select the
equal to fT. correct answer using the code given below:
IES-2007 (a) Only 1 and 2 (b) Only 2 and 3
Ans. (b) : Cascode amplifier when compared with a (c) Only 1 and 3 (d) 1, 2 and 3
simple common-emitter amplifier provide same voltage IES-2006
gain but high band width. h
Application of cascode amplifier- Ans. (b) : Trans-conductance (gm) = fe
h ie
• This amplifier is used in tuned RF amplifiers with
V
television circuit. re = T = α g m
• The isolation offered among input & output with IE
these amplifiers is extremely high. When temperature increase, α increase thus hfe also
113. Which of the following features are offered by increases.
a bipolar junction transistor amplifier in 116. When a voltage divider biased amplifier has its
Darlington connection? Q-point near to the middle of the dc-load line,
1. High voltage gain what is the maximum unclipped peak-to-peak
2. High input impedance output voltage?
3. High current gain (a) VCEQ (b) ICQrL
Select the correct answer using the code given (c) 2ICQrL (d) 2VCEQ
below: IES-2005
(a) 1 and 2 only (b) 2 and 3 only Ans. (d) :
(c) 1 and 3 only (d) 1, 2 and 3
Nagaland PSC (Degree)-2018, Paper-II
IES-2015, 2007, 1992
Ans. (b) :

It is consist of two common collector transistors in

cascade connection. It has unit voltage gain. Very high
input resistance low output resistance and high current
gain. It is used as a buffer amplifier.
114. For a CE amplifier, d.c. load line is drawn in if Q-point is at the middle of D.C load line.
which one of the following plots? V
(a) IC versus VCE for a given value of (RC + RE) VCEQ = CC
2
and VCC Maximum (peak to peak) unclipped voltage = 2VCEQ
(b) IB versus VEE for a given value of (RC + RE) 117. Consider the following statements:
and VCC
1. To achieve wide bandwidth, a transistor
(c) IB versus VCE for a given value of IB with a small Cbc is chosen.
(d) IC versus VCB for a given value of IE 2. To achieve wide bandwidth, a transistor
IES-2007 with a small Cbe is chosen.
Analog Electronics 265 YCT
 3. To achieve wide bandwidth, a transistor 119. Consider the following circuit:
with a small base spreading resistance is
chosen.
Which of the statements given above are
correct?
(a) 1 and 2 (b) 2 and 3
(c) 1 and 3 (d) 1, 2 and 3
IES-2005
Ans. (a) : To achieve wide bandwidth, a transistor with
What is voltage difference between collector
a small Cbc and Cbe is used.
and emitter (VCE) in the above circuit?
118. Consider the following circuits: (a) 10/3 V (b) 0 V
(c) 5 V (d) 3 V
IES-2004
Ans. (c) : Given, VCC = 5V

Which one of then following statements is

correct?
(a) Circuit 1 is parallel connection and Circuit 2
is Darlington connection.
(b) Circuit 1 is cascode connection and Circuit 2 According to figure
is Darlington connection IB = 0
(c) Circuit 1 is Darlington connection and Circuit
we know IC = βI B
2 is cascode connection
(d) Circuit 1 is cascode connection and circuit 2 IC = β × 0 {IB = 0}
is parallel connection. IC = 0
IES-2004, 1997 ∴ V = V − I R − I R
CE CC C C E E
Ans. (b) : VCE = VCC − 0 − 0
VCE = VCC
VCE = 5 V
120. A bipolar junction transistor is in saturation
region. Given VCC = 10 V, RC = 1 kΩ, hFE = 100
and VCEsat = 0.3 V. What is the collector
current in saturation?
(a) 10 mA (b) 9.7 mA
(c) 0 mA (d) 1 mA
IES-2004
From the above figure, Ans. (b) : Given,
VCC = 10V
Circuit 1- is a cascode connection and circuit-2 is a
RC = 1kΩ
Darlington connection.
hFE = 100
In cascade amplifier is a cascode of CE and CB VCE(sat) = 0.3
amplifiers yet Darlington is a cascade of two common
collector amplifier.
Darlington Amplifier used in buffer amplifier cascode
amplifier provide both voltage and current amplification
therefore preferred over common base amplifier in radio
frequency amplification and wideband amplification.
So the option (b) circuit 1 is cascode connection and Applying KVL-
circuit 2 is Darlington connection. VCC – ICRC – VCE(sat) = 0
Analog Electronics 266 YCT
 10 – IC ×1 ×103 –0.3 = 0 The given above circuit is a boot strap circuit. Bootstrap
10 – 0.3 = IC ×1 ×103 biasing network is a special biasing circuit used in
9.7 Darlington amplifier to prevent the decrease in input
= IC resistance due to the biasing network being used.
1× 103 Capacitor and resistance are added to the circuit to
IC = 9.7mA prevent it from happening.
121. Match List-I (Circuit) with List-II (Property) 123. Which of the following main properties of a
and select the correct answer using the codes bipolar junction transistor make it necessary
given below the lists: for the transistor to have bias stabilization ?
List-I List-II 1. Variation of VBE with temperature.
A. R-C coupled single 1. Beta multiplier 2. Variation of hFE with temperature
stage amplifier 3. Variation of ICO with temperature
B. Emitter follower 2. Constant current 4. Variation of hFE with transistor
source replacement
C. Common base 3. Very high input 5. Variation of VBE with transistors
amplifier impedance replacement
D. Darlington amplifier 4. phase inverter 6. Variation of ICO with transistor
with voltage gain replacement
Codes: Select the correct answer using the codes given
A B C D below:
(a) 3 4 1 2 (a) 1, 2 and 6 (b) 1, 3 and 4
(b) 4 3 1 2 (c) 2, 3 and 5 (d) 3, 4, 5 and 6
(c) 3 4 2 1 IES-2003
(d) 4 3 2 1 Ans. (c) : Bipolar junction transistor make it necessary
IES-2003 for the transistor to have bias stabilization
Ans. (d) • Variation of hFE with temperature
R-C coupled single stage amplifier is a phase • Variation of ICO with temperature
inverter. • Variation of VBE with transistors replacement
Emitter follower source is used in impedance The process of making the operating point independent
matching. Emitter follower has low output of temperature charges or variation in transistor
impedance and high input impedance. parameter is known as stabilization.
Common base amplifier has constant current it 124. In the circuit shown below, if R1 >> Rp and the
current gain is equal to very low. impulses can completely saturate transistor Q1.
Darlington amplifier is a two transistor multiplier it is then the output voltage V0 will be
a beta multiplier. It is used in buffer.
122. The biasing shown in the below circuit is

(a) Emitter bias (b) Self bias

(c) Potential divider bias (d) Bootstrap bias (a) (b)
IES-2003
Ans. (d)
(c) (d)

IES-2002
Ans. (d) : There is a CE transistor in a circuit so output
has phase shift of 180º gain due to charging and
discharging of capacitor find output ramp positive and
negative.

Analog Electronics 267 YCT

125. In the circuit shown, 4.3
IB =
100 × 103
4.3
IB = 5
10
I B = 0.043 mA
IC = β× I B (Assume β = 100 )
the transistor is biased at = 100 × 0.043
(a) 0 mA (b) 5 mA IC = 4.3mA
(c) 3.9 mA (d) ∞
IES-2002 Vc = 5 − 5 × 103 × Ic
Ans. (c) : Vc = 5 − 5 × 4.3
Vc = −16.5
VE = 0
If VC < VE {then we know transistor is in saturation
region}
If Vc > VE {Transistor is in active region}
So the option is in saturation region.
127. Consider the following statements regarding
the bootstrap biasing arrangement for a BJT
For saturation emitter follower:
VCE = 0.2V 1. The input impedance is very high
VCC –ICRC–VCE = 0 2. The voltage gain is exactly equal to one
10 –2.5 ×103×IC –0.2 = 0 3. The output impedance is equal to zero
9.8 = 2.5 ×103 × IC Which of these statements is correct?
(a) None (b) 2 alone
9.8
IC = (c) 3 alone (d) 1 alone
2.5 ×103 Kerala PSC Lecturer (NCA)-04.07.2017
IC = 3.92mA IES-2000
126. The transistor in the circuit of the given figure Ans. (d) : Transistor Bootstrapping circuit using BJT-
is operating Boot strapping is a technique used in the design of
transistor amplifier circuit to increase the input
impedance and thereby reduce the loading effects on the
input source. It typically involves the use of bootstrap
capacitor, which provides positive feedback of ac signal
to the base junction of a transistor in an emitter follower
circuit.
128. In the circuit shown in the given figure, the
(a) in the cut-off region approximate voltage at the transistor
(b) in the active region
(c) in the saturation region
(d) either in the active or the saturation region.
Mizoram PSC IOLM -2018, Paper II
IES-2001
Ans. (c)

(a) base and emitter respectively are –8V and –

7.3 V.
(b) base and collector respectively are –8 V and –
5V
(c) collector and emitter respectively are –8V
and –7.3 V
VBB = 100 ×103 × I B + 0.7 (d) base, emitter and collector respectively are –
8V, –7.3 and –5V.
5 = 100 ×103 × I B + 0.7 IES-2000
Analog Electronics 268 YCT
Ans. (a) 130. Consider the following statements:
A totem pole configuration used in the output
stage of an op-amp has the advantage of using
1. only n-p-n BJTs
2. complementary symmetrical pair of
transistors
3. only one transistors
Which of these statement is/are correct?
The give figure is (voltage divider Biasing) we know (a) 1 alone (b) 2 alone
that (c) 3 alone (d) 1 and 3
16 IES-2000
Vth = × −10 Ans. (a) : A totem pole configuration used in the output
4 + 16
stage of an op amp has the advantage of using only n-p-
16
Vth = × −10 n BJT.
20 131. The collector voltage VC of the circuit shown in
Vth = −8v the given figure is approximately
R th = 4 ||16
16
R th = = 3.2kΩ
5
VCE = 0.7 (Assume)
VE = VB + VCE
= –8 + 0.7
VE = –7.3V (a) 2 V (b) 4.6 V
(c) 8 V (d) 8.6 V
129. A common emitter amplifier circuit is shown in IES-1999
the given figure Ans. (c) :

The slope of AC load line is

 1 1   1 
(a) −  +  (b) −  
 RL RC   RL + RC 
1 1  
(c) − (d) − 20 kΩ
RL RC VB = 10  
 20 kΩ + 20 kΩ 
IES-2000
VB = 5V
Ans. (a) : Formula-
VE = VB − VBE
1
=− = 5– 0.7
R C || R L VE = 4.3V
−1 V 4.3
= IE = E = = 1mA
 RC × RL  R E 4.3 kΩ
 
 R L + RC  (IE= IC = 1mA). IB is very low.
 R + RC  VCC –ICRC = VC
= − L  10 – 1×10–3 ×2×103 = VC
 RC × RL  VC = 10 – 2
 RL RC  VC = 8V
= − + 
 R C .R L R C .R L  132. Thermal runaway will take place if the
quiescent point is such that
 1 1 
Slope of A.C load line. = −  +  1
R
 C R L 
(a) VCE > VCC (b) VCC < VCC
2
Analog Electronics 269 YCT
 1 Thevenin's equivalent circuit-
(c) VCE < 2VCC (d) VCE < VCC
2
IES-1999
Ans. (a) : The condition for thermal runaway to occur is
in-
V
VCE > CC
2
133. In a transistor amplifier, the reverse saturation
current ICO.
(a) Doubles for every 10ºC rise in temperature
(b) Doubles for every 1ºC rise in temperature
R 1R 2
(c) Increase linearly with temperature R th = R1 || R 2 =
(d) Doubles for every 5ºC rise in temperature R1 + R 2
IES-1998 1+ β
Ans. (a) : In a transistor amplifier, the reverse Stability factor (s) = ………….(i)
 dI B 
saturation current (ICO) is doubles for every 10ºC rise in 1− β 
temperature.  dIC 
 T2 – T1  dIB dI
  0 = R th + RE + RE B
I0 (T2 ) = I0 ( T1 ) .2 10 
dIC dIC
dI B
134. A transistor is operated as a non-saturated −R E = ( R th + R E )
switch to eliminate dIC
(a) Storage-time (b) Turn-off time 1+ β
(c) Turn-on time (d) Delay time s=
RE
IES-1998 1+ β
R th + R E
Ans. (a) : A transistor switching speed is very crucial
parameter in high speed operation. Lower the switching
s=
(1 + β )( R th + R E )
speed better the performance in speed.
Switching speed depends on storage time and transient
( R th + R E ) + β ( R E )
time. Mainly depends in storage time, if storage time is (1 + β )( R th + R E ) R th << R E (1 + β )
less switching speed is fast the storage time depends on s =
R th + R E (1 + β )
current lower the on current the storage time.
135. For transistor amplifier with self-biasing R + RE
network, the following components are used: s = th …………………(ii)
RE
R1 = 4kΩ, R2 = 4 kΩ and RE = 1 kΩ
The approximate value of the stability factor 4 × 4 16
R th = = =2
'S' will be 4+4 8
(a) 4 (b) 3 Put value at equation (i)
(c) 2 (d) 1.5
2 +1 3
IES-1998 s = = =3
Ans. (b) : Self bias circuit in the given circuit 1 1
R 1 = 4KΩ, R 2 = 4 KΩ R E = 1 KΩ 136. In the circuit shown in the figure, if RL = RC =
Self bias circuit (voltage divider circuit) 1 kΩ, then the value of V0 will be

(a) 4.55 V (b) 2.5 V

(c) 1 V (d) zero
IES-1998

Analog Electronics 270 YCT

Ans. (b) 138. Match List-I (Transistor parameter) with List-
II (Typical value) and select the correct answer
using the codes given below the lists:
List-I List-II
A. rbb 1. 80 kΩ
B. rbe 2. 1 kΩ
C. rce 3. 100Ω
D. Cbe 4. 100pF
5. 3 pF
IC Codes:
Current gain, β =
IB A B C D
(a) 3 2 1 4
IC = βI B
(b) 3 2 1 5
IC = β× 0 (c) 1 3 2 4
IC = 0 (d) 1 3 2 5
∴ IE = IB + IC IES-1997
Ans. (b) : According to question.
=0+0
Typically II- model parameter force is-
=0
rbb is of the order of - 100Ω
Q IE, IB, IC value is zero so, transistor operate in cut-off
region. rbe is the order of - 1kΩ
rce is order of- 80kΩ
cbe is order of - 3pF
139. In the case of the circuit shown in the figure,
the collector current Ic will be

5× RL 5 ×1kΩ
V0 = =
R C + R L 1kΩ + 1kΩ
5
V0 = = 2.5V
2
137. The 'h' parameters of the BJT shown in the
figure are: hib = 25Ω ; hfb = 0.999 and hob = 10–6
The voltage gain is
(a) 2.26 mA (b) 1.85 mA
(c) 0.375 mA (d) 0.185 mA
IES-1997
Ans. (b) :

(a) 0.999 (b) 1.98

(c) 2.0 (d) 400
IES-1997
Ans. (d) : The following question given as
h ib = 25Ω h fb = 0.999 h ob = 10 −6
12
Voltage gain (AV) = ? Vth = × 12
12 + 20
h 0.99 0.99
Current gain = fe = = Vth = 4.5V
1 + h fe 1 + 0.01 1.01
R th = R1 R 2
A i = 0.98 1
Ai R L 1× R L 1 1 1 4 + 12 32
Voltage gain = = = + = =
Zi h il R th 12 20 12 × 20 240
1 4
10 × 103 =
Voltage gain = = 400 R th 30
25
Analog Electronics 271 YCT
 R th = 7.5kΩ Ans. (c) :
• Input at base point and output from collector point→
Applying KVL in input loop- Amplifier in CE mode with no feedback.
• Input at base point and output from Emitter point →
Amplifier in CC mode with feedback.
• Input at Emitter point and output from collector point
→ Amplifier in CB mode with no feedback.
• Input the base point and output from collector point
→ Amplifier in CE mode with feedback.
141. If α = 0.995, IE = 10 mA and ICO = 0.5µA, then
VTh = IBRTh + VBE + IE. RE ICEO will be
VTh = I B R Th + VBE + (1 + β) IB × 2 × 103 (a) 100 µA (b) 25 µA
(c) 10.1 mA (d) 10.5 mA
4.5 = 7.5 ×103 I B + 0.7 + (1 + 100) IB × 2 × 103
IES-1996
3.8 = 103 × IB (7.5 + 202) Ans. (a) : Given,
3.8 = 103 × I B × 209.5 α = 0.995 IE = 10mA ICO = 0.5µA
IB = 0.0181mA ICEO = ?
IC = βIB β
IC = 100×0.0181mA α=
1+ β
IC = 1.81mA ≅ 1.85mA
β
140. The circuit shown in the given figure is 0.995 =
modified according to List-I. Match List with II 1+ β
and select the correct answer using the codes 0.995 + 0.995β = β
given be the lists:
0.995 = β − 0.995β
0.995 = β (1 − 0.995 )
0.995
β=
0.005
β = 199
ICEO = (1 + β ) ICBO
List-I List-II
A. CB = 0, CC = 0, CE = 1. Amplifier in CC ICEO = (1 + 199 ) × 0.5 ×10−6
∞. Input at base mode with ICEO = 200 × 0.5 × 10−6
point and output feedback
ICEO = 100µA
from collector point
B. CB = 0, CE = 0, CC = 2. Amplifier in CB 142. The circuit shown in the given figure is a
∞. Input at base mode with no
point and output feedback
from emitter point
C. CB = ∞, CE = 0, CC = 3. Amplifier in CE
0. Input at Emitter mode with
point and output feedback
from collector point (a) Constant voltage source
D. CB = 0, CE = 0, CC = 4. Amplifier in CE (b) Constant current source
0, Input the base mode with no (c) Common emitter amplifier
point and output feedback (d) Common base amplifier
from collector point IES-1995
Codes: Ans. (b)
A B C D
(a) 1 2 3 4
(b) 4 3 2 1
(c) 4 1 2 3
(d) 2 3 4 1
IES-1996

Analog Electronics 272 YCT

 IB = 0 Ans. (c) : Self biasing (voltage Divider circuit) will give
the best performance in preventing the variation of
then I E ≃ IC = I L collector current against change in ambient temperature.
VZ • Self bias circuit has least stability factor among all
IC = biasing circuit.
RC
• Stability factor is independent of Rc.
VZ • Self biasing circuit can be used to bias BJT for any
IL = There is RC value is constant then the circuit
RC configuration.
behave like a constant current source.
143. Consider the following statements:
Drift in direct coupled amplifiers may be
reduced effectively by use of
1. A diode as thermal compensating element.
2. Another active device, making it a
differential amplifier.
3. Bypass capacitors.
4. Choppers.
Of these statements R2
Vth = VCC
(a) 1 and 3 are correct R 1 + R2
(b) 1, 2 and 3 are correct R th = R1 || R 2
(c) 2 and 4 are correct
145. In the circuits shown in the following figure,
(d) 1, 2 and 4 are correct the feedback causes
IES-1995
Ans. (d) : A direct coupled amplifier is a type of
amplifier in which the output of one stage of the
amplifier is coupled to the input of the next state in such
away as to permit signal with zero frequency also
referred to as direct current, to pass from input to
output. Drift in direct coupled amplifier may be reduced
effectively by use of (a) an increase in both the input and output
• A diode as thermal compensating element. impedance
• Another active device, making it a differential (b) an increase in the input impedance but a
amplifier. decrease in the output impedance
• Choppers. (c) a decrease in both input and output
impedances
144. Which one of the following biasing will give the (d) a decrease in the input impedance but an
best performance in preventing the variation of increase in the output impedance
collector current against change in ambient IES-1994
temperature?
Ans. (b) : In this circuit fraction of the output voltage is
applied in series with the input voltage through the
feedback circuit. So this is a voltage series feedback
(a) (b) circuit.
Due to voltage series feedback input resistance
increases and output resistance decreases.
146. What should be the Collector-Emitter
breakdown voltage BVCEO of the transistors
used in the circuit shown in the given figure?

(d)
(c)

(a) βVCEO ≥ VCC (b) βVCEO ≥ VCC/2

(c) βVCEO ≥ 2VCC (d) βVCEO ≥ (VCC + E)
IES-1994 IES-1993
Analog Electronics 273 YCT
Ans. (b) : The collector Emitter breakdown voltage I E I B IC
β VCEO ≥ VCC / 2 . = +
IB IB IB
147. For the circuit shown in the given figure, the γ = 1+ β
quiescent point is
1  1 
= 1+ β γ = 
1− α  1 − α
1
−1 = β
1− α
1 − (1 − α )
=β
1− α
1−1+ α
=β
1− α
(a) 12 V, 5mA (b) 12V, 2mA α
(c) 10V, 2mA (d) 10V, 5mA =β
1− α
IES-1993
149. Match List-I with match List-II and select the
Ans. (c) Assume β is very high then I B = 0 correct answer using the code given below:
List-I List-II
A. Darlington 1. The output current is the
connection same in both the
devices in the circuit
B. Cascade 2. The output current of the
connection first device becomes the
input current of the
second device
So, IBRB= 0 C. Differential 3. The collector of the first
amplifier device is connected to the
then IC I E
base of the second device
Applying KVL in E-B loop without using capacitor
0–IBRB– VBE – IERE = –30 D. Direct coupled 4. Output voltage depends
0 – 0.7 – IE × 15×103 = –30 amplifier on the relative values of
29.3 the two input voltages
IE = 2mA
15 × 103 Codes:
KVL applying in C-E loop- A B C D
Vcc − Ic R c − VCEQ − I E R E + 30 = 0 (a) 1 2 3 4
(b) 3 4 1 2
20 − 2 ×10−3 × 5 × 103 − VCEQ − 2 ×10−3 × 15 × 103 + 30 = 0 (c) 2 1 4 3
20 − 10 − VCEQ − 30 + 30 = 0 (d) 4 3 2 1
IES-1991
− VCEQ + 10 = 0
Ans. (c) : Darlington Amplifier- Darlington amplifier
VCEQ = 10V is used for buffer. In this amplifier first transistor output
The value of quiescent point current second transistor input current connect.
= (VCEQ, IC)
= (10V, 2mA)
148. For the junction transistor, which of the
following relation is true?
β
(a) α = (b) α = β(1 + β)
β −1
α α
(c) β = (d) β =
1− α 1+ α Common collector configuration
IES-1992 • Cascade connection– Cascade connection is the
Ans. (c) : Basic formula of transistor process the first device output current for the second
I E = IB + IC .............. (i) device input current is called cascading.
In equation (i) divided by IB A = A1 × A 2 × A 3 ..........

Analog Electronics 274 YCT

• Differential Amplifier– Differential amplifier is a 151. In the BJT amplifier shown in the figure is the
type of electronic amplifier that amplifies the transistor is biased in the forward active region
difference between two input voltage putting a capacitor across RE will

In differential amplifier output voltage depends on the

relative value of the two input voltage.
• Direct coupled Amplifier:-
(a) Decrease the voltage gain and decreases the
input impedance
(b) Increase the voltage gain and decreases the
input impedance
Direct coupled amplifier the collector of the first device (c) Decrease the voltage gain and increase the
is connected to the base of the second device without input impedance
using capacitor. (d) Increase the voltage gain and increase the
150. For the amplifier circuit of figure. The input impedance
transistor has a β of 800. The mid band voltage GATE-1997
gain V0/Vi of the circuit will be. Ans. (b) :

(a) 0 (b) < 1

(c) ≈ 1 (d) 800
GATE-1993 1
Ans. (c) : Given, β = 800 Q X CE =
2πfC
• If f→ low, then X CE → High, then current Ie will not
be pass.
• If f→ High, X CE → low
then current Ie will be pass.
Putting a capacitor across common emitter resistance CE
which voltage gain will be increase and decreased the
Input impedance. Capacitor CE act as by pass. Thus
The circuit is PNP transistor, collector coupled 'AC' signals will pass through capacitor CE. Eliminated
amplifier. The voltage gain is unity for a CC amplifier. the feedback effect, it is used to emitter resistance
Equivalent circuit, across capacitor CE. Reduced the input voltage drop.
RE
X CE ≤ ( Pratically conditions )
10
152. The circuit of the figure is an example of
feedback of the following type

V0 V0
Voltage gain = A V = = (Vbe is very small,
Vi V0 + Vbe
let neglected)
V0
≅1
V0 (a) current series (b) current shunt
So, Vi = V0 = Ve ⇒ Emitter always following to input (c) voltage series (d) voltage shunt
Hence, This is condition emitter follower. GATE-1998
Analog Electronics 275 YCT
Ans. (d) So,
Ad
CMRR =
Ac
R E ↑→ A c ↓ CMRR ↑ but A d has not effected.
154. In the circuit of the figure, assume that the
This is figure represented voltage shunt feedback. transistor is in the active region. It has a large
In the voltage shunt feedback circuit a traction of the β and its base-emitter voltage is 0.7 V. The
output voltage is applied in parallel with the input value of Ic is
voltage through the feedback.
Voltage shunt feedback characteristics-
1. Voltage gain – Decreases
2. Bandwidth – Increases
3. Input Resistance – Decreases
4. Output Resistance – Decreases
5. Harmonic distortion – Decreases
6. Noise – Decreases
(a)
Indeterminate since Rc is not given
153. In the differential amplifier of the figure, if the (b)
1 mA
source resistance of the current source IEE is (c)
5 mA
infinite, then the common-mode gain is
(d)
10 mA
GATE-2000
Ans. (d) : Given,
β = large value
VBE = 0.7V
Apply potential divider at point B

(a) zero (b) infinite

V + Vin 2
(c) indeterminate (d) in1
2VT
GATE-2000
10 × 5 10
Ans. (a) : R th = = Ω
15 3
R V
Vth = 2 CC
R1 + R 2
5 × 15
= = 5V
15
Q β = large value
IC I IC
So, β = ⇒ IB = C = ≅0
IB β large value
Q Differential mode gain, I E = IB + IC
Ad = gm (RC || r0) I E = IC (Q IB = 0 )
where r0 = output impedance of BJT
Vth − VBE
and common mode gain IE =
RE
−R C
Ac = R E ↑→ A c ↓ Vth − VBE
2R E So, IC = I E =
RE
Q Differential mode gain Ad independent of RE
Vth − VBE 5 − 0.7 4.3
for ideal transistor amplifier, ∴ IC = = = = 0.01A = 10mA
RE = ∞, then, Ac = 0 RE 430Ω 430Ω

Analog Electronics 276 YCT

155. If the transistor in the figure is in saturation,
then

1 1
because, X C = = =∞
2πf c 0
So, KVL at collector-Emitter loop
(a) IC is always equal to β dcIB VCC = IC R C + VCE
(b) IC is always equal to –β dcIB 6−3
(c) IC is greater than or equal to βdcIB RC = = 2kΩ
1.5mA
(d) IC is less than or equal to β dcIB IC 1.5mA
GATE-2002 And I B = = = 10µA
β 150
Ans. (d) : βdc = denotes the dc current gain. Apply KVL at base-emitter loop
IE = IB + IC VCC = IBR1+VBE
6 − 0.7
I R1 = = 530kΩ
β= C 10µA
IB
Q Transistor will be changed, then β = 200
∴ KVL apply Base-emitter loop

VCC − VBE
IB =
R1
For transistor in saturation,
6 − 0.7
I
I B ≥ C and VCE = 0 = = 10µA
β 530kΩ
then, IC = βI B = 200 × 10µA = 2mA.
156. In the amplifier circuit shown in the figure, the
Again, KVL apply at common-emitter loop
values of R1 and R2 are such that the transistor
is operating at VCE = 3V and IC = 1.5 mA when VCE = VCC − IC R 2 = 6 − 2 × (2)
its β is 150. For a transistor with β of 200, the = 6 – 4 = 2Volt.
operating point (VCE' IC) is for β = 200, ( VCE , IC ) = ( 2V, 2mA )
157. Assuming VCEsat = 0.2 V and β = 50, the
minimum base current (IB) required to drive
the transistor in the figure to saturation is

(a) (2 V, 2 mA) (b) (3 V, 2 mA)

(c) (4 V, 2 mA) (d) (4 V, 1 mA) (a) 56 µA (b) 140 µA
GATE-2003 (c) 60 µA (d) 3 µA
Ans. (a) : Given, VCE = 3V GATE-2004
IC = 1.5mA Ans. (a) : Given,
β = 150 VCE(Sat ) = 0.2V
Q For D.C. signal (f =0), β = 50
then C act as open circuit, Apply KVL at collector to emitter,

Analog Electronics 277 YCT

 IC
and β (current gain) =
IB
IC IC
IB = = ≅ 0, then IC = 1mA
β Very l arg e

(Q IE = IB + IC , IE = 0 + IC , IE = IC )
Q Apply KVL at collector to emitter,
V − VCE 3 − 0.2 VCE = VCC – ICRC –IERE (IC=IE)
IC = CC = = 2.8mA
RC 1kΩ = 5 –1mA (2.2 + 0.3)
I I 2.8mA = 5– 2.5
β = C then, I B = C = = 56µA = 2.5V
IB β 50
159. For an npn transistor connected as shown in
IC the figure, VBE = 0.7 volts. Given that reverse
Q Saturation condition - IB ≥ satisfy.
β saturation current of the junction at room
temperature 300°K is 10–13 A, the emitter
158. Assuming that the β of the transistor is current is
extremely large and VBE = 0.7 V, IC and VCE in
the circuit shown in the figure are

(a) 30 mA (b) 39 mA
(c) 49 mA (d) 20 mA
GATE-2005
(a) IC = 1 mA, VCE = 4.7 V
Ans. (c) : Given,
(b) IC = 0.5 mA, VCE = 3.75 V
(c) IC = 1 mA, VCE = 2.5 V VBE = 0.7
(d) IC = 0.5 mA, VCE = 3.9 V
GATE-2004
Ans. (c) : Given,

Reverse saturation current

IS = 10–13A (Room temp. At 300ºk)
VT =26mV (T = 300ºk)
 kT 
 Where VT = = 26mV 
β = Very large  q 
Transistor acting as forward bias,
VBE = 0.7V
Q Apply voltage divider point B, I E = IS ( e VBE / ηVT − 1) (where η=1)
5 ×1 5  0.7 
VB = = = 1V = 10−13  e1× 26mV − 1
1+ 4 5
 
Q Apply KVL at base to emitter,
IE = 49mA
I E R E = VB − VBE
160. The circuit using a BJT with β = 50 and VBE
1 − 0.7 = 0.7 V is shown in the figure. The base current
IE = = 1mA
300Ω IB and collector voltage VC are respectively

Analog Electronics 278 YCT

 Ans. (b) : Given,
β = 50
Emitter injection efficiency =0.995
β
Qα =
1+ β
( α = γ*β* )
γ* .β* =
50
51
( γ* = Emitter injection efficiency )
(a) 43 µA and 11.4 volts (b) 40 µA and 16 volts 50
β* = = 0.9852
(c) 45 µA and 11 volts (d) 50 µA and 10 volts 51× 0.995
GATE-2005 (β* = Base transport factor )
Ans. (b) : Given,
162. For the BJT circuit shown, assume that the β of
β = 50, VBE = 0.7V the transistor is very large and VBE = 0.7 V.
Q D.C. signal f = 0 The mode of operation of the BJT is
then C act as open circuit.
IE = IC +IB
= βIB + I B
IE = ( β + 1) IB

(a) cut-off (b) saturation

(c) normal active (d) reverse active
GATE-2007
Ans. (b) : Given,
β = Very large
I IC
IB = C = ≅0
β Very l arg e
Apply KVL at base,
VBE = 0.7V
VCC = IB R1 + VBE + (1 + β) I B R E ( IE = (β + 1)IB )
20 = I B × 430kΩ + 0.7 + 51× I B × 1kΩ
20 − 0.7
IB =
(430 + 51) × 103
19.3
=
481× 103
Q During cut-off region,
= 0.401mA
I B = 0, IC = 0
= 40 µA
Q Condition for saturation I B ≥ I B(min)
I
Q Current gain ( β ) = C ⇒ IC = I Bβ IC ≥ IC(sat)
IB
VCE(sat ) = 0.2V(si) and 0.1(Ge)
IC = 40µA × 50
Step 1→IC(sat)=
IC = 2mA
10 − VCE (sat) 10 − 0.2 9.8
Apply KVL at collector loop, = = mA = 0.891mA
VCE = VCC − R 2 IC (10 + 1) × 103 11× 103 11
Step 2→ IC(expected)
VCE = 20 − 2 ×103 × 2 × 10 −3
2 − VBE(sat ) − IC(exp) × 1× 103 = 0
VCE = 16V
161. The DC current gain (β) of a BJT is 50. 2 − 0.8 − IC(exp) ×103 = 0
Assuming that the emitter injection efficiency is IC(exp) = 1.2mA
0.995, the base transport factor is
(a) 0.980 (b) 0.985 then from step-1 and step-2
(c) 0.990 (d) 0.995 IC(exp ected) > IC(sat )
GATE-2007 So, transistor is in saturation region.

Analog Electronics 279 YCT

163. A small signal source vi(f) = A cos 20 t + B sin So,
106 t is applied to a transistor amplifier as A Cos 20t is suppressed at output.
shown below. The transistor has β = 150 and hie
And for ω2 = 106 ,
= 3 kΩ. Which expression best approximates
v0(t) ? 1 1
then X C2 = = 6 = 10Ω
ω2 C 10 × 100 × 10−9
X C2 = Very small (act as short circuit).
So,
B sin 106 t will appeared at output.
∴ From equation (i),
V0 (t) = −150Bsin106 t
(a)v0(t) = –1500(A cos 20t + B sin 106t) 164. In the silicon BJT circuit shown below, assume
6 that the emitter area of transistor Q1 is half
(b)v0(t) = –150(A cos 20t + B sin 10 t)
(c)v0(t) = –1500 B sin 106t that of transistor Q2.
(d)v0(t) = –150 B sin 106t
GATE-2009
Ans. (d) : Given,
Vi (f ) = A coas 20t + Bsin106 t
β = 150
hie = 3kΩ
The value of current Io is approximately
Q Ac analysis, CE = 10µF (given) as a short circuit and
emitter resistance can be removed (AC analysis). (a) 0.5 mA (b) 2 mA
Q Common emitter amplifier without RE:(No feedback) (c) 9.3 mA (d) 15 mA
A1 = h fe = −β = −150 GATE-2010
Zi = h ie = 3kΩ Ans. (b) : Given, Assume area (emitter) of transistor Q1
is half that of transistor Q2. It is a current mirror circuit
R 'L in which the output current is a mirror image of the
A V = A1.
Zi input current if both the transistor are identical.

Apply KVL Transistor Q1 (Transistor act as a Diode)

− I1R − VBE = −10
−10 + 0.7
R 'L 3k − I1 = = 1mA
A V = A1 = −150 × = −150 9.3
Zi 3k
I1 = 1mA = Isi e VBE / ηVT .....(i)
V0 (t) = A V Vin (t) = −150[A cos 20t + Bsin106 t] ....(i)
Q I0 = IC2 = I E2 ≅ IS2 .e VBE / ηVT ....(ii)
ω1 = 20
From equation (i) and (ii)
ω2 = 106
I0 = IS2 .eVBE / ηVT = 2ISi e VBE / ηVT = 2I1 = 2 ×1
then,
I0 = 2mA
1  ω
XC = f =  165. The amplifier circuit shown below uses a
2πfc  2 π
silicon transistor. The capacitance CC and CE
for ω1 = 20,
can be assumed to be short at signal frequency
2π 1 and the effect of output resistance r0 can be
X C1 = = = 500000Ω
2π× ω1C 20 ×100 ×10−9 ignored. If CE is disconnected from the circuit,
which one of the following statements is
X C1 = very large TRUE?

Analog Electronics 280 YCT

 Ans. (a) : Given, C1 and C2 are very large and shorts at
V0
the input frequency The gain magnitude at 10 M
Vi
rad/s.

(a) The input resistance Ri increases and the

magnitude of voltage gain Av decreases
(b) The input resistance Ri decreases and the
magnitude of voltage gain Av increases
(c) Both input resistance Ri and the magnitude of Q C1 and C2 act as a short circuit and RE can be
voltage gain Av decrease removed.
(d) Both input resistance Ri and the magnitude of Q AC equivalent,
voltage gain Av increase ZL = ZP || RL
GATE-2010 So, V0 = ic (ZL)
Ans. (a) : Given, CE is disconnected from the circuit.
V0 = −i c [ ZP || R L ] .....(i)
Without considering the emitter capacitor-
Where ZP = Parallel RLC circuit.

Q Voltage across the base-emitter junction,

V ×r 1 1
VBE = s π fr = = rad / sec
R E + rπ 2 LC × π LC
So, VBE is less than the above case where the emitter 1
capacitor is not considered gain is reduced. fr = = 10M rad / s
Input impedance when capacitor is removed, 10 × 10 × 1× 10−9
−6

RB From equation (i)

Ri = .....(i)
R B + rπ V0 = −i c (ZP || R L ) (where ZP will be maximum)
So, Input resistance is increased. V0 = icRL = Maximum output and maximum gain
Therefore, capacitor is not considered then input at resonance frequency.
resistance is increased but gain will be reduced to 167. For the BJT Q1 in the circuit shown below, β =
emitter resistance.
∞, VBEon = 0.7 V, VCEsat = 0.7 V. The switch is
166. In the circuit shown below, capacitors C1 and initially closed. At time t = 0, the switch is
C2 are very large and shorts at the input opened. The time t at which Q1 leaves the active
frequency vi is a small input. The gain
region is
magnitude | v0/vi | at 10 M rad/s is

(a) Maximum (b) Minimum (a) 10 ms (b) 25 ms

(c) Unity (d) Zero (c) 50 ms (d) 100 ms
GATE-2011 GATE-2012
Analog Electronics 281 YCT
Ans. (c) : Given,
β = ∞, VBEon = 0.7, VCEsat = 0.7V

So, IE = IB +IC = 0+IC

Q When transistor are active region, IE = 1mA.
Apply KVL at Base to emitter loop, Q VE = I E R E = 1× 10 −3 × 500
− VB − VBE − I E R E = −VCC VE = 0.5V
−5 − 0.7 − 4.3k × I E = −10 And VBE +VE = 0.7 + 0.5
VR 2 = 1.2V
10 − 5.7 4.3
IE = = = 1mA From voltage divider rule,
4.3 4.3
R2
We know that, IE = IC + I1 VR 2 = VCC
R1 + R 2
I1 = 1 − 0.5 = 0.5mA
R2
Q When transistor are saturation region, Apply KVL at 1.2 = 3 ×
60k + R 2
collector to emitter loop,
72 + 1.2R2 = 3R2
VCC − VCEsat − IE R E = − VCC
72
VC − 0.7 − 4.3 × 1 = −10 R2 = = 40Ω
1.8
VC = –5V 169. A good current buffer has
Q q = CVC = −5 ×10 −6 × 5V (a) Low input impedance and low output
–6 impedance
= –25×10
(b) Low input impedance and high output
and q = i × t impedance
At time t = 0, the switch is opened, that t = (0–t) upto, (c) High input impedance and low output
I1 (0 − t) − 25 × 10 −6 impedance
(d) High input impedance and high output
−I1 t = −25 ×10−6 impedance
t = 25 ×10 −6 / 0.5 ×10 −3 ⇒ t = 50mSec GATE-2014, Set-I
Punjab PSC Poly. Lect. - 20/08/2017
168. In the circuit shown below, the silicon npn
Ans. (b) : For a good current buffer has-
transistor Q has a very high value of β. The • Unity current gain
required value of R2 in kΩ to produce IC = 1 • Low input impedance, Ideal R = 0
i
mA is • High output Impedance, Ideal R0 = ∞
• Very large voltage gain.
For a good voltage buffer-
• Unity voltage gain.
• Very large current gain
• High input impedance, Ideal, Ri = ∞
• Low output impedance, Ideal, R0 = 0
170. In the circuit shown, the silicon BJT has β = 50.
(a) 20 (b) 30 Assume VBE = 0.7 V and VCE(sat) = 0.2 V. Which
one of the following statements is correct?
(c) 40 (d) 50
GATE-2013
Ans. (c) : Given,
β = Very high then
I B ≅ 0(ignored)
IC =1mA

Analog Electronics 282 YCT

 (a) For RC = 1 kΩ, the BJT operates in the
V0 −g m R i'
saturation region =
(b) For RC = 3 kΩ, the BJT operates in the Vi 1 + g m R E
saturation region V0 −g m R i'
(c) For RC = 20 kΩ, the BJT operates in the cut- A V = = → R E↑→ A V ↓, R i ↑
Vi 1 + g m R E
off region
(d) For RC = 20 kΩ, the BJT operates in the Q R i = βre + (1 + β) R E
linear region AR
GATE-2014 Set-III AV = I L
Ri
Ans. (b) : Given,
⇒ If the emitter is not by passed voltage gain decreases
β = 50 VCE(sat ) = 0.2V and input resistance increases.
VBE = 0.7 172. Consider the common-collector amplifier in the
Assume the transistor is in active region, figure (bias circuitry ensures that the transistor
operates in forward active region, but has been
omitted for simplicity). Let IC be the collector
current, VBE be the base-emitter voltage and VT
be the thermal voltage. Also, gm and ro are the
small-signal trans-conductance and output
resistance of the transistor, respectively. Which
one of the following conditions ensures a nearly
constant small signal voltage gain for a wide
range of values of RE?
Apply KVL in Base to emitter loop,
VB − VBE = IB R B
5 − 0.7 4.3
IB = = × 10−3 = 0.086mA
50kΩ 50
Q Isolator current, IC = β IB = 4.3mA .....(i)
Q Saturation condition, β IB ≥ IC(sat ) .....(ii)
(a) gm RE << 1 (b) IC RE >> VT
Q KVL across CE loop, (c) gm ro >> 1 (d) VBE >> VT
10 − IC(sat ) .R C − VCE(sat ) = 0 GATE-2014 Set-IV
10 − 0.2 9.8 Ans. (b) : Transistor operates in forward bias region,
IC(sat) = = Assume,
RC RC
Assume, (According to option)
9.8
(i) R C = 1kΩ, IC(sat) = = 9.8mA .....(iii)
1KΩ
9.8
(ii) R C = 3kΩ, IC(sat ) = = 3.266 ....(iv)
3
From equation i, ii, iii and (iv),
β IB ≥ IC(sat ) → BJT operate in saturation
gmVbe >>ib
region for R = 3kΩ. Q Voltage gain
171. If the emitter resistance in a common-emitter V g V .R
voltage amplifier is not by passed, it will A V = 0 = m be B
(a) Reduce both the voltage gain and the input V i Vbe + V0
impedance g m R E Vbe
(b) Reduce the voltage gain and increase the AV =
Vbe + g m R e Vbe
input impedance
(c) Increase the voltage gain and reduce the input gmR E
= ≅1
impedance 1 + gm R E
(d) Increase both the voltage gain and the input Q g R >> 1 then
m E
impedance
UPPSC ITI Principal/Asstt. Director-09.01.2022 IC R E
>> 1 [T-model equivalent circuit]
GATE-2014 Set-IV VT
Ans. (b) : If the emitter in a common - emitter voltage
IC R E >> VT
amplifier is not by passed then voltage gain,
Analog Electronics 283 YCT
173. An increase in the base recombination of a BJT then, capacitor act as a short circuit.
increase
(a) The common emitter dc current gain β
(b) The breakdown voltage BVCEO
(c) The unity-gain cut-off frequency fT
(d) The trans-conductance gm
GATE-2014 Set-II
Ans. (b) : An increase in recombination will cause a
decrease in ICBO which ICEO will decrease.
ICEO = (1 + β) ICBO
But power rating constant so,
Q Emitter current
Break down voltage ↑→ ICEO ↓
10 − 0.7
174. The Ebers-Moll model of a BJT is valid IE = = 0.465mA
20
(a) Only in a active mode
Q Transconductance,
(b) Only in active and saturation modes
I 0.465
(c) Only in active and cut-off modes gm = E = = 17.88mA / V
(d) In active, saturation and cut-off modes VT 26
GATE-2016 Set-II V0
Ans. (d) : It is used for BJT, can be used in forward or Q Voltage gain A V = V = −g m k(R C || R L )
i
reverse active mode of operation, as well as in both
saturation and cut-off mode.  10 × 10 
A V = −17.88mA /×  
Ebers-moll equation for the emitter current  10 + 10 
( )
IE = a11 ( e VE / VT − 1) + a12 e VC / VT − 1 = –17.88×10–3×5×103
= –89.42
kT |AV| = –89.42
Where, VT = (Thermal voltage)
q 176. The load impedance ZL of common emitter
VT =26 mV (Room temperature) amplifier has R and L in series. The phase
175. For the BJT in the amplifier shown below. VBE difference between output and input will be
= 0.7 V, kT/q = 26 mV. Assume the BJT output (a) 180º
resistance (ro) is very high and the base current (b) More than 180º but less than 270º
is negligible. The capacitors are also assumed (c) 0º
to be short circuited at signal frequencies. The (d) More than 90º but less than 180º
input Vi is direct coupled. The low frequency Punjab PSC Poly. Lect. 20.08.2017
gain Vo/Vi of the amplifier is Ans. (b) : The load impedance ZL of common emitter
amplifier has R and L in series. The phase difference
between output and input will be more than 180º but
less than 270º.
177. The self bias is used in amplifiers to
(a) reduce the cost of the circuit
(b) reduce the dc base current
(c) make the operating point almost independent
of β
(d) limit the input ac signal going to the base
(a) –178.85 (b) –256.42 terminal
(c) –128.21 (d) –89.42 TSPSC Manager (Engg.) - 2015
GATE-2020
Ans. (c) : Self bias provides stable IC collector current
Ans. (d) : Given, irrespective of variation in temperature of β.
VBE = 0.7V
178. A biasing circuit has a stability factor of 40. If
kT due to temperature change, ICO changes by 1
VT = 26mV =
q µA. Then IC will change by
BJT output resistance (r0) = Very high (a) 20 µA (b) 40 µA
IB = Negligible. (c) 80 µA (d) 10 µA
for AC analysis, f = ∞ , XC = 0 Nagaland PSC (Degree) 2018, Paper-II

Analog Electronics 284 YCT

Ans. (b) : Given S =40, Ico = 1µA 181. A given transistor has an α of 0.98. If the
device is connected with its emitter grounded,
∂Ic
Stability factor (s) = What will be the change in the collector current
∂Ico for a change of 0.2mA in the base current ?
∆I c (a) .98mA (b) 9.8mA
∴ 40 =
1µA (c) 98mA (d) .0 98mA
∴ ∆Ic = 40 µA TNPSC AE- 2019
179. What is the thermal runway in a bipolar Ans. (b) : Given,
junction transistor biased in active region due α = 0.98
to? I B = 0.2mA
(a) Heating of the transistor emitter region.
α 0.98
(b) Changes in β which increases with β= = = 49
temperature. 1 − α 1 − 0.98
(c) Base emitter voltage VBE which decreases I
β= C
with rise in temperature. IB
(d) Increase in reverse collector-base saturation IC = βI B = 49 × 0.2
current due to rise in internal device
temperature = 9.8 mA
Nagaland PSC (Degree) 2018, Paper-II 182. A certain transistor has αdc of 0.98 and a
Ans. (d) : Thermal runaway occurs in BJT due to collector leakage current Ico of 1µA. When
increase in reverse collector-base saturation current due IE = 1mA, the collector and base currents will
to rise in internal device temperature. be
180. In the base biased transistor circuit, the (a) Ic = 0.981mA and IB = 0.019mA
junction temperature may vary from 250C to (b) Ic = 0.981µA and IB = 0.019µA
750C. If β increase from 100 to 150 with raising (c) Ic =9.81mA and IB = 0.19mA
temperature, percentage change in VCE point (d) Ic = 9.81µA and IB = 0.19µA
will be TNPSC AE- 2019
Ans. (a) : Given,
αdc = 0.98
Ico= 1 µ A and IE=1mA
Ic = .αIE + ICEO
= 0.98 × 1× 10-3 + 10-6
Ic= .0.98 mA
(a) 40% (b) -44.57% IB = (1-α) IE – ICEO
(c) -46.57% (d) -48%
= (1 – 0.98) 1×10-3 -1×10-6
TNPSC AE- 2019
= 0.02×10-3 – 1×10-6
V − VBE 12 − 0.7 = 20 × 10–6 – 1×10-6
Ans. (b) : I B = CC = = 0.113mA
RB 100 × 10 3
IB = 19×10-6 = 0.019 mA
IC = β IB = 100 × ( 0.113) = 11.3mA 183. The transistor shown in figure in specified to
have β in the range of 50 to 150. Find the vlaue
VCE = VCC − IC R C = 12 − (11.3 × 10−3 × 500 )
of RB that results in saturation with an
= 5.35V overdrive factor of atleast 10.
0
At 75 C
I B = 0.113mA
IC = β IB = 150 × 0.113 = 16.95mA
VCE = 12 − (16.95 × 10−3 × 500 )
= 3.32V (a) 2.2 K Ω
16.75 − 11.3 (b) 3.2 K Ω
∆I C = ×100 = 50% ( Increase )
11.3 (c) 3.4 K Ω
3.52 − 6.35 (d) 2.8 K Ω
∆VCE = × 100 = −44.57% ( decrease )
6.35 TNPSC AE- 2019
Analog Electronics 285 YCT
Ans. (a) : 187. The circuit shown below is a–

Given,
VC = VCE = 0.2V
(a) Constant voltage source
10 − 0.2
ICSat = (b) Constant current source
1 (c) Common emitter
= 9.8 mA (d) Oscillator
To saturate the transistor with the lowest B, Nagaland PSC CTSE- 2015, Paper-II
I 9.8 Ans. (a) :
I B = Csat = = 0.196mA
βmin 50
For an overdrive factor of 10.
IB = 10× 0.196 = 1.96 mA
5 − 0.7
= 1.96
RB
5K × 5K
4.3 RB = = 2.5 KΩ
RB = = 2.2KΩ 10K 2
1.96
10 × 5K
184. Transistors ratings symbols using capital letter VB = = 5V
and with subscripts also in capital letters 10K 2
denotes Given circuit is common constant voltage source.
(a) DC parameters (b) AC parameters 188. Current stability of a CC amplifier can be
(c) Effective values (d) Time varying increased by
values (a) Reducing both emitter and base resistance
(b) Increasing both emitter and base resistance
Nagaland PSC- 2018, Diploma Paper-II (c) Reducing emitter resistance and increasing
Ans. (a) : DC parameter of transistor always represent base resistance
in capital letter used for DC analysis of transistor. For (d) Increasing emitter resistance and decreasing
ac analysis all parameter represent in small letters. base resistance
185. CC amplifier has (e) Keeping emitter resistance and base
resistance to same value
(a) High Ri and high Ro (b) Low Ri and low Ro
CGPSC SO 14.02.2016
(c) Low Ri and high Ro (d) High Ri and low Ro
Ans. (d) : Current stability factor of CC amplifier
Nagaland PSC- 2018, Diploma Paper-II
R R E = emitter resistance
Ans. (d) : For common collector amplifier Rin (input S= E
RB R B = base resistance
impedance) ⇒ High
Rout (output impedance) ⇒ Low. If we increase the emitter resistance and decreasing base
resistance current stability factor increased.
186. In class B amplifier, with sinusoidal input
189. Which of the following statements are correct
signal, the output current flows for for basic transistor amplifier configuration?
(a) Half the cycle (a) CB amplifier has low input impedance and a
(b) Full cycle low current gain
(c) Less than half cycle (b) CC amplifier has low output impedance and a
(d) More than half cycle low current gain
(c) CE amplifier has very poor voltage gain but
Nagaland PSC- 2018, Diploma Paper-II very high input impedance
Ans. (a) : In a class a amplifier with a sinusoidal input (d) The current gain of CB amplifier is higher
signal the output current flow for full cycle i.e. 360º than the current gain of CC amplifier
where as class B amplifier with a sinusoidal input (e) CC amplifier has highest voltage gain
signal, the current flow for 180º half cycle. CGPSC SO 14.02.2016
Analog Electronics 286 YCT
Ans. (a) : The basic transistor amplifier configuration is 192. In the circuit shown below, if RC = 10 kΩ, RL =
common base CB. 10 kΩ, β = 100, input signal voltage is 1mV
r.m.s. The output voltage is:
β
Which has current gain α = very low.
β +1

input impedance Zin = R E || re very low.

190. To set the operating point at 2V, 1mA by
biasing a silicon transistor with collector
feedback resistor RB. If β = 100, the value of
RB is : (a) 100 V (b) 150 V
(c) 250 V (d) 350 V
(e) 200 mV
CGPSC SO 14.02.2016
Ans. (e) : Voltage gain = (RC || RL) β =(10 || 2.5) × 100=
Vo
= 200
Vin
Vo = 200 × Vin = 200 mV
(a) 130 Ω (b) 13 KΩ Vo = 200mV
(c) 130 KΩ (d) 13 Ω 193. When a a.c. signal is applied to an amplifier,
(e) 200 KΩ the operating point ______?
CGPSC SO 14.02.2016 (a) moves along d.c. load line
Ans. (a) : Given, (b) moves along a.c. load line
(c) moves along both d.c. and a.c. load lines
IC = 1mA β = 100 VCE = 2V VBE = 0.7V
(d) does not moves at all
I 1
IB = C = = 0.01 mA (e) shifts along dc load line by peak amplitude of
β 100 a.c. signal
VCE = VBE + VCB CGPSC SO 14.02.2016
2 = 0.7 + VCB VCB = 1.3V Ans. (b) : When an AC signal applied to an amplifier
the output will vary from its dc bias operating voltage
V 1.3 and current the operating point moves along a.c. load
R B = CB = = 130Ω
IB 0.01 line.
194. The main use of an emitter follower is as:
191. In the circuit shown below, β = 60 and input
(a) Amplifier
resistance Rin = 1 kΩ.
(b) Low input impedance circuit
(c) Buffer stage
(d) Follower of base signal
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Ans. (c) : Emitter follower is a negative current
feedback circuit.
Emitter follower configuration, also known as common
What is the voltage gain? collector, provides high input impedance and low output
(a) 12 (b) 24 impedance.
(c) 36 (d) 48 So they are used for the purpose of impedance
(e) 60 matching. The main use of an emitter follower is as
CGPSC SO 14.02.2016 buffer stage.
Ans. (b) : Given, 195. In a transistor switch application, the operating
β = 50 Rin = 1kΩ Rc = 2kΩ point moves between following region:
(a) Cut-off and saturation
Vo  R L × R c   0.5 × 2  (b) Cut-off and active
= ×β =   × 60
Vin  R L + R c   0.5 + 2  (c) Active and saturation
(d) None of the above
Vo = 24
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I

Analog Electronics 287 YCT

 Ans. (a)

→ This configuration is used for impedance matching

i.e. driving a low impedance load from a high
196. From measurement of the rise time of the impedance source.
output pulse of an amplifier whose input is a → This configuration circuit is such less temperature
small amplitude square wave, one can estimate dependent.
the following parameter of the amplifier.
199. The dc current gain in common collector
(a) Gain-bandwidth product
configuration is given by;
(b) Upper-3-dB frequency
(a) β + 1 (b) β
(c) Lower-3-dB frequency
(d) Slew-Rate (c) α + 1 (d) α
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Gate-1998 Ans. (a) : Common collector configuration, also known
Ans. (b) : as emitter follower provides high input impedance and
low output impedance.
I 1
γ = E = 1+ β =
IB 1– α
200. For a common emitter. BJT configuration with
collector terminal resistance R, the slope of the
D.C. load line can be given by:
(a) 1 (b) R
upper-3-dB frequency can estimate from measurement
(c) 1/R (d) –1/R
of the rise time of the output pulse of an amplifier
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
whose input is a small amplitude square wave.
Ans. (d) : VCC = IC R L + VCE
197. The CE amplifier circuits are preferred over
CB amplifier circuit because they have: V V
(a) Larger amplification factor ∴ IC = CC – CE
RL RL
(b) Lower amplification factor (i) When
(c) High input resistance and low output
IC = 0 , VCE=VCC
resistance
(d) None of the above Cut-off point A
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (ii) V
VCE=0, IC= CC
Ans. (a) : CE amplifier- This transistor configuration RL
is probably the most widely used. The circuit provides → Saturation point B
a medium input and output impedance levels. Both Slope of load line AB = –1/RL
current and voltage gain can be described as medium,
but the output is the inverse of the input i.e. 180 0 201. The maximum peak to peak output voltage
phase change. The provides a good overall swing is obtained when Q point of a circuit is
performance and as such it is often thought of as the located:
most widely used configuration or can be said as that (a) Center of the load line
we get a good amplification factor here in CE (b) Near saturation point
amplifier compared to CB amplifier. (c) Near cut off point
198. The following transistor configuration circuit is (d) Any point on the load line
much less temperature dependent: OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
(a) Common base (b) Common emitter Ans. (a) : The Q-point is located at the centre of the
load line. In this condition, we get the maximum
(c) Common collector (d) None of these
possible output signal. The point gives the optimum Q-
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
point. The maximum undistorted signal= 2 VCEQ .
Ans. (c) : cc configuration- It the Q-point is located near saturation point, The
IE maximum negative swing= VCEQ
γ=
IB 202. The d.c. collector current in a BJT is Ic=1 mA.
If thermal voltage at room temperatures given
1
γ = 1+ β = as 25 mV and β=100, the value of small single
1– α parameter gm is:

Analog Electronics 288 YCT

 (a) 0.4 mA/V (b) 0.04 mA/V 205. If the α value of a transistor changes 0.5%
(c) 4A/V (d) 40 mA/V from its nominal value of 0.9, the % change in
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I β will be
Ans. (d) : IC=1 mA (a) 0% (b) 2.5%
VT=25 mV (c) 5% (d) 7.5%
β=100 Sikkim PSC SI (Mains)-2018
I Ans. (c) : α1 = 0.9
transconductance (gm) = c
VT α 0.9
β1 = 1 = =9
1× 10 –3 1 − α 1 − .9
= Change α 2 = 0.9 × 0.005 +0.9
25 × 10–3
gm = 40 mA/V = 0.0045 + 0.9
α 2 = 0.9045
203. If α for the BJT lies between 0.9 to 0.98, the
corresponding range for β is: α2 0.9045
β2 = = = 9.47
(a) 9 to 98 (b) 9 to 49 1 − α 2 1 − 0.9045
(c) 50 to 100 (d) 90 to 98 β = 9.47
2
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
β −β
Ans. (b) : Given Change % β = 2 1 ×100
α = 0.90 to 0.98 β1
α 0.90 9.47 − 9
β= = = × 100
1 – α 1 – 0.90 9
0.90 0.47
β= =9 = × 100
0.1 9
0.98 0.98 β = 5.2%
β= = = 49
1 – 0.98 0.02 206. In the case of small BJT model with common
204. The amplifier circuit shown below uses a emitter, the collector current ic is 1.3 mA, when
silicon transistor. The capacitors CC and CE the collector-emitter voltage is Vce of 2.6 V. The
can be assumed to be short at signal frequency output conductance of the circuit is.
and the effect of output resistance r0 can be (a) 2.0 mΩ (b) 2.0 m
ignored. If CE is disconnected from the circuit, (c) 0.5 mΩ (d) 0.5 m
which one of the following statements is Sikkim PSC SI (Mains)-2018
TRUE? Ans. (d) : The conductance of an amplifier is defined as
the ratio of the collector to emitter voltage to the
collector current of the BJT, i.e.
I
g0 = c
Vce
Ic = Collector current
Vce = Collector to emitter voltage
(a) The input resistance Ri increases and voltage 1.3
gain Ai decreases g0 = = 0.5m℧
2.6
(b) The input resistance Ri decreases and voltage
gain Ai increases 207. In the case of BJT amplifier, bias stability is
achieved by
(c) Both input resistance Ri and voltage gain Av
(a) Keeping the base current constant
decreases
(b) Charging the base current in order to keep IC
(d) Both input resistance Ri and voltage gain Av
and VCE constant
increases
(c) Keeping the temperature constant
NIELIT Scientists- 2017
(d) Keeping the temperature of base current
Ans. (a) : Input Resistance- constant
rin = RB β re Nagaland PSC CTSE (Degree)-2017, Paper-II
rin ≈ βre Ans. (d) : The stabilization of operating point is very
Voltage gain, important to get the distortion free out. It is possible to
r –
r –
r – get stabilized operating point by keeping the temperature
Av = β ⋅ 0– = β 0 = 0 and base current so, stabilization can be achieved by
rin βre re keeping temperature and base current constant.
Analog Electronics 289 YCT
208. The voltage divider bias circuit is used in 211. The transistor in the circuit of the given figure
amplifiers quit often because it is operating
(a) Limits the ac signal going to the base
(b) Makes the operating point almost independent
of β
(c) Reduce the dc base current
(d) Reduces the cost of the circuit
Nagaland PSC CTSE (Degree)-2017, Paper-II
Ans. (b) : The voltage divider bias circuit is used in
amplifiers quite often because it makes the operating
point almost independent of β. (a) In the cut-off region
(b) In the active region
209. In voltage amplifiers the load resistance should
be (c) In the saturation region
(a) As large as possible (d) Either in the active or the saturation region
(b) As small as possible Nagaland PSC CTSE (Degree)-2017, Paper-II
(c) Equal to output impedance Ans. (c) :
(d) Equal to input impedance
Nagaland PSC CTSE (Degree)-2017, Paper-II
Ans. (a) : • A voltage amplifier is any simple circuit
that produces a large voltage at its output and also that
amount of power coming out from the circuit.
• In a voltage amplifier the load resistance should be as
a large as possible.
210. In the amplifier circuit shown in the figure, the
values of R1 and R2 are such that the transistor Assume, VCE = 0.2V, hFE= β = 30
is operating at VCE = 3V and IC = 1.5 mA when Apply KVL at the collector side,
its β is 150. For a transistor with β of 200, the
5 − 0.2
operating point (VCE, IC) is IC = = 0.96mA
5
I 0.96
Q IB = C = = 0.032mA …………….(i)
β 30
5 − 0.7 4.3
| IB |= = = 0.043mA …………..(ii)
100k 100k
(a) (2 V, 2 mA) (b) (3 V, 2 mA) From equation (i) and (ii)
(c) (4 V, 2 mA) (d) (2 V, 1 mA) 0.043 > 0.032mA
Nagaland PSC CTSE (Degree)-2017, Paper-II IC
Ans. (a) : We know that, Given that, VCC = 6V IB >
β
VCC = IC R C + VCE ∵ RC = R 2 VCE = 3 Hence, transistor is in the saturation region.
6 = 1.5 × R 2 + 3 IC = 1.5mA 212. In common emitter BJT amplifier, the
R 2 = 2kΩ β = 150 maximum usable supply voltage is limited by
(a) Avalanche breakdown of Base-Emitter
IC 1.5
IB = = = 0.01mA junction
β 150
(b) Collector-Base breakdown voltage with
When β = 200 emitter open (BVCBO)
Now (c) Collector-Emitter breakdown voltage with
IC = β × I B base open (BVCBO)
= 200 × 0.01 (d) Zener breakdown voltage of the Emitter–Base
IC = 2mA junction
VCC = IC R 2 + VCE Nagaland PSC CTSE (Degree)-2017, Paper-II
6 = 2 × 2 + VCE Ans. (c) : In common emitter BJT amplifier the
maximum usable supply voltage is limited by collector-
VCE = 2V emitter breakdown voltage with base open (BVCBO).

Analog Electronics 290 YCT

213. In a common emitter amplifier, the un
bypassed emitter resistance provides
(a) Voltage shunt feedback
(b) Current series feedback
(c) Negative voltage feedback
(d) Positive current feedback
Nagaland PSC CTSE (Degree)-2017, Paper-II
Ans. (c) : In a common emitter unbypassed resister
provides negative voltage feedback.
214. The Darlington pair is mainly used for
(a) Impedance matching
I ref I ref
(b) Wideband voltage amplification (a) (b)
 (1 + N)   N 
(c) Power amplification  1 + β(β + 1)   1 + β(β + 1) 
(d) Reducing distortion    
Nagaland PSC CTSE (Degree)-2017, Paper-II βI ref βI ref
(c) (d)
 (1 + N)   N 
 1 + β(β + 1)   1 + β(β + 1) 
Ans. (a) :
   
ISRO Scientist- May, 2017
Ans. (a) : For given figure,
Q R ,Q1 ,Q 2 ......Q N have perfectly equal VBE

I ref = IC +
( N + 1) I B
( β + 1)
 N +1 
I ref = I B  β + 
 β +1 
I ref
IB =
 N +1 
A Darlington pair configuration has high input β + 
impedance and low output impedance so, it is mainly  β +1 
used for impedance matching. Q I0 = βIB
215. IB=10mA, ICEO=150 µA, ICBO= 5µA Find β βI ref
∴ I0 =
(a) 29 (b) 30  N +1 
β + 
(c) 50 (d) 40  β +1 
AAI-2015 I ref
Ans. (a) : ICEO = Reverse leakage current in the or I0 =  N +1 
1 + 
common emitter configuration of BJT when the base is
 β (β + 1) 
open.
ICBO = Reverse leakage current in the common base 217. Match the following :
1. Rectifier a. Power electronics,
configuration of BJT when the emitter is open.
Motor speed control,
Battery charging,
Given that ICBO = 5µA ICEO = 150µA Phase control
from ICEO = (1 + β ) ICBO 2. Transistor b. Rectifiers, Wave
clipper circuits
150 = 5 (1 + β ) 3. SCR c. Amplifier, Switches
So, β = 30 − 1 (a) 1-a, 2-c, 3-b (b) 1-b, 2-a, 3-c
(c) 1-b, 2-c, 3-a (d) 1-c, 2-a, 3-b
β = 29
RRB SSE 21.12.2014, (Green)
216. All transistor in the N output current mirror in Ans. (c) : Diode- rectifier, wave clipper
the figure are matched with a finite gain β and Transistor- Amplifiers , switches
early voltage VA = ∞. The expression for load SCR- power electronics, motor speed control, battery
current is charging, phase control.

Analog Electronics 291 YCT

218. In a NPN transistor, if the base current is 100 (a) 3 µA (b) 56 µA
µA and the current gain, β = 200, the collector (c) 60 µA (d) 140 µA
current will be: BPSC Polytechnic Lecturer-2014
(a) 2 mA (b) 100 mA Ans. (b) :
(c) 10 mA (d) 20 mA
UPPCL AE-05.11.2019
Ans. (d) : For NPN transistor-
IC = β ⋅ I B
IC = 100 ×10 −6 × 200
IC = 20000 × 10−6
VCEsat = 0.2V, β = 50
IC = 20 × 10−3
IB = ?
IC = 20mA
3 − IC − 0.2 = 0
219. Calculate the value of IE for a BJT with I = 2.8 mA
C
α dc = 0.99 and I B = 0.99.
IC = β IB
(a) 8.0 mA (b) 5.0 mA
(c) 4.0 mA (d) 9.9 mA 2.8mA
IB = = 56µA
UPPCL AE-05.11.2019 50
Ans. (c) : For a transistor 222. An npn transistor operated at lc=5mA has a
I E = IB + IC ∵ IC = βI B collector load resistor of 2 kΩ and its emitter is
grounded. The voltage gain of this stage is
I E = IB + βI B about. Where VT = 25 mV(npn)
I E = IB (1 + β ) (a) 100 (b) 400
Given that α = 0.99, I B = 40µA (c) 25 (d) 10
RRB SSE 01.09.2015, Shift-III
0.99
β= = 99 Ans. (b) : Given,
1 − 0.99 IC = 5mA, R L = 2kΩ
I E = ( 99 + 1) × 40µA
VT = 25mV
I E = 4mA I R
Voltage gain = C L
220. Calculate the value of IE for a transistor that VT
has α dc = 0.98 and I B = 100µA.
5 × 10−3 × 2 × 103
(a) 5.0 mA (b) 4.8 mA Voltage gain =
(c) 4.9 mA (d) 6.4 mA 25 × 10−3
Voltage gain = 400
UPPCL AE-05.11.2019
223. For the circuit shown in the below figure, by
Ans. (a) : Given,
assuming β = 100 and VBE = 0.7 V, the best
α 0.98 approximation for the collector current Ic in
α = 0.98 β= =
1-α 1 − 0.98 the active region is
0.98
β= = 49
0.02
I E = (1 + β ) ⋅ I B
I E = 50 × 100µA
I E = 5mA
(a) 2.5 mA (b) 3 mA
221. Assuming VCEsat = 0.2V and β = 50 , the (c) 5 mA (d) 3.5 mA
minimum base current ( I B ) required to drive RRB SSE 02.09.2015, Shift-II
the transistor shown in the figure below to Ans. (a) : Apply KVL base to emitter,
saturation is −12 + IB ×10k + 0.7 + 450 × (1 + β ) IB = 0

Analog Electronics 292 YCT

−11.3 + I B10k + 450I B = 0 12 − 0.7 11.3 11.3 ×10
Ans. (c) : I B = = = = 113 × 10−6
46.450kIB = 11.3 100 × 103 105 105 × 10
= 113 µA
11.3
IB = = 0.024327mA 227. For the silicon transistor shown in the figure
46.45 × 103
IC = 100 × 0.0243 below, the value of IB is

2.53mA
224. A microphone is connected between the base
and the ground of a BJT. A 1kΩ resistance is
connected between the collector VCC. If
Is = 6 ×10–16 A and the peak value of the
microphone signal is 20mV, what is the peak
value of the output signal?
(a) 1.29 ×10–16V (b) 1.29 ×10–6V (a) 26.47 µA (b) 52.94 µA
–12
(c) 1.29 ×10 V (d) 1.29 × 10–14V (c) 13.235 µA (d) 30.11 µA
UPMRC AM - 2020 ISRO Scientist December, 2017
Ans. (c) : Given, Is = 6 × 10−16 A, R C = 1kΩ Ans. (d) :

VBE = 20mV, VT = 26mV

Q In BJT collector current,
IC = ISe VBE / VT
 20×10−3 
 
−16  26×10 
−3
= 6 × 10 e
= 6 × 2.158 × 10−16 Given, VEE = −8V, VCC = 10V
= 1.29 × 10 −15 kVL in base to emitter loop,
Q peak output voltage, − VBE − I E R E + VEE = 0
Vo = IC R C
−0.7 − ( 2.4 ×103 × IE ) + 8 = 0
Vo = 1.29 × 10 −15 × 103
7.3
Vo = 1.295 ×10 −12 V IE = = 3.042 mA
2.4 × 103
225. A transistor has a base current of 200 μA and We know that,
a collector current of 50 mA. Find its β. I E = IB + IC
(a) 200 (b) 150 I E = IB + βI B
(c) 500 (d) 250 −3
NLC GET -24.11.2020 I B = I E = 3.042 × 10 = 30.11µA
Ans. (d) : Given IC = 50mA, I B = 200µA 1+ β 100 + 1
228. As compared to a BJT amplifier, an amplifier
I 50 × 10−3 made using a JEET is likely to have
β= C =
I B 200 × 10−6 (a) very high voltage gain
1000 (b) very high bandwidth
β= = 250 (c) very high voltage swing
4
(d) very high input resistance
226. Determine the base current of the amplifier by
taking the base-emitter junction voltage into BSNL (JTO)-2001
account. Ans. (d) : As compared to a BJT amplifier, an amplifier
made using a JEET is likely to have very high input
resistance.
229. The voltage gain of a common emitter
amplifier is
(a) directly proportional to collector bias current
(b) inversely proportional to collector bias
current
(c) independent of collector bias current
(a) 113 mA (b) 213 µA (d) proportional to square of collector bias
(c) 113 µA (d) 313 µA current
NLC GET -24.11.2020 BSNL (JTO)-2001
Analog Electronics 293 YCT
Ans. (a) : We know that (a) 2.73 Ω (b) 6.83 Ω
V −I R (c) 17 Ω (d) 22.5 Ω
Av = 0 = C L BSNL(JTO)-2009
Vi Vi
Ans. (a) : Given, VCC = 100, β = 9, VCE(sat ) = 1V
So, A v ∝ IC
230. In the circuit shown in figure below, β is the VBE(sat ) = 1.5V
same for both the BJTs. VCC − IC R C − VCE(sat ) = 0
100 − IC × 10 − 1 = 0
10IC = 99
IC = 9.9
IC = βI B
IC 9.9
IB = =
β 9
I2 Q Over drive factor = 2.5
Neglecting early effect, is : 9.9
I1 So, IB = × 2.5 = 2.75A
9
1+ β 1
(a) (b) Now, Vi − IB R B − VBE(sat ) = 0
2 1+ β
9 − 2.75R B − 1.5 = 0
1+ β β
(c) (d) 2.75R B = 7.5
2+β 2+β
BSNL JTO-2009, 2006 R = 7.5 = 2.73Ω
B
DRDO-2009 2.75
Ans. (d) : Q β is same for both BJT because both are 232. For the circuit shown in figure, the transistor
identical transistor. parameters are VBE = 0.7 V , β = 99. If VC is to
Suppose collector current of transistor Q1 is IC1 , be set at 7.5 V, the required value (in kΩ) of RB
is
So IC1 = I 2 (Q β same for both transistor )
IC1 I 2
I1 = IC1 + +
β β
I I
Or I L = I 2 + 2 + 2 (QIC1 = I 2 )
β β
2I2  2
I1 = I2 + = I 2 1 + 
β  β
(a) 172 (b) 136
β+2
I1 =   I2 (c) 100 (d) 82
 β  BSNL(JTO)-2009
I2 β Ans. (a) :
= → [known as current mirror]
I1 β + 2
231. For the power transistor circuit shown in
figure, VCE(sat) = 1.0 V, VBE(sat) = 1.5 V and β=9.
With an overdrive factor of 2.5, the required
resistance RB for saturation is

given VBE = 0.7

β = 99
VC = 7.5V
10 − 7.5
IC =
1k
IC = 2.5 mA

Analog Electronics 294 YCT

IC = βI B 236. Determine the change in collector current,
∆I C due to change in base emitter voltage VBE
2.5 mA
IB = from 25°C to 100°C for a Silicon Transistor in
99 Fixed Bias Configuration having β = 100.
I B = 25 µA
(Consider following variation in Silicon
I E = IC + I B transistor parameters with temperature-At
I E = 2.5mA + 25 µA T=25°C, VBE =0.65 V and At T= 100°C. VBE =
0.5V)
I E = 2.5 + 0.025
I E = 2.525 mA
kVL in collector to base loop-
VC − R B I B − 0.7 − IE ×1kΩ = 0
7.5 − R B × 25µA − 2.5 = 0.7
4.3 = R B × 25µA
4.3
RB =
25 × 10−6 (a) 60µA (b) 30µA
R B = 172 kΩ
(c) 15µA (d) 120µA
233. An NPN Bipolar Transistor with a current gain ISRO Scientist Engg.-2018
of 100 is biased in saturation mode. If the base
Ans.(a):
current is increased by ∆Ib, then :
(a) ∆IC > 100∆Ib (b) ∆IC = 100∆Ib
(c) ∆IC < 100∆Ib (d) ∆IC = ∆Ib
BSNL(JTO)-2002
Ans. (c) : In saturation mode h fe I B ≥ Ics .
So, ∆IC < 100∆Ib.
234. Let β be the short-circuit common-emitter
current gain of a BJT biased in normal active
mode. Let IC be the collector current. Is this β: Given,
(a) a monotonically increasing function of IC? At T = 25ºC, VBE = 0.65V
(b) a monotonically decreasing function of IC? And At T = 100ºC,
(c) Initially an increasing function of IC, which VBE = 0.5V
reaches a plateau and then decreases with β = 100
increasing IC? KVL Apply at input terminal
(d) Independent of IC? VCC = IBRB+VBE
BSNL(JTO)-2002 V − VBE
I B = CC
Ans. (c) : At low injection levels β is degraded by poor RB
emitter injection efficiency. At high currents, β So,
decreases due to excess majority charge in the base. At T = 25ºC,
235. A BJT has α = 0.99, I B = 25 µA and 10 − 0.65
IB =
I CBO = 200nA. The collector current is 250kΩ
(a) Ic = 2.5 mA (b) Ic = 1.5 mA 9.35
= mA
250
(c) Ic = 3.5 mA (d) Ic = 4.5 mA
BSNL (JTO)-2006
( Where, IC = β IB )
α 0.99 9.35
Ans. (a) : β = = = 99 IC1 = 100 ×
1 − α 1 − 0.99 250
IC = βI B + ICEO = 3.74mA
10 − 0.5
= βIB + (1 + β ) ICBO IC2 = 100 ×
250kΩ
= 99 × 25 × 10 −6 + 100 × 200 × 10 −9 = 3.80mA
= 10−6 ( 99 × 25 + 10 × 200 × 10−3 ) So, Change in collector current,
2.5mA ∆IC = IC2 − IC1 = 0.06mA = 60µA

Analog Electronics 295 YCT

237. Common-base current gain of a p-n-p bipolar 239. Which one plot gives the closest resemblance to
transistor is 0.99. The common emitter current the stability factor S(ICO) of emitter bias
gain of the transistor is: R
configuration of BJT with respect to E ? (RE
(a) 101 (b) 0.01 RB
(c) 99 (d) 1.0 is emitter resistance and RB is base resistance)
ISRO Scientist Engg. -2015
Ans. (c) : Given : α = 0.99 , β = ?
α
β=
1− α (a)
0.99
= = 99
1 − 0.99
238. A BJT is having common emitter current gain
100. Considering 10V supply and VBE = 0.7V
what will be the value of RC and RB to set the
quiescent point at IC = 10 mA and VCE = 8V? (b)

(c)

(a) RC = 200Ω , RB = 93 kΩ
(b) RC = 2 kΩ, RB = 100 kΩ
(c) RB = 83 kΩ, RC = 100Ω
(d) RC = 20Ω, RB = 93 kΩ (d)
ISRO Scientist Engg. -2015
Ans. (a) :
ISRO Scientist Engg. -2020
Ans. (b) : For saturation region
VCC
IC (sat) =
RE + RL

β=100, IC = 10mA, VCE = 8V

Applying KVL output circuit,
10–IC RC – VCE = 0
10 − 8
RC =
10 × 10−3
= 200Ω
KVL apply at the input circuit,
10 – IBRB – VBE = 0 Apply KVL
10mA − IB R B − VBE − I E R E + VCC = 0
IB = IC /β =
100 Q I E = IB + IC
= 0.1 mA − IB R B − VBE − ( I B + IC ) R E + VCC = 0
10 − 0.7
RB = − IB ( R B + R E ) − VBE − IC R E + VCC = 0
0.1×10−3
= 93 kΩ Where I B = IC / β, I E = IC

Analog Electronics 296 YCT

 IC R B Ans. (a) :
VCC = + VBE + IC R E
β
Q Stability factor,
1+ β
S= .......(i)
dI
1− β B
dIC
VCC − VBE − IC R E
Q IB =
RB + RE
dI B −R E
= ....(ii)
dIC R B + R E | VA |
From equation (i) and (ii)
r0 = ( VA = early voltage )
IC
1+ β
S= 50 ×103 =
50
βR E
1+ IC
RB + RE
IC = 1mA
If RE = 0, then S = 1+β Note- Increase IC with a increase VCE is called 'Early
R effect'.
If RE >> RB then E → Very large
RB 241. If an emitter follower has VCEO = 6V,
ICQ =200mA, and re= 10Ω, the maximum peak
to peak unclipped output is
(a) 2V (b) 4V
(c) 6V (d) 8V
Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (b) : For an emitter follower effect given that,
VCEO = 6V, ICQ =200mA, and re= 10Ω, the maximum
peak to peak unclipped output 2 × (ICQ × re)
=2×2
= 4V
then, 242. In the circuit shown V1=2.7 V, VBE = 0.7V and
 RE  β >> 1. the gm of the transistor is
(1 + β ) 1 + 
 R B 
Stability factor (S) =
R
1 + (1 + β) E
RB
 RE 
S ≅1  >> 1
R
 B 
240. Output characteristics of a BJT amplifier is
given. Find the minimum collector current (a) 200 m mho (b) 400 m mho
required for r0 = 50 kΩ. (r0 is output (c) 200 ohms (d) 400 ohms
resistance)
Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (b) :

(a) 1 mA (b) 5 mA
(c) 10 mA (d) 100 mA
ISRO Scientist Engg. -2020
Analog Electronics 297 YCT
Applying KVL at input side Ans. (d) :
2
⇒ IE = = 0.01A = Ie
200
I 0.01
So, gm = e = = 0.4 = 400 mA/V
VT 25 × 10−3
= 400 m mho Apply KVL, –10 + ΙB × 106 + 0.7 = 0
243. The value of Rb required to drive the transistor 9.3
in the circuit below into saturation is IB = 6
10
IB = 9.3 µA
245. The self bias provides
(a) stable Q point
(b) large voltage gain
(c) high input impedance
(d) high base current
Mizoram PSC Jr. Grade-2015, Paper-II
Ans. (a) : Voltage divider bias or self bias-
(a) 1 kΩ (b) 110KΩ
(c) 20 KΩ (d) 30 KΩ
Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (c) : Transistor in saturation mode.
VCE = 0, IC = max
VCC 10
IC(sat ) = = = 10mA
R C 1kΩ
IC(sat ) 10mA
IB = = = 500 µA
βDC 20 R1R 2
R in = R B =
This is the value IB necessary to drive the transistor to R1 + R 2
the point of saturation. Any further increase in IB will
R 2 VCC
drive the transistor deeper into saturation but will not Vin =
increases IC. when the transistor is on, VBE = 0.7V the R1 + R 2
voltage across RB is VCE = VCC − IC (R E + R C )
VRB = Vin − VBE = 10 − 0.7 = 9.3V So, operating point not depend upon β. In this kind of
The value of RB needed to allow a IB of 500 µA is- biasing, IC is resistant to the changes in both β as well
as VBE, which results in a stability.
VRB 9.3
RB = = = 0.0186 × 106 246. The configuration of the transistor in the
IB 500 ×10−6
circuit shown is
R B = 18.6 kΩ
RB 20 kΩ
244. In figure what is the base current if VBE = 0.7
V?

(a) 10 µA (b) 10 mA (a) CB (b) CE

(c) 4 mA (d) 9.3 µA (c) CC (d) Both CC and CE
Mizoram PSC Jr. Grade-2015, Paper-II Mizoram PSC IOLM-2010, Paper-II

Analog Electronics 298 YCT

Ans. (b)  
(a) 2 log10  V2 R 1 
 V1 R 2 
 
(b) log10  V2 R 1 
 V1 R 2 
 
(c) 2.3 log10  V2 R 1 
V R
 1 2
 
(d) 4.6 log10  V2 R 1 
Such a common – emitter or grounded – emitter V R
 1 2
configuration
ISRO Scientist- May, 2017
247. Voltage gain of BJT amplifier is
(a) AIRL (b) AI (Ri/RL) Ans. (b) : Given that,
(c) A (RL/Ri) (d) none of these β >> 1
Mizoram PSC AE/SDO 2012-Paper-I VT = 0.026V
Ans. (c) : The voltage gain for BJT
for Transistor Q1 :
RL
A V = A. V
Ri IC1 = 1
R1
248. The cascade amplifier is a multistage IC
configuration of VBE1 = VT ℓn 1
(a) CC-CB (b) CE-CB IS
(c) CB-CC (d) CE-CC for transistor Q 2 :
Nagaland PSC CTSE (Degree)-2017, Paper-II
V
Ans. (d) : CE–CC→ Cascade connection I C2 = 2
R2
CE-CB→ Cascode connection
CC-CC→ Darlington pair IC
VBE 2 = VT ℓn 2
The voltage gain of amplifier can be increased by IS
using cascading connection of individual stages.
output voltage ⇒
The cascade connection is used to obtain high
current gain. 333  V2 R 1 
In a cascade amplifier, the overall gain is equal to V0 = 20 × VT ℓn  R × V 
 2 1 
product of gain of individual amplifier.
For n-amplifier in cascade connection overall 333 V R  V R 
bandwidth will be- = × 0.026ℓn  2 × 1  ≃ log10  2 × 1 
20 R
 2 V1   R 2 V1 
= fH ( 2) − 1
1/ n
250. The gain of a single stage BJT amplifier in the
249. Transistors Q1 and Q2 are identical and β >> 1 Emitter follower configuration, when
in the circuit shown in the figure below. The R c = 22kΩ and R E = 2.2kΩ is:
output voltage is (VT = 0.026 V)
(a) 8.0
(b) 10.0
(c) 5.0
(d) 100.0
UPPCL AE-05.11.2019
Ans. (b) : For emitter follower circuit-
RC
Gain =
RE
22
AV =
2.2
A V = 10

Analog Electronics 299 YCT

 4. The hybrid-pi model is used for:
(iii) Frequency response of BJT (a) analysis of BJT for feedback
amplifiers (b) analysis of BJT for large signal
(c) analysis of BJT at low frequency
(d) analysis of BJT at high frequency
1. For the equivalent circuit of a CE amplifier
UPRVUNL AE -19.07.2021, Shift-II
shown, lower cut off frequency will be Mizoram PSC AE/SDO 2012-Paper-I
Ans. (d) : There are two types of model is used in high
frequency.
(i) Hybrid π-model
(ii) Hybrid T-model
5. The resistance rbb' in the hybrid-pi model is
know as .
b (a) base part resistance
1 1 (b) base speeding resistance
(a) (b)
2πR s C 2πR1C (c) base portion resistance
(d) base spreading resistance
1 1 UPRVUNL AE -19.07.2021, Shift-II
(c) (d)
2π ( R s + R i ) C  RsRi  Ans. (d) : The resistance rbb’ in the hybrid-pi model is
2π  C
 s
R + R i 
know as base spreading resistance, which acts as a
feedback network for the flow of minority carrier
UPPSC ITI Principal/Asstt. Director-09.01.2022 current form emitter to collector.
Ans. (c) : 6. For a transistor, gm = / V T.
(a) IB (b) IE
(c) IC (d) VCE
UPRVUNL AE -19.07.2021, Shift-II
Ans. (c) : gm is the reciprocal of the emitter impedance
VT IC
Re which is , i.e. g m =
Ic VT
1
Lower cut off frequency fc = 7. If rb'e= 1000 ohms and rbb' = 100 ohms for the
2π ( R S + R i ) C hybrid pi-model, what is the value of hie?
2. The coupling capacitor used in CE amplifier (a) 10 ohms (b) 1000000 ohms
(c) 1100 ohms (d) 900 ohms
offers reactance in mid and high
UPRVUNL AE -19.07.2021, Shift-II
frequency region.
Ans. (c) : hybrid Pi model, hie = rb'e + rbb'
(a) high (b) low
= 1000Ω + 100Ω
(c) very high (d) medium
= 1100Ω
UPRVUNL AE -19.07.2021, Shift-II hie = 1100Ω
Ans. (b) : In practical coupling capacitor are large 8. In a hybrid π model, which terminal is NOT
capacitor (µF) because they should offer low accessible?
(negligible) reactance at frequency of AC input. (a) Emitter (b) Collector
3. If 3 amplifiers are connected in cascade and fL (c) Induced base (d) Virtual base
of each is 120 Hz, then fL of cascaded amplifiers UPRVUNL AE -19.07.2021, Shift-II
is: Ans. (d) : hybrid π model is only used for BJT and in
BJT, there are three terminals i.e Emitter, Collector &
(a) 59.98 Hz (b) 253.43 Hz
Base (Induced). It is also called Giacoletto model.
(c) 235.37 Hz (d) 254.33 Hz ∴ Virtual base is not accessible
UPRVUNL AE -19.07.2021, Shift-II 9. An amplifier has midband gain of 100 a lower
Ans. (c) : Given, N = 3 3dB frequency 23Hz. What is the value of
fL of cascaded amplifier frequency at which gain is 99?
(a) 161.41 Hz (b) 2.37 kHz
fL 120
= = (c) 166.89 Hz (d) 19.87 Hz
2 −1
1/ N
21/ 3 − 1 UPRVUNL AE -19.07.2021, Shift-II
120 Ans. (a) : Given-
= = 235.37 Hz
0.5098 A mid = 100, f L = 23Hz, A LF = 99, f = ?

Analog Electronics 300 YCT

 Ans. (b) : In multistage amplifier, there are two types
A mid amplifier i.e. Darlington & Cascade amplifier. In
A LF =
2 Darlington amplifier-
f 
1+  L  rπ + (1 + β1 )rπ 2
f  R 0 = R E ||
(1 + β2 )(1 + β1 )
100
99 = R0 = output Resistance of final stage in Cascade
2
 23  amplifier
1+   R0 = RC = output resistance of final stage.
 f 
2
12. What is the formula of lower cut-off frequency
100  23  of an RC coupled amplifier?
= 1+  
99  f  1 π
(a) f L = (b) f L =
 100 
2
 23 
2 2πRC 2RC
  −1 =   R C
 99   f  (c) f L = (d) f L =
2
2πC 2 πR
1 199  23  UPRVUNL AE -19.07.2021, Shift-II
× = 
99 99  f  Ans. (a) : Voltage gain at low frequencies
199 23 V A vm
= A VL = O =
V 1
99 f I 1 − ω×
14.106 23 CC (R C + R L )
= 1
99 f ∴ ωL =
f = 161.41Hz CC (R C + R L )
10. A transistor amplifier has poles at 1
⇒ fL =
S1 = – 0.00245 × 109 rad/s 2πRC
S2 = – 0.0748 × 109 rad/s (R = RC + RL)
S3 = – 0.670 × 109 rad/s 13. In a single stage amplifier, if hoe = hre = 0, then
S4 = – 4.38 × 109 rad/s output impedance is if Zo=2kΩ||2kΩ.
The upper 3 dB frequency of the amplifier will (a) 2 kΩ (b) infinity
be (c) 1 kΩ (d) 10 kΩ
(a) S1 (b) S1 + S2 + S3 + S4 UPRVUNL AE -19.07.2021, Shift-II
(c) S1+S4 (d) S4 Ans. (c) : If hoe = hre = 0,
IES-1998
Then output impedances Zo = 2kΩ || 2kΩ
Ans. (a) : In a transistor amplifier, when there are many
poles, we consider only the pole which is near the 2× 2
Zo =
origin. 2+2
The nearest pole of the given question is S1. Zo = 1kΩ
S1= –0.00245×109 rad/sec.
Hence, S1 will be the upper 3 dB frequency of the 14. When voltage gain Av is greater than 1, the
amplifier. voltage gain in dB is .
(a) zero (b) positive
(c) negative (d) one
UPRVUNL AE -19.07.2021, Shift-II
V 
Ans. (b) : Voltage gain in dB = 20 log10  out 
 Vin 
For voltage gain = 1 → dB = 0 dB
voltage gain = 1.1 → dB = 1 dB (positive).
15. For a single stage amplifier, if Ai = – 48.54,
11. The output resistance of a multistage amplifier Ri = 1085.44 ohms and Rs=1k ohms, what is the
is equal to the: value of A?
(a) addition of output resistance of individual (a) – 20 (b) 20
stages (c) – 23.28 (d) 25
(b) output resistance of final stage UPRVUNL AE -19.07.2021, Shift-II
(c) product of output resistances of individual
A .R −48.54 × 1085.44
stages Ans. (c) : A = v i = = −25.26
(d) input resistance of first stage Ri + Rs 1085.44 + 1000
UPRVUNL AE -19.07.2021, Shift-II = –23.28.

Analog Electronics 301 YCT

16. A BJT has Ce=1pF. If gm is 50 mA/V, calculate
Ans. (c) : In a cascaded amplifier, the transformer
the fT of a common-emitter amplifier. coupling method which is capable of providing the
(a) 20 MHz (b) 80 MHz highest gain. Transformer coupled amplifier are used as
(c) 8 GHz (d) 2 GHz power amplifier to drive high power speaker load.
APPSC POLY. LECT. 14.03.2020 19. An npn transistor has beta cut-off frequency
mA fβ of 1 MHz, and common emitter short circuit
Ans. (c) : Ce = 1 pF gm = 50 low-frequency current gain βo of 200 at unity
V gain frequency fT and the alpha cut-off
g 50 × 10 −3

fT = m = frequency f α to respectively are-

2πCe 2π× 10−12 (a) 200 MHz 201 MHz (b) 200 MHz 199 MHz
= 7.9 GHz (c) 199 MHz 201 MHz (d) 201 MHz 202 MHz
f T = 8 GHz Nagaland PSC CTSE (Degree)-2017, Paper-II
Kerala PSC Lect. (NCA) - 04/07/2017
17. Generally, the gain of a transistor amplifier
falls at high frequencies due to the GATE-1996
(a) Internal capacitances of the device Ans. (a) : fβ = 1MHz β = 200
(b) Coupling capacitor at the input f T = β × fβ f α = (1 + β ) fβ
(c) Skin effect
(d) Coupling capacitor at the output fT = 200 × 1 f α = (1 + 200 ) × 1
GATE – 2020, 2003, IES-2018 f = 200 MHz f α = 201 MHz
T
Nagaland PSC CTSC (Degree)- 2017, Paper-II
GPSC Asstt. Prof.-11.04.2017 20. In a multi-stage RC-coupled amplifier the
TSPSC Manager (Engg.)-2015 coupling capacitor.
Ans. (a) : The current gain of a bipolar transistor drops (a) Limits the low frequency response
at high frequencies because of the transistor (b) Limits the high frequency response
capacitances. (c) Does not effect the frequency response
If frequency will be high then, (d) Blocks the d.c. components without effecting
the frequency response
Nagaland PSC CTSE (Degree)-2018, Paper-II
GPSC Asstt. Prof.-11.04.2017
GATE-1993
Ans. (a) : The low frequency response of an Amplifier
is effected by coupling capacitors and bypass
capacitors.
The high-frequency response of the amplifier is affected
1
XC = or f ↑→ X C ↓ by junction capacitors.
2πfC 21. Input voltage applied to a circuit is 1Vrms and
So, XC will be very small therefore it behaves like a the output is 1mVrms. Net gain of the circuit is:
short circuit. The loading effect of next stage increases, (a) +30dB (b) –30dB
which reduces the voltage gain. It is increases the Ib.
(c) –60dB (d) +60dB
So, current gain are reduces.
ISRO Scientist Engg.-2013
Hence, the voltage gain rolls at high frequency.
Internal capacitances of the BJT are Cbc, Cbe, Cce. Ans. (c) : Given that,
For Cce → Shunting effect at high frequency in the Input voltage (Vin) = 1Vrms
output side and reduces the gain of the amplifier. Output voltage (Vout) = 1mV = 10–3Vrms
I V
Current gain ( β ) = C Net gain (G) = 20log out
Vin
I
B

So, IC ↓→ β ↓ 10−3
Net gain (G) = 20log
18. In a cascade amplifier, the coupling method 1
which is capable of providing highest gain is Net gain (G) = –60log1010
(a) RC coupling = –60 dB
(b) Direct coupling 22. For a directional coupler, the quantities
(c) Transformer coupling I (isolation in dB), D (directivity in dB),
(d) Impedance coupling C (coupling in dB) are related by
RRB JE-31.08.2019, 10AM – 12PM (a) I = C/D (b) I = D – C
Nagaland PSC CTSE (Diploma)- 2018, Paper-I (c) I = D + C (d) I = D/C
Nagaland PSC CTSE (Diploma)- 2018, Paper-II ISRO Scientist Engg.-2013
Analog Electronics 302 YCT
Ans. (c) : Given that, VBE1 = VB − VE
I = Isolation in dB. 0.3V = VB − ( −10 )
D = Directivity
Direction coupler C = Coupling in dB VB = −9.7V
VCE − VB 10 − ( −9.7 )
So, I1 = =
R 20kΩ
P  19.7
Q Coupling = 10log  1  …………..(i) = = 0.985mA
20kΩ
 P3  β of the transistor is very high
P 
Isolation = 10log  1  …………..(ii) So, β =
IC
, ∴ IB = 0
 P4  IB
P  I B1 = I B2 = 0
Directivity = 10log  3  …………..(iv)
 P4  I1 = IC1 = 0.985mA
P P P I = 3.IC1
Therefore, 1 = 1 . 3
P4 P3 P4 = 3 × 0.985mA
= 2.955mA
P  P  P 
10log  1  = 10log  1  + 10log  3  24. Each Transistor in Darlington pair (as shown
 P4   P3   P4  in Fig.) has hfe = 100. Overall hfe of composite
I = C+D transistor neglecting leakage current is,
23. For the current mirror circuit shown below, if
the emitter area of Q2 is thrice of Q1, the
current I is :

(a) 10000 (b) 10001

(c) 10100 (d) 10200
ISRO Scientist Engg.-2016
Ans. (d)

(a) 0.328 mA (b) 2.955 mA

(c) 0.105 mA (d) 0.012 mA
ISRO Scientist Engg.-2013
Ans. (b)

Q Given transistor (each) in Darlington pair h fe = 100

IC
h fe = and IC = βI B
IB
I E = IC + IB = βI B + I B
= (1 + β ) I B
IC1
For transistor Q1 = h fe1 = = β1
I B1
Given Q2 = 3Q1 I C2
And Q2 = h fe2 = = β2
So, β2 = 3β1 i.e. collector current of ( Q 2 ) is three time I B2
of collector current of Q1 Q h fe = h fe1 = h fe2
Assume, transistor is Ge
IC
So, cut-off For full circuit h fe =
VBE = 0.3V IB

Analog Electronics 303 YCT

IC = IC1 + IC2 = h fe1 IB1 + h fe2 I B2 26. The following circuit represents the low
frequency model of
I B2 = I E1 = ( β + 1) IB1 = ( h fe + 1) I B1
IC = h fe  IB1 + ( h fe + 1) IB1 
IC = h fe I B1 [1 + h fe + 1]
IC = h fe I B1 [ 2 + h fe ] (I B = IB1 )
IC
= 2h fe + h fe2 = h fe (a) RC coupled amplifier
IB
(b) Phase shift oscillator
h fe = 1002 + 2 ×100 (c) Darlington circuit
h fe = 10200 (d) Single stage common emitter amplifier
TNPSC AE - 2018
25. Find the approximate output impedance of the
Ans. (a) : RC coupled coupling is the most widely used
VCCS (voltage-controlled current source) method of coupling in multistage amplifier. Give circuit
based circuit at port V0. is a multistage connection of amplifier.
27. h-parameter indicating input resistance in a
common emitter circuit is
(a) hfe (b) hre
(c) hoe (d) hie
GPSC Asstt. Prof. 11.04.2017
Ans. (d): h–parameters are one system for
characterizing bipolar transistor. h parameter indicating
input resistance in a common emitter circuit is hie.
28. The lower cut-off frequency of the transistor
(a) 0.01 Ω (b) 100 Ω stage in the adjoining figure is
(c) 100 kΩ (d) 10 MΩ
ISRO Scientist Engg.-2010
Ans. (b) :

(a) 7.95 Hz (b) 13.25 Hz

(c) 5.30 Hz (d) 3.18 Hz
BSNL (JTO)-2006
Ans. (c) : Given R1 = 3k , C1 = 1µF
Lower cut-off frequency
1 1
V = –VT fL = = = 5.30 Hz
2πR1C1 2π × 3 × 103 × 10 ×10−6
Apply Nodal at node output-
VT V 29. For a directional coupler the power is in the
IT + g m V = + T ratio of
100KΩ R in (a) 40dB (b) 30dB
 1 1  (c) 20dB (d) 10dB
IT = VT  + + 0.01
 100KΩ 10MΩ  Ans. (c) : For a directional coupler the power is in the
ratio of 20 dB.
VT 10MΩ 10 × 106
=  30. In an amplifier, the coupling capacitors are
IT 100 + 1 + 105 105 employed for
= 100Ω (a) Limiting the bandwidth
VT (b) Matching the impedance
So, Impedance = (c) Controlling the output
IT
(d) Preventing of dc mixing with input or output
= 100Ω Mizoram PSC IOLM -2018, Paper II
Analog Electronics 304 YCT
Ans. (d) : Coupling capacitors are essential component
The cascode is a two stage amplifier that consist of a
in amplifier circuits, they used to prevent interference of
common-emitter stage feeding in to a common-base
a transistor's bias voltage by AC signals. stage. Cascode have many advantage over single stage
31. Consider the amplifier model shown below amplifier like better output isolation, high input and
output impedance and high bandwidth.
V
The voltage gain 0 of the amplifier is 34. If the value of hfe increases, the
Vs (a) value of input impedance decreases and the
value of current gain increases
(b) values of both the input impedance and the
current gain decrease
(c) values of both the input impedance and the
current gain increase
(a) 150 (b) 50 (d) value of input impedance increases and the
(c) 200 (d) 100 value of current gain decreases
UPPCL AE- 31.12.2018 TNPSC AE-2014
Ans. (c) : Apply voltage division rule- Ans. (a) : β for A.C analysis of the CE circuit (hfe)
1× Vs i2 β ib
Vi = [ Vs = 2Vi ] hfe = = =β
1+1 i1 ib
Apply KCL - If the value of hfe increases, the value of input
V0 V0 impedance decreases and the value of current gain
0.1Vi + + =0
20 × 10 5 ×103
3 increases.
V  1 1 35. The h-parameter model is more commonly
0.1Vi = − 03  +  used because
10  20 5 
(a) h-parameter can be measured more easily
V 1 + 4 
0.1Vi = − 03  (b) h-parameter does not vary with frequency
10  20  (c) the analysis, with h-parameter gives the same
V0 expression for the performance for all
0.1Vi = − configurations
4 × 103
(d) h-parameter model is an accurate
V0 = −4 × 10 2 Vi
representation
V0 4 ×102 Vi TNPSC AE-2013
=−
Vs 2Vi Ans. (a) : The h-parameter model is more commonly
used because h-parameter can be measured more easily.
= 2 × 10 2 = 200 h-parameter can not used for high frequency model.
32. In the Hybrid-pi model for the BJT small 36. In an amplifier the increase in gain is 12 dB if
signal analysis, rπ denotes the frequency is doubled. What will be the gain
(a) Input resistance (b) Trans conductance if frequency is increased 10 times?
(c) Output resistance (d) Trans impedance (a) 20 dB (b) 40 dB
UPPCL AE- 31.12.2018 (c) 2.4 dB (d) 60 dB
Ans. (a) : In BJT small-signal models there are both re MPPSC Forest Service Exam.-2014
and rπ parameter. They both represent the dynamic
resistor between the base and emitter terminals. Ans. (b) : When frequency is double gain K = 12dB
Now when frequency is 10 times increase
33. Which of the following configuration provides
maximum gain bandwidth product? Gain K = 40 dB
(a) Common base amplifier 37. If a CE stage is directly coupled to an emitter
(b) Differential amplifier follower
(c) Cascode amplifier (a) Low and high frequencies will be passed
(d) Cascade amplifier (b) Only high frequencies will be passed
UJVNL AE-2016 (c) High-frequency signal will be blocked
Ans. (c) : (d) Low-frequency signals will be blocked
Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (a) : An emitter follower delivers maximum power
to a low impedance load. It acts as a buffer between
input and output. Therefore, if a CE stage is directly
coupled to an emitter follower, there will be maximum
power delivered or all the frequencies from low to high
will be passed.
Analog Electronics 305 YCT
38. A three stage amplifier with identical stages Double-tuned circuit - A double tuned circuit, which
with lower cut off frequency per stage = f1 is consisting of two magnetically coupled, identical high-
given overall negative feedback Depending on quality factor tuned circuit.
the overall gain, the system may oscillate at a It operated at the same resonant frequency will have the
low frequency fc given by magnitude response always high.
f f 1 Stagger-tuned amplifier -
(a) 1 = 1 (b) 1 = In these two single tuned cascaded amplifiers having
fc fc 3 certain bandwidth are taken and their resonant
f1 f1 1 frequency are so adjusted that they are separated by an
(c) = 3 (d) = amount equal to B.W of each stage.
fc fc 2 41. A CE amplifier has an unbypassed emitter
Nagaland PSC CTSE (Degree)-2016, Paper-II resistance of 0.5 kΩ and a collector load of
Ans. (c) : A three stage amplifier with identical stages 5k Ω. The β of the transistor is 100 and it is
with lower cut off frequency per stage is "f1", then operating at 1 mA. The voltage gain of the
system may oscillate at a low frequency given by stage at mid band will be of the order of
f1 (a) 200 (b) 100
= 3 (c) 10 (d) 50
fc
IES-2011
39. When two identical stages with upper cutoff Ans. (c) : Given R =0.5 kΩ, Rc = 5kΩ
frequency ωH are cascaded, overall cutoff
e
gmR c 1 −R C
frequency is at: Av = = Q R E >>> | A V |=
(a) 1ωH (b) 2ωH 1 + gm R E gm Re
(c) 0.5ωH (d) 0.64ωH 5
AV =
Nagaland PSC CTSE(Degree) - 2016,Paper II 0.5
IES-2013 A V = 10
Ans. (d) : Given that, 42. Which of the following components control the
N=2 high frequency response of the R-C coupled
1 amplifier?
fH = fH × 2 − 1
* N
1. Parasitic capacitances of the transistor
f H* = 0.64f H 2. Coupling capacitance
3. Stray capacitance
40. In order to increase the bandwidth of tuned 4. Wiring capacitance
amplifiers, one can use: Select the correct answer using the code given
1. Tuned circuit with inductance having high below:
Q factor (a) 1 and 2 only (b) 2 and 3 only
2. Double tuned amplifier with two tuned (c) 3 and 4 only (d) 1, 3 and 4
circuits coupled by mutual inductance
IES-2009
3. Staggered tuned amplifiers in which
different tuned circuits which are cascaded Ans. (d) : Parasitic capacitances of the transistor, or
stray capacitance or wiring capacitance components
are tuned to slightly different frequencies
control the high frequency response of the R-C coupled
(a) 1, 2 and 3 (b) 1 and 2 only amplifier.
(c) 2 and 3 only (d) 1 and 3 only RC coupled amplifier of pertaining to frequency
IES-2013 response-
Ans. (c) : The tuned amplifier is capable of amplifying Coupling capacitance effects low frequency
a signal over a narrow band of frequencies centered at response.
By pass capacitance effect low frequency response.
Both statements is correct.
Frequency response curve is graph that indicates and
relationship between voltage gain and function of
frequency.

The quality factor is the ratio of resonant frequency of

band width
fr
Q=
B.W.

Analog Electronics 306 YCT

43. Consider the following statements: f H = 2.02MHz
Tuned amplifiers
1. are wide band amplifiers BW
fL = f c − = 2MHz − 0.02MHz
2. are used in radio transmitters and receivers 2
3. performance is determined by Q of the circuit f L = 1.98MHz
Which of the statements given above are
correct? 46. The two stages of a cascade amplifier have
(a) 1 and 2 only (b) 2 and 3 only individual upper cut-off frequencies f1=5 MHz
(c) 1 and 3 only (d) 1, 2 and 3 and f2=3.33 MHz. What is the best
IES-2009 approximation for the upper cut-off frequency
of the cascade combination?
Ans. (b) : Tuned amplifier are the amplifiers that are
(a) 4.16 MHz (b) 3.33 MHz
employed for the purpose of tuning. Tuning means
selecting among a set of frequency available, if there (c) 2.5 MHz (d) 5.00 MHz
occurs a need to select a particular frequency, the tuned IES-2006
amplifiers are used in ratio transmitters and receivers Ans. (c) : Given that
and performance is determined by Q of the circuit. f1 = 5 MHz and f 2 = 3.33 MHz
44. Which one of the following statements is 1 1 1
correct? = +
The rise time of an amplifier is f UCF f1 f 2
(a) Directly proportional to the upper 3-dB 1 1 1
frequency = +
f UCF 5 3.33
(b) Inversely proportional to the upper 3-dB
1 1
frequency =
(c) Directly proportional to the lower 3-dB f UCF 2
frequency f UCF = 2 MHz
(d) Inversely proportional to the lower 3-dB
frequency Best approximation fUCF = 2.5 MHz
IES-2007 47. A cascaded amplifier comprises N identical
non-interacting stages, each having a lower
Ans. (b) : Rise time of an amplifier is measured with
respect to time, i.e. , 3dB frequency of fL. If fL* is the lower 3 dB
0.35 frequency of the cascaded amplifier, then
tr = which one of the following is correct?
B.W.
1 (a) f L* = f L (b) f L* = f L 21/ N − 1
tr ∝
B.W. fL fL
(c) f L* = (d) f L* =
Since bandwidth is taken to be the upper 3dB cut-off 2 −1 1/ N N
frequency. IES-2012, 2005
Hence Bandwidth ≈ higher cut off frequency.
Ans. (c) : N-identical non-interacting amplifiers are
45. A tuned amplifier has peak output at 2 MHz cascaded and each amplifier has an individual cut-off
and quality factor 50. The bandwidth and 3-dB frequency f L1 & FH1 then the overall cut-off frequency of
frequencies shall be at what values
respectively? the cascaded amplifier will be -
(a) 40 kHz, 2.02 MHz, 1.98 MHz f L1
(b) 40 kHz, 2.04 MHz, 1.96 MHz f L* =
1
(c) 80 kHz, 2.04 MHz, 1.96 MHz 2 N −1
(d) 80 kHz, 2.08 MHz, 1.92 MHz 1
f H* = f H1 × 2 N
−1
Sikkim PSC SI (Mains)-2018
IES-2014, 2011, 2007 1
for 2 N − 1 < 1
Ans. (a) : Given that, fc = 2 MHz
Note - Cascading increases lower cut-off and decreases
Q = 50
higher cut-off frequency hence bandwidth decreases.
f 2 × 106
B.W = c = = 40 kHz 48. A transistor RC coupled amplifier is designed
Q 50 for a voltage and band gain of 20. But a
Upper and lower 3 db frequency will be respectively- measurement at a particular frequency shows
BW the gain to be only [Link] is the likely phase
fH = fc + shift at this frequency?
2 (a) 180º (b) 135º
40kHz (c) 90º (d) 45º
f H = 2MHz + = 2MHz + 0.02MHz
2 IES-2005
Analog Electronics 307 YCT
Ans. (b) : Given, 51. Which one of the following statements is
A0 = 20 correct?
A = 14 If in a doubled-tuned voltage amplifier, the
mutually coupled secondary and primary are
A0 f
A= Where , 1 ≈ 1 synchronously tuned with equal Q values then
1 + i  1 
f fº for the over-coupled case the maximum voltage
 f0  amplification
20 (a) is greater than that for critical coupling and
14 = the amplifier characteristic is double peaked
1
1+ i  (b) is less than that for critical coupling and the
1 amplifier characteristic has a single peak
40 (c) is same as that for critical coupling and the
A=
1+ i amplifier characteristic is double peaked
(d) is less than that for critical coupling and the
1
φ = − tan −1   = −45º amplifier characteristic is doubled peaked.
1 IES-2004
φ = 180º – 45º = 135º Ans. (d) : A doubled-tuned voltage amplifier, the
49. A tuned amplifier has a voltage gain of 100 and mutually coupled secondary and primary are
a bandwidth of 10 kHz. It is required to synchronously tuned with equal Q values is less than
increase the bandwidth to 20 kHz. This can be that for critical coupling and the amplifier characteristic
achieved by which one of the following ways? is doubled peacked.
(a) By doubling the gain 52. An amplifier has two identical cascaded stages.
(b) By doubling the resonant frequency Each stage has a bandwidth of 20 kHz. The
(c) By halving the Q of the coil overall bandwidth shall approximately be
(d) By halving the power supply voltage equal to
(a) 10 kHz (b) 12.9 kHz
IES-2004
(c) 20 kHz (d) 28.3 kHz
Resonant frequency IES-2003
Ans. (c) : B.W =
Quality factor Ans. (b) : Given, N = 2
where, fr = Resonant frequency Bandwidth = 20 kHz
Q = Quality factor 1
Over all bandwidth = B.W × 2 2 − 1
since bandwidth is increase from 10kHz to 20 kHz,
1
means doubled, Hence the value of Q will be halved. = 20 × 2 2 − 1
50. The transfer function of a transistor amplifier = 20 × 1.414 − 1
is given by
= 20 × 0.64
V 4240 = 12.9 kHz
AV = 0 =
VS  f  f  53. The common emitter current gain-bandwidth
1 + j  1 + j 
 4 ×105  4 ×106  product of a transistor (fT) is defined as the
Which one of the following gives the frequency at which
approximate upper 3-dB frequency fH of the (a) Alpha of the transistor falls by 3 dB
amplifier? (b) Beta of the transistor falls by 3 dB
(a) 4 × 105 Hz (b) 2.2 × 106 Hz (c) Beta of the transistor falls to unity
6
(c) 4 × 10 Hz (d) 4.4 × 406 Hz (d) Power gain of the transistor falls to unity
IES-2004, 1997 LMRC AM (S&T) 13.05.2018
IES-2005, 2003
Ans. (a) : Given,
Ans. (c) : Unity gain frequency (fT) is the frequency at
1 1
= 4 ×105 Hz and = 4 ×106 Hz which (CE) common emitter short circuit current gain
f1 f2 (β) of the transistors falls to unity, it is expressed by -
1 1 1 gm
= + fT =
f H f1 f 2 2π ( Cµ + C π )
1 1
= + 54. Which of the following components control the
4 × 105 4 × 106 low frequency of the R-C coupled amplifier?
4 × 105 1. Wiring capacitance
fH = 2. Parasitic capacitances of transistor
1.1
3. Coupling capacitances
f H = 3.63 × 105 ≃ 4 ×105 Hz 4. Emitter bypass capacitance
Analog Electronics 308 YCT
 Select the correct answer using the codes given Ans. (a) : Beta cut-off frequency given by -
below: gm / β
fβ =
2π ( Cµ + C π )
(a) 1 and 2 (b) 2 and 3
(c) 3 and 4 (d) 1, 2 and 4
IES-2015, 2013, 2009, 2003, 2000 1
=
Ans. (c) : Coupling capacitances and emitter bypass 2π ( Cµ + C π ) r
capacitance are the components which can control the For fβ to be higher, and Cµ should be smaller.
low frequency of the RC coupled amplifier.
55. For a BJT in common emitter mode, base to 58. An RC amplifier stage has a bandwidth of
emitter capacitance (Cπ) is ten times the 500 kHz. What will be rise time of this
amplifier stage?
collector to base capacitance (Cµ). Transistor is
biased at quiescent collector current ICQ = 1 (a) 0.35 µs (b) 0.7 µs
mA and its short circuit unity gain frequency is (c) 1.0 µs (d) 2.0 µs
0.909 M (rad/s). What is the (Cπ) value? IES-2007, 2002
(a) 6.45 nF (b) 44 nF Ans. (b) : Given,
(c) 40 nF (d) 7.1 nF Bandwidth = 500 kHz
IES-2003 0.35
Rise time, tr =
Ans. (a) : Unity gain frequency - Bandwidth
gm 0.35
fT = =
2π ( Cµ + C π ) 500 ×103
= 0.7 µs
given, Cπ = 10Cµ 59. In a single-stage RC coupled common emitter
Trans conductance - amplifier, the phase shift at the lower 3 dB
I frequency is
g m = CO (a) zero (b) 135º
VT
(c) 180º (d) 225º
ICO
fT = Nagaland PSC-2018, Diploma Paper-II
2π × 11Cµ × VT IES-2001
1× 10 −3 Ans. (d) : The phase shift can be given by -
0.909 = f 
2 × 3.14 ×11× Cµ × 26 × 10−3 φ ( f ) = 180 + 90 − tan −1  
1× 10−3  f1 
Cµ = Transfer function is of the form A(if)
6.28 × 11× 26 × 10−3 × 0.909
Cµ = 0.0006125 A 0 ( jf )
Aif =
Cµ = 0.64 nF 1 + j  f 
 f1 
and Where f1 is the lower 3 db frequency
C π = 10Cµ ⇒ 6.45 nF f 
φ ( f1 ) = 180º +90º − tan −1  1 
56. Which one of the following is a wide band  f1 
amplifier? = 180º + 90º – 45º
(a) RF amplifier (b) IF amplifier φ ( f1 ) = 225º
(c) Video amplifier (d) AF amplifier
IES-2003 60. An amplifier using BJT has two identical stages
Ans. (a) : Wide band amplifier- An amplifier that will each having a lower cut-off (3 dB) frequency of
pass a wide range frequency with substantially uniform 64Hz due to coupling capacitor. The emitter
amplification RF amplifier is a wide band amplifier. bypass capacitor also provides a lower cut-off
(3 dB) frequency due to emitter degeneration
57. A BJT is to be used in a high frequency circuit alone of 64 Hz. The lower (3 dB) frequency of
in common emitter amplifier. For a higher the overall amplifier is nearly
upper cut-off frequency Cµ, Cπ and r0 have their (a) 100 Hz (b) 128 Hz
usual meanings) (c) 156 Hz (d) 244 Hz
(a) Cµ should be as small as possible IES-2000
(b) r0 and Cµ should be as large as possible Ans. (a) : Given -
(c) Cπ and Cµ should be as large as possible. Number of stages N = 2
(d) r0, Cπ and Cµ should be as large as possible. Lower 3dB frequency, fL = 64 Hz
IES-2002 Lower (3dB) frequency of the overall amplifier =
Analog Electronics 309 YCT
 fL Codes:
f L* = A B C D
21/ N − 1 (a) 1 3 1 2
64 (b) 3 4 2 1
=
1 (c) 3 4 1 2
22 −1 (d) 4 3 2 1
64 IES-1997
=
0.414 Ans. (c) :
64 List-1 List-II
= = 100 Hz (A) R.C- coupled – Flat frequency with an
0.64 Amplifier Upper and a lower cut-
f L* = 100 Hz off frequency
(B) Tuned Amplifier – Peak in gain frequency
61. If the Q of a single-stage tuned amplifier is response response.
doubled, then its bandwidth will
(C) Chopper stabilized – Very low drift.
(a) remain same (b) become half
response Amplifier
(c) become double (d) become four times
frequency
IES-2016, 2000
(D) Direct coupling – Flat frequency
Ans. (b) : The quality factor (Q) of a single-stage tuned capacitor response from zero
amplifier is doubled, then its bandwidth will become
frequency onwards
half.
64. For a bipolar junction transistor, if the current
Resonant frequency amplification factor and cut-off frequency in
Bandwidth =
Quality factor the CB mode are αCB and f αCB respectively,
then the cut-off frequency in the CE mode is
62. The input resistance of a common emitter stage equal to
can be increased by :
(a) fαCB (b) f αCB (1 – αCB)
1. un bypassing emitter resistance
(c) f αCB/(1 – αCB) (d) f/αCB
2. bootstrapping
IES-1997
3. biasing it at low quiescent current
4. using compounded BJTs Ans. (c) : For a bipolar junction transistor, if the current
The correct sequence in descending order of amplification factor and cut-off frequency in the CB
the effectiveness of these methods is mode are αCB and f αCB respectively, then the cut-off
(a) 2, 4, 1, 3 (b) 4, 3, 2, 1 frequency in the CE mode is equal to
(c) 2, 4, 3, 1 (d) 4, 2, 3, 1 Cut-off frequency of CB mode.
IES-1999 fα CB
=
Ans. (a) : The input resistance of a common emitter (1 − α CB )
stage can be increased by bootstrapping then using
compounded BJTs after that unbypassing emitter 65. In the case of an amplifier, the normalized
resistance then it is correct sequence of descending voltage gain is given by
order of the effectiveness. f
Hence correct order of effectiveness 2 > 4 > 1 > 3. 1+ j
Av 1 f0
63. Match List-I (Circuit) with List-II = .
A R f
(Characteristic) and select the correct answer 0 1+ 1 1+ j
using the codes given below the Lists: R 2 f p

List-I List-II Where f0 is the zero frequency and fp is the pole

A. RC-coupled 1. Very low drift frequency. For a standard frequency response
amplifier of the amplifier,
(a) fp >> f0 (b) fp = f0
B. Tuned amplifier 2. Flat frequency
response from (c) fp << f0 (d) f0 = 2 fp
zero frequency IES-1997
onwards Ans. (a) : For standard frequency response, pole
C. Chopper 3. Flat frequency frequency must be more than zero frequency.
stabilized response f p >> f 0
amplifier with an upper and
a lower cut- 66. Of the various capacitances associated with a
off frequency junction transistor, the gain-band width
product is affected to a maximum extent by
D. Direct coupling 4. Peak in gain
capacitor frequency (a) Base-collector parasitic capacitance
response (b) Base-collector space charge layer capacitance

Analog Electronics 310 YCT

 (c) Base-emitter space charge layer capacitance 68. Match List-I with List-II and select the correct
(d) Base-emitter diffusion capacitance answer using the codes given below the lists:
IES-1997 List-I List-II
Ans. (d) : A. RC coupling 1. Higher voltage gain &
Gain-bandwidth product is a transistor affected to a impedance matching
extent by- B. Inductive 2. Ability to amplify dc and
(i) Base- collector parasitic capacitance. coupling low frequency signals.
(ii) Base- emitter space charge layer capacitance. C. Transformer 3. Minimum possible
(iii) Base- collector space charge layer capacitance and coupling non-linear distortion
maximum affected by Base- emitter diffusion D. Direct coupling 4. Low collector supply
capacitance. voltages can be used
67. Consider the following statements: Codes:
In order to increase the bandwidth of tuned A B C D
amplifier, one can use (a) 4 1 3 2
1. Tuned circuit with inductance having high Q (b) 3 4 1 2
factor. (c) 1 2 3 4
2. Double-tuned amplifier with two tuned (d) 4 3 2 1
circuits coupled by mutual inductance. IES-1996
3. Staggered tuned amplifiers in which Ans. (b) :
different tuned circuits which are cascaded are List-I List –II
tuned to slightly different frequencies. RC- coupling - Minimum possible non-linear
Of these statements distortion
(a) 1 alone is correct Inductive coupling - Low collector supply voltage
(b) 1 and 2 are correct can be used
(c) 2 and 3 are correct Transformer coupling - High voltage gain and
(d) 1, 2 and 3 are correct Impedance matching.
IES-1997 Direct coupling - Ability to amplify dc and low
Ans. (c) : frequency signal
Double tuned Amplifier- 69. The upper 3 dB frequency in a Common
In double tuned Amplifier, voltage gain remains Emitter amplifier is given in terms of the
approximately constant inside pass band and it falls hybrid parameters as
rapidly out side pass band- g g
(a) b 'e (b) b 'e
2πC C
h g
(c) fe (d) m
g b 'e h fe
IES-1995
Ans. (a) :
Hybrid parameter-
fo
Bandwidth = 2 × ( for double tuned ) AI =
h fe
Q 2
Double-tuned amplifier with two tuned circuits coupled f 
1+  T 
by mutual inductance. f 
Staggered tuned- it is cascade of tuned Amplifier  β
having unequal resonant frequencies it is used to The upper 3 dB frequency in a common emitter
increased Bandwidth. Amplifier is-
g b 'e
=
2 πC
70. The bandwidth of an RC-Coupled Amplifier is
limited by
(a) Coupling Capacitors at the low-frequency end
and bypass Capacitors at high frequency end.
(b) Coupling Capacitors at high frequency end
and bypass Capacitors at the low frequency
Staggered tuned amplifiers in which different tuned end.
circuits which are cascaded are tuned to slightly (c) Bypass and Coupling Capacitors at the low
different frequencies. frequency end and shunt capacitors at the
So the statement 2, 3 are correct. high frequency end.
Analog Electronics 311 YCT
 (d) Shunt Capacitors at the low frequency end V Z
and bypass as well as Coupling Capacitors at i
=
the high frequency end. I i 1 − K
IES-2011, 1994 Z
Zi =
Ans. (c) : To limit the Bandwidth of an RC-coupled 1− K
Amplifier we use bypass and coupling capacitors at the
low frequency end and shunt capacitor (or junction 73. The fT of a BJT is related to its gm' Cπ and Cµ
capacitor) at the high frequency end. as follows
71. A two-stage amplifier is required to have an C π + Cµ 2π(C π + Cµ )
(a) fT = (b) fT =
upper cut-off frequency of 2MHz and a lower gm gm
cut-off frequency of 30 Hz. The upper and
lower cut-off frequencies of individual stages g m gm
(c) fT = (d) fT =
are respectively approximately C π + Cµ 2π(C π + Cµ )
(a) 4 MHz, 60 Hz (b) 3 MHz, 20 Hz GATE-1998
(c) 3 MHz, 60 Hz (d) 4 MHz, 20 Hz Ans. (d) The unity gain bandwidth frequency of a BJT
TNPSC A.E-2019 is related to its g C and C by Relation-
m' π µ
IES-1993
g
Ans. (b) : We known- fT = m

2π ( C π + Cµ )
fH = fH 2 −1
' 1N

74. An npn transistor (with C = 0.3 pF) has a

2 × 106 = f H 21 2 − 1 unity-gain cut-off frequency fT of 400 MHz at a
2 ×10 6 dc bias current Ic = 1 mA. The value of its
fH = Cµ (in pF) is approximately (VT = 26 mV)
0.414
(a) 15 (b) 30
f H = 3.1 MHz (c) 50 (d) 96
fL TNPSC AE-2019
f L' = TNPSE AE-2014, GATE-1999
21 2 − 1 Ans. (a) : Given-
f L = f L' 21 N − 1 ⇒ 30 21 2 − 1 =19.30 Hz  20 Hz C = 0.3 pF
72. In the circuit shown in figure is a finite gain f T = 400 MHz
amplifier with a gain of K, a very large input I = 1 mA
C
impedance, and a very low output impedance.
The input impedance of the feedback amplifier VT = 26 mA
with the feedback impedance Z connected as Cµ = ?
shown will be
1 1 I
fT = Where, = gm = C
2πRC R VT
IC 1 mA
fT = ⇒ Cµ =
2πVT × Cµ 2π × 26mV × 400 × 106
Cµ = 15pF
[Link] amplifier is assumed to have a single-pole
 1
(a) Z 1 −  (b) Z (1 – K) high-frequency transfer function. The rise time
 K of its output response to a step function input is
 Z   Z  35 nsec. The upper 3dB frequency (in MHz) for
(c)  (d) 
 K − 1   the amplifier to a sinusoidal input is
1 − K  approximately at
GATE-1996 (a) 4.55 (b) 10
Ans. (d) : (c) 20 (d) 28.6
V GATE-1999
Zi = i
Ii Ans. (b) : Given-
(tr) step function input is = 35 nsec.
Vi − Vo
Ii = t r × BW = 0.35
Z
0.35
 V  B.W =
Vi 1 − o  35 × 10−9
= 
Vi 
Z B ⋅ W = 10 MHz

Analog Electronics 312 YCT

76. An npn BJT has gm = 38 mA/V, Cµ = 10–14 F, 78. Which one of the following statements is
Cπ = 4×10–13F, and DC current gain β0 = 90. correct about an ac-coupled common-emitter
For this transistor fT and fβ are amplifier operating in the mid-band region?
(a) fT = 1.64 × 108 Hz and fβ = 1.47 × 1010 Hz (a) The device parasitic capacitances behave like
(b) fT = 1.47 × 1010 Hz and fβ = 1.64 × 108 Hz open circuits, whereas coupling and bypass
capacitances behave like short circuits.
(c) fT = 1.33 × 1012 Hz and fβ = 1.47 × 1010 Hz
(b) The device parasitic capacitances, coupling
(d) fT = 1.47 × 1010 Hz and fβ = 1.33 × 1012 Hz capacitances and bypass capacitances behave
GATE-2001 like open circuits.
Ans. (b) : Given- (c) The device parasitic capacitances, coupling
npn BJT gm = 38 mA/V capacitances and bypass capacitances behave
Cµ = 10–14 F like short circuits.
Cπ = 4×10–13F (d) The device parasitic capacitances behave like
β0 = 90 short circuits, whereas coupling and bypass
fT = ? capacitances behave like open circuits.
fβ = ? GATE-2016, Set-II
gm Ans. (a) : The device parasitic capacitances behave like
fT = open circuits, whereas coupling and bypass
2π ( C π + Cµ ) capacitances behave like short circuits when an AC-
coupled common-emitter amplifier operating in the
38 × 10−3
= mid-band region.
2π ( 4 × 10−13 + 10−14 ) 79. The Miller effect in the context of a common
emitter amplifier explains
f T = 1.47 × 1010 Hz
(a) An increase in the low-frequency cutoff
f T 1.47 × 1010 frequency
fβ = = (b) An increase in the high-frequency cutoff
βo 90
frequency
fβ = 1.64 ×108 Hz (c) A decrease in the low-frequency cutoff
frequency
77. A bipolar transistor is operating in the active (d) A decrease in the high-frequency cutoff
region with a collector current of 1 mA. Assuming frequency
that the β of the transistor is 100 and the thermal GATE-2017, Set-I
voltage (VT) is 25 mV, the transconductance (gm) Ans. (d) : Miller effect makes dominant increase in the
and the input resistance (rπ) of the transistor in the input capacitance of CE amplifier.
common emitter configuration, are
1
(a) gm = 25 mA/V and rπ = 15.625 kΩ Upper cut-off frequency (fh) ∝
(b) gm = 40 mA/V and rπ = 4.0 kΩ Cinput
(c) gm = 25 mA/V and rπ = 2.5 kΩ Hence, there is reduction in upper cut-off frequency and
(d) gm = 40 mA/V and rπ = 2.5 kΩ bandwidth of common emitter amplifier
IES-2014 80. The overall bandwidth of two identical voltage
GATE-2004 amplifiers connected in cascade will be:
Ans. (d) : Given that - (a) same as single stage
IC = 1mA (b) higher than single stage
(c) lower than single stage
VT = 25mV (d) higher if stage gain is low and lower if stage
β = 100 gain is high
RPSC VP/Suptd. ITI 05.11.2019
IC 10−3
gm = = Ans. (c) : the overall bandwidth of two identical voltage
VT 25 × 10−3 amplifiers connected in cascade will be lower than
g m = 40mA / V single stage.
81. In a transistor hfe = 50, hie = 830Ω, hoe = 10-4
1 1
re = = mho. Its output resistance when used in CB
g m 40 × 10−3 configuration is about
re = 25Ω (a) 2 MΩ (b) 2.5 MΩ
The hybrid parameter rπ will be- (c) 500 Ω (d) 500 kΩ
rπ = β × re = 100 × 25 TSPSC Manager (Engg.) - 2015
Ans. (d) : Given that-
rπ = 2.5kΩ hfe = 50, hie = 830Ω, hoe = 10 −4 
Analog Electronics 313 YCT
 h oe 10−4 86. A single stage amplifier has a voltage gain of
h ob = = 60. The collector load Rc = 500 Ω and the input
1 + h fe 1 + 50 impedance is 1kΩ. The overall gain when two
10−4 such stages are cascaded through R-C coupling
h ob = is:
51
(a) 60 (b) 3600
1 51
R ob = = −4 = 510 kΩ  500kΩ (c) 120 (d) 1200
h ob 10 (e) 2397
82. Consider the following data for common- CGPSC SO 14.02.2016
emitter hybrid equivalent circuit of BJT Ans. (e) : gain of single stage = 60
transistor, IE = 2.5 mA. hfe = 140, hoe = 20 µS Rc = 500Ω
and hob = 0.5 µS
Rin = 1000Ω
The values of hie and r0 will be nearly:
(a) 1.46 kΩ and 30 kΩ (b) 1.46 kΩ and 50 kΩ Effect load = Rc || Rin = 333Ω
(c) 1.64 kΩ and 50 kΩ (d) 1.64 kΩ and 30 kΩ 333
Gain of second stage = 60 × = 39.96
UPSC [Link].10.03. 2019 500
Total gain = 60 × 39.96 = 2397.6  2397
1 1
Ans. (b) : ro = = = 50kΩ 87. A three-stage amplifier has a first stage voltage
h oe 20 ×10−6 gain of 100, second stage voltage gain of 200
V 26mV and third stage voltage gain of 400. The total
re = T = = 10.4Ω voltage gain in dB is:
Ie 2.5mA
(Given that log10 100=2, log10 200=2.3, log10
β β
rπ = = = β.re = 140 ×10.4 = 1.456kΩ 400=2.6)
g m 1 re (a) 400 (b) 700
rπ  1.46kΩ (c) 350 (d) 138
83. The current gain of a bipolar transistor drops (e) 276
at high frequencies because of CGPSC SO 14.02.2016
(a) Transistor capacitance Ans. (d) : A1 = 100 A2 = 200 A3 = 400
(b) High current effects in the base Total Gain (A) = A1 A2 A3
(c) Parasitic inductive element = 100 × 200 × 400 = 8 × 106
(d) The early effect Gain in dB = 20 log A = 20 log (8 × 106)
Nagaland PSC (Degree) 2018, Paper-II = 138.0 dB
UPRVUNL AE 2016 88. A multistage amplifier employs five stages each
Ans. (a) : The current gain at high frequencies drop in of which has a power gain of 30? The total gain
BJT due to transistor (inter-electrode) capacitances. of the amplifier in dB is _____
84. Cascading amplifier stages to obtain a high (log10 30 = 1.477)
gain is best done with------ (a) 150 dB (b) 75 dB
(a) Common-emitter stages (c) 73.85 dB (d) 100 dB
(b) Common-base stages (e) 147.7 dB
(c) Common-collector stages TNPSC AE 2019
(d) (b) and (a) CGPSC SO 14.02.2016
TNPSC AE- 2019 Ans. (c) : Gain of each stage = 30
GPSC Asstt. Prof.-11.04.2017 Number of stages = 5
Ans. (a) : In cascaded amplifiers, the output as voltage Power gain of each stage in dB = 10 log10 30 = 14.77
of the first stage becomes the input voltage of the Total power gain = 5 × 14.77 = 73.85 dB
second stage and the ac output of the second stage
becomes the input of the third stage and so on. 89. The current ib through base of a silicon npn
Cascading amplifier stages to obtain a high gain is best transistor is 1+0.1 cos (100πt) mA. At 300K, the
done with common-emitter stages. rπ in the small signal model of the transistor is:
85. In a tuned circuit, the secondary circuit has a
capacitor of 100pF. The reflected value of this
25pF. The turn ratio is
(a) 2 : 1 (b) 1 : 2
(c) 4 : 1 (d) 1 : 4
Nagaland PSC CTSE- 2015, Paper-II
Ans. (c) : Given as- C1 = 100pF & C2 = 25pF
(a) 25 Ω (b) 27.5 Ω
C1 100
turn ratio a = , a= = 4 :1 (c) 125 Ω (d) 250 Ω
C2 25
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Analog Electronics 314 YCT
Ans. (a) : rπ = β / g m rb'c or gb'c Resistance of reverse 4M Ω
baised P-N junction 0.25 × 10−6 mho
Ic
gm = between base and
VT collector conductance
of reverse biased P-N
β
rπ = junction between base
( Ic / VT ) and collector
VT rce or gce Output resistance 80k Ω
rπ = β between collector and 12.5 × 10−6 mho
IC
emitter. Conductance
VT
rπ = ( β / Ic ) VT = between base and
Ib emitter
25mV Ce Junction capacitance 100pF
rπ = , between base and
1mA emitter
rπ = 25Ω Cc Junction capacitance 3pF
90. The common emitter model is shown below between base and
collector
92. Bootstrap voltage sweep generator uses
(a) negative feedback
(b) positive feedback
(c) both negative and positive feedbacks
simultaneously
The h-parameters of this model are (d) no feedback
8 1   5 1 RPCS Lect.-2011
(a)   (b)   Ans. (b) : A bootstrap sweep generator is a time base
0.8 0.25 0.8 1 generator circuit whose output is feedback to the input
8 0.8  5 0.8 through the positive feedback. This will increase or
(c)   (d)   decrease the input impedance of the circuit. The process
1 0.25 1 1  of bootstrapping is used to achieve constant charging
NIELIT Scientists- 2017 current.
Ans. (a) : Write input KVL and output KCL equation 93. Which component can amplify a small signal
V1 = h11I1 + h12 V2 but must use high voltages?
I 2 = h 21I1 + h 22 V2 (a) A vacuum tube
(b) A transistor
V1 = 8I1 + V2
(c) An electrolytic capacitor
V (d) A multiple-cell battery
I2 = 0.8 I1 + 2
4 RRB SSE-03.09.2015, Shift-III
 8 1 Ans. (a) : Vacuum tubes are used to amplify very small
 h11 h12  8 1 
h  =  1  =   signals and use them at high voltages.
 21 h 22   0.8 0.8 0.25
 4  94. A BJT differential amplifier with matched
transistors is having hfe of 200 and hie of
91. Which one of the following is not an element of 1.2kΩ and Rc of 3.3kΩ. Find the differential
a hybrid π model gain, AV.
(a) rbb (b) CC (a) -350 (b) 300
(c) Ce (d) hfe (c) -275 (d) 295
Nagaland PSC CTSE (Diploma)-2018, Paper-I
Nagaland PSC CTSE (Degree)-2017, Paper-II UPPCL AE-05.11.2019
Ans. (d) : hfe is not an element of a hybrid π model. Ans. (c) : Given R c = 3.3kΩ
Hybrid- π parameter element and value:- h fe = 200
Parameter Meaning Value h ie = 1.2kΩ
Im Mutual conductance 50mA/V Rc
rbb' Base spreading 100Ω AV = − × h fe
resistance 2h ie
rb'e or Ib'e Resistance between 1k Ω AV = −
3.3
× 200
base and emitter 1m mho 2 × 1.2
conductance between
base and emitter A V = −275

Analog Electronics 315 YCT

95. For the base bias circuit, R B = 470kΩ, (a) 20 dB (b) 10 dB
R C = 2.2kΩ, and VCC = 18V and the transistor (c) –40 dB (d) –20 dB
NLC GET -24.11.2020
has an hfe of 100. Find VCE .
Ans. (c) : For % THD, the dB distortion will be
(a) 8.548 V (b) 10.246 V
x%
(c) 12.602 V (d) 9.902 V = 20log10
100
UPPCL AE-05.11.2019 for 1% THD, the dB distortion will be
Ans. (d) : Given- 1
R B = 470kΩ , R C = 2.2kΩ , VCC = 18V = 20log10 = 20log1010–2
100
β = h fe = 100 = 20×(–2)log1010
Base bias circuit is represented as = −40dB
98. Following is the small-signal high-frequency
equivalent circuit of a common source
amplifier. V0/Vi will be of the form (K, z1, a0, a1,
a2, a3 are constants containing circuit
elements).

Or
Fixed bias circuit
V − VBE
I B = CC , with IC = β IB
R BE
18 − 0.7
IB = = 0.036mA (a) K ( s − z ) / ( a 0 + a1s + a 2s 2 )
470kΩ
The value of the collector current is (b) K.s / ( a 0 + a1s + a 2s 2 + a 3s3 )
IC = βI B
(c) K ( s − z1 )( a 0 + a1s )
= 100 × 0.036mA
The value of the collector current is VCE = VCC − IC R C (d) K / ( a 0 + a1s )
= 18 − 3.68 × 2.2 ISRO Scientist December, 2017
= 9.902V Ans. (a) : General gain equation for small signal high
frequency common source amplifier is-
96. A two stage capacitor coupled CE amplifier has
( )( 0 1 2 )
stages having a voltage gain of 100 each. It is G = Vo = K s–z a + a s + a s 2
known that the gain of each stage drops by 3dB Vi
at lower cutoff frequency. What is the overall
gain of the multistage amplifier at lower cutoff 99. A BJT Darlington pair has :
frequency? (a) high input impedance and high β
(a) 74 dB (b) 34 dB (b) high input impedance and low β
(c) -74 dB (d) -34 dB (c) low input impedance and high β
UPPCL AE-05.11.2019 (d) low input impedance and low β
Ans. (a) : For two stage amplifier- DRDO-2009
A = A ×A
V V1 V2
Ans. (a)

A V ( dB ) = A V1 ( dB ) + A V2 ( dB )
When gain is 100,
A V1 = 20log (100 ) = 40dB.
It is given that the gain of each stage drops by 3dB
Gain of first stage (Av1) = (40–3)dB = 37dB
Gain of output of second stage (Av2) = 37 dB
The over all gain will be
A v = A v1 + A v2 A Darlington pair is a two-transistor circuit with the
= 37 + 37 emitter of one transistor is connected to the base of the
= 74 dB other transistor, while both collector terminals are
97. What is the dB distortion for an amplifier with connected to the common terminals. it has high current
1 percent THD? gain β and it also has high input impedance.

Analog Electronics 316 YCT

100. In the circuit shown in figure below, β for the Ans. (b) : As compared to CE amplifier, the frequency
BJTs is 99. response of an emitter follower is Better because its
bandwidth is larger.
103. If two stages of a cascaded amplifier have
decibel gains of 60 and 30, then overall gain is
............. dB.
(a) 90 (b) 1800
(c) 2 (d) 0.5
TNPSC AE-2008
Ans. (a) : The overall gain in dB can be written as,
Assuming the thermal voltage to be 50 mV, the
input resistance Ri is : A V (dB) = A V1 (dB) + A V2 (dB) + ........ + A n (dB)
(a) 650 Ω (b) 25 kΩ A v (dB) = 30 + 60
(c) 40 kΩ (d) 65 kΩ
DRDO-2009 A v (dB) = 90 dB
Ans. (d) : Given β = 99 104. For a transistor
hie = 1kΩ, hfe = 30Ω, hre = 0
I 0.8
Sol. Io = 0.8, mA IC1 = IC2 = o = = 0.4mA hoe = 20 × 10–6  , and RL = 2.5 kΩ
2 2 The transistor is used in a single stage CE
β β amplifier. The voltage gain and power gain,
rπ = = = β re
g m 1 re respectively, are
V 50mA (a) 75 and 1750 (b) 25 and 2250
re = T = = 125Ω (c) 75 and 2250 (d) 25 and 1750
IC 0.4mA IES-2019
loop equation.
Ans. (c) : Given that, h ie = 1× 10 Ω = Rb
3
− Vi + rπi b + 200i e + 200i e + rπi b = 0
h fe = 30Ω
2rπi b + 400i e = Vi
hre = 0
2rπ + 400 ( β + 1) i b = Vi h oe = 20 × 10 −6 
V
2  reβ + 200 ( β + 1)  = i R L = 2.5kΩ
ib If (hoe×RL)< 0.1
R i = 2 [125 × 99 + 200 × 100] AI  β = h fe = 30
= 64.75KΩ
 65KΩ
101. Consider a diode with reverse saturation
current Is = 9.5 × 10–15 A and thermal voltage
VT = 26 mV, ideality factor n = 1. For voltage
0.65 V across the diode, the diode current is
approximately
(a) 0.032 mA (b) 1.22 mA Single stage CE amplifier voltage gain
(c) 0.68 mA (d) 4.87 mA  RL 
UPPCL AE- 31.12.2018 A v = β  R 
 b
 VηBE   2.5 
Ans. (c) : I D = IS e VT − 1 = 30 ×   = 75
   1 
 0.65  Power gain = [Link]
I D = 9.5 × 10−15  e 26 mV − 1
  = 75×30 (β = Ai )
I D = 6.84 ×1011 ×10 −15 = 2250
105. Except at high frequencies of switching, nearly
I D = 6.84 × 10 −4 all the power dissipated in the switch mode
ID = 0.684 mA operation of a BJT occurs, when the transistor
is in the
102. As compared to CE amplifier, the frequency (a) Active region
response of an emitter follower is (b) Blocking state
(a) Worse (b) Better (c) Hard saturation region
(c) Similar (d) None of these (d) Soft saturation region
UJVNL AE-2016 IES-2016
Analog Electronics 317 YCT
Ans. (c) : In the hard-saturation region, the on time Therefor it behaves like a short circuit, it increase the
duration is more. So, the power dissipation occurs in base current of the transistor due to which the current
large amounts as the current is maximum. gain ( β ) reduces.
In the cut-off region current is zero. So, no power
dissipation occurs in this region during the switched
mode operation of BJT.
106. Upper 3 dB cut-off common emitter amplifier
depends on
(a) E-B junction capacitance
(b) C-B junction capacitance
(c) Capacitances of both junctions
109. To get higher cut-off frequency in a BJT, base
(d) Coupling capacitor capacitance sheet resistance should be
IES-2015 (a) low
Ans. (c) : Upper 3dB cut-off common emitter amplifier (b) high
depends on capacitances of both junction. (c) equal to cut-off frequency
(d) zero
IES-2014
Ans. (a) : To get higher cut-off frequency the base sheet
resistance should be low.
1 1
f= ,f ∝
2πRC RC
R = resistance and C = capacitance
Large area bipolar transistor can have a very non-
107. Consider the following statements in respect of uniform current distribution due to the sheet resistance
an R-C coupled transistor amplifier: of the base layer.
1. The low frequency response is determined 110. For common-collector amplifier, the current
by the transistor junction capacitors. gain (A1) is
2. The high frequency response is limited by 1 + h fe
coupling capacitors. (a) 1 + hfe (b)
1 + h oe R L
3. The Miller capacitance reduces the gain at
high frequencies. 1 + h fe 1 + h fe
(c) (d)
4. As the gain is increased the bandwidth gets h oe h ie 1 + h ie R L
reduced. IES-2012
Which of the above statements are correct? Ans. (b) : The general equation for the current gain of
(a) 1 and 2 (b) 2 and 3 small signal analysis of a transistor amplifier.
(c) 3 and 4 (d) 1 and 4 −h f
IES-2015, 2003 A I = .............(i)
1 + h oe R L
Ans. (c) : R-C coupled transistor amplifier-
The Miller capacitance reduces the gain at high For common collector amplifier
frequencies h f = − (1 + h fe ) ...............(ii)
As the gain is increased the bandwidth gets reduced. Put the value equation (ii) in equation (i)
The low frequency response is determined by 1 + h fe
coupling capacitor and bypass capacitor. AI =
The high frequency response is determined by shunt 1 + h oe R L
capacitor (junction capacitor). 111. In the below circuit the optimum low frequency
Above both statements is correct. compensation is obtained when
108. The current gain of bipolar transistor drops at
high frequency because of
(a) Transistor capacitances
(b) High current effects in the base
(c) Parasitic inductive elements
(d) The early effect
IES-2014
Ans. (a) : The gain of a bipolar transistor, drops at high (a) C1R1 = RE CE (b) C1R1 = CCRi
frequency because of the interelectrode capacitances. (c) C1 ( R C R1 ) = CC R i (d) C1 ( RC R1 ) = RECE
As we know that at high frequency range, the reactance
of CC becomes quite small. IES-2011
Analog Electronics 318 YCT
Ans. (c) : Above circuit the optimum to frequency
compensation is obtained when-
It is used to extensively to improve the bandwidth of the
system.
Condition for low frequency compensation,
CL R L = Ci R i .............(i)
According to given circuit
CL = C1
R L = R1 || R C
(a) CS, CE, internal junction capacitance of
Put the value in equation. transistor
C L R L = Ci R i , Ci = CC (b) Strong wiring capacitance (CW), CC
C1 ( R1 || R C ) = CC R i (c) CS, CE, CC
(d) CS, CE only
112. A common emitter transistor amplifier has a
IES-2007
collector load of 10 kΩ. If its hfe = 100 and
Ans. (c) :
hie = 2 kΩ(hre ≈ hoe ≈ 0), the voltage
amplification of the amplifier is nearly equal to
(a) 500 (b) 200
(c) 100 (d) 50
IES-2011
Ans. (a) : In common emitter transistor h-parameter
given as,
R L = 10 kΩ, h fe = 100
h ie = 2 kΩ = Ri
h fe R L Lower cut off frequency depend on CE emitter bypass
CE amplifier voltage gain, A v = −
h ie capacitor, CS source capacitance and CC coupling
capacitor. “3 dB less than at midrange is called the
−100 × 10 × 103 lower cutt of frequency”
=
2 × 103 115. A CE-amplifier has RL = 10kΩ. Given
A v = −500 hie = 1kΩ, hfe = 50, hre = 0 & 1/hoe = 40 kΩ.
A v = 500 What is the voltage gain?
(a) – 500 (b) – 400
113. Which of the transistor models is most (c) – 50 (d) – 40
preferred for the analysis of a transistor circuit IES-2015, 2006
both at mid-band at high frequencies?
Ans. (b) : The general equation for the current gain of
(a) h-parameter model (b) y-parameter model
small signal analysis of transistor amplifier
(c) s-parameter model (d) hybrid π-model According to given question
Nagaland PSC CTSE (Degree)-2017, Paper-II
R L = 10kΩ h ie = 1kΩ h fe = 50
IES-2009
1
Ans. (d) : Hybrid π model is the most preferred for the h re = 0 and = 40kΩ
analysis of the transistor circuit both at mid-band at h oe
high frequency. Av = ?
The hybrid- π-model used for analyzing the small signal − h fe 50
behaviour of BJT and FET Ai = =−
1 + h oe R L 1× 10 × 103
Hybrid π model – 1+
40 ×103
−50
= = −40
5
4
Z −40 × 10k
A v = Ai ⋅ L =
114. For the amplifier shown in the figure given Zin 1k
below, the lower cut-off frequency depends on
A v = −400
which of the following?
Analog Electronics 319 YCT
116. An amplifier circuit is shown in the given figure:117. In a junction transistor biased for operation at
emitter current 'IE' and collector current 'IC'
the trans conductance 'gm' is
(a) kT/qIE (b) qIE/kT
(c) IC/IE (d) IE/IC
IES-1999
Ans. (b) : Trans-conductance mathematically defined as
the ratio of the change in collector current to thermal
The voltage gain (V0/Vs) is: voltage
(a) 4/3.33 (b) 100 I
(c) 150 (d) 160 gm = E
VT
IES-2000
I E = Emitter current
Ans. (d) : D.C analysis
Capacitor work as open circuit- VT = Thermal voltage
IE
gm =
kT
q
qI
gm = E Where, k= [ Boltzmann constant ]
kT
118. If Rs is the source resistance, the output
30 × 103 × 60 × 103
R Th = = 20kΩ resistance of an emitter-follower using the
90 × 103 simplified hybrid model would be
12 × 30 ×103 R s + h ie h + Rs
VB = = 4V (a) (b) ie
90 × 103 1 + h fe h fe
V − VBE 4 − 0.7 1 1
IE = B = = 1mA (c) R s + (d)
RE 3.3k h fe h 0e
h FE = 150 = β IES-1998
β is very Ans. (a) : Emitter follower also known as common
IC = β IB collector configuration.
It is used for impedance matching it is the ratio of
∴ β↑ then I B ↓ (Very low) emitter current to base current.
Assume IB is neglected, I
I E = IB + IC (I B = 0) γ= E
IB
IE = IC =1mA Phase shift between input and output is 0º
Trans-conductance CC configuration
I 1mA
gm = C = (at room temperature VT =25mV)
VT 25mV
gm = 40mA/V

Output resistance of an emitter follower using the

V0 = −g m .Vπ .R L simplified hybrid model would be
V0 = −g m .VS .R L {Vπ = VS } R + h ie v o
Ro = S =
1 + h fe io
V0
= −40 × 10−3 × 4 ×103 119. A trans conductance amplifier has
VS
(a) High input impedance and low output
V0 impedance
= −40 × 4
Vs (b) Low input impedance and high output
impedance
V0
= −160 (c) High input and output impedances
VS (d) Low input and output impedance.
Voltage gain = 160 IES-1998
Analog Electronics 320 YCT
Ans. (c) : The trans-conductance amplifier convert an Vi
=  h ie + (1 + h fe ) R e 
input of voltage to an output of current. It is also called Ib 
a current to voltage converter. V
A trans-conductance amplifier has high input and output Where, i = R i
Ib
impedance.
output current R i = h ie + (1 + h fe ) R e
gm =
output voltage 122. Consider the following statements regarding
It is used in bipolar junction transistor in order to the time-base voltage of an oscilloscope: It can
measure its sensitivity. be generated using
1. Miller sweep circuit
120. Match List-I (Models of BJT) with List-II
2. boot-strap integrator circuit
(Applications) and select the correct answer
3. time-delay circuit
using the codes given below the lists:
4. a controlled circuit
List-I List-II Of these statements
A. Hybrid model 1. Microwave (a) 1, 2 and 3 are correct (b) 1 and 2 are correct
measurements (c) 2, and 4 are correct (d) 1, 3 and 4 are correct
B. Hybrid pi-model 2. Coupled diode IES-1997
C. S-parameter 3. Low frequency Ans. (a) : The generator which is used for generating the
D. Ebers-Moll model 4. High frequency linear variable voltage concerning time is known as the
Codes: time base generation these wave are used in cathode ray
tube for deflecting the beam in a horizontal direction.
A B C D
It can be generated by.
(a) 4 3 1 2
Miller sweep circuit.
(b) 3 4 2 1 Boot strap integrator circuit
(c) 3 4 1 2 Time-delay circuit
(d) 4 3 1 2 123. In the circuit shown in the given figure, assume
IES-1998 that the capacitor C is almost shorted for the
Ans. (c) : Hybrid model is used for low frequency. frequency range of interest of the input signal.
Hybrid π model is used for high frequency because it Under this condition, the voltage gain of the
amplifier will be approximately.
provides more accurate result than other two models.
hfe = 100, hie = 1 kΩ
S-parameters applicable for microwave frequency
measurement. S-parameter are frequency domain
quantities which are commonly used to model
behavior of RF circuit components.
Ebers-moll model is used coupled diode.
121. The approximate value of input impedance of a
common emitter amplifier with emitter
resistance Ri is given by
(a) 0.33 (b) 0.5
(a) hie + A1Re (b) hie + (1 + hfe) Re
(c) 0.66 (d) 1
(c) hie (d) (1 + hfe) Re
IES-1996
IES-1997
Ans. (d) : Given,
Ans. (b) :
hfe = 100, hie = 1kΩ
Re = RL=0.66 kΩ
V −h fe × R L
AV = 0 =
VB h ie + (1 + h fe ) R e
−100 × 0.66k
=
1k + (1 + 100 )(1k )
−100 × 0.66 × 103
Applying KVL =
1× 103 + (1 + 100 ) 0.66 ×103
Vi − h ie I b − Ie R e = 0
Vi = h ie Ib + ( I b + h f e I b ) R e 66 × 103 1
= =
66.66 × 10 1.01
3

Vi =  h ie + (1 + h f e ) R e  I b Av ≃ 1

Analog Electronics 321 YCT

124. For the transistor amplifier in the given figure, hie hre hfe hoe
the voltage amplification is approximately. (a) 100 Ω 10–1 50 1 ms
(b) 5 kΩ 10–4 200 20 ms
(c) 5 kΩ 0 20 3 ms
(d) 100 kΩ 102 100 10 ms
IES-1995
Ans. (b) : At 1mA collector current, for small signal
Audio transistor in the CE configuration.
The h-parameter for CE configuration value-
Input impedance (hie)- order is of 5 kΩ
(a) 100 (b) 84
Reverse voltage gain (hre)- order in 10–4
(c) 0.723 (d) –2
Current gain (hfe)-High value (200)
IES-1995
Output admittance (hoe)-order is 20 ms
Ans. (d) : Given,
hfe = 100, hie = 1kΩ 127. The equivalent circuit of a CE transistor is
Re = 0.5kΩ represented by
V −h fe × R L
AV = 0 =
VB h ie + (1 + h fe ) R e
−100 ×1k
= (a)
1k + (1 + 100 )( 0.5k )
−100
Av =
1 + 50.5
−100
Av = ≃ −2
51.5
125. The small signal input impedance of a (b)
transistor when the output is shorted for the
measuring signal, is (where the symbols have
their usual meaning).
V1 V1
(a) h11 = (b) h12 =
i1 v 2 =0
i 2 i =0
1
(c)
i i
(c) h 21 = 2 (d) h 22 = 2
i1 v 2 =0
v2 i1 = 0

IES-1995
Ans. (a) : Small signal input impedance of a transistor
when the output is shorted,
The hybrid parameter model (d)
The h-parameter model of BJT is defined by two port
network as.

IES-1994
Ans. (b) : CE transistor represented by-
V1 = h11I1 + h12 V2 .......... (i)
I 2 = h 21I1 + h 22 V2 ............ (ii)
The input impedance h11 / I1
V1
h11 =
I1 V2 = 0

126. Typical values of h parameters, at about 1 mA VB = I B h ie + h re VC

collector current, for small signal audio
IC = h f e I b + h oe VC
transistors in the CE configuration are
Analog Electronics 322 YCT
128. The 'h' parameter equivalent circuit of a 131. α cut-off frequency of a bipolar junction
junction transistor is valid for transistor
(a) high frequency, larger signal operation (a) Increase with the increase in base width
(b) high frequency, small signal operation (b) Increase with the increase in emitter width
(c) low frequency, small signal operation (c) Increases with the increase in collector width
(d) low frequency, larger signal operation (d) Increase with decrease in the base width
TSPSC Manager (Engg)-2015
Nagaland PSC (Degree)-2018, Paper-II
IES-1993
GATE-1993
Ans. (c) : The h-parameter are used to analyzing
Bipolar junction Transistor or BJT. The ‘h’ parameter Ans. (d) : α = Common base dc current gain.
equivalent circuit of a junction transistor is valid for low Ic
frequency, small signal operation. α=
Ie
129. A transistor has h-parameter as
hie = 10kΩ, hre = 20 × 10–4, hfe = 100, hoe = 25 µS. for dc → f = 0
The hib for this transistor will be But take, α = α0 = at zero frequency (are at low
(a) 100Ω (b) 99.01Ω frequency and mid frequency).
(c) 5MΩ (d) 101KΩ So,
IES-1991 At low frequency and Mid frequency the value of α, a
Ans. (b) : Given, common base dc current gain is going to be constant.
h ie = 10kΩ, h re = 20 ×10 −4 But a high frequency parasitic capacitance.
At High frequency,
h fe = 100, h oe = 25µS.
α0
h ie α (t) =
h ib =  f 
1 + h fe 1+j  
 fα 
10 ×103
h ib = Where fα is the cut off frequency at which α0 drops to
1 + 100 0.707
10000 So, α are reduces then fα cut off frequency also reduces.
=
101 Q BJT act as a amplifier, when in active region.
h ib = 99.01Ω
130. The bandwidth of an n-stage tuned amplifier,
with each stage having a bandwidth of B, is
given by
(a) B/n (b) B / n
(c) B 21/ n − 1 (d) B / 21/ n − 1
As |VCB| are increases then with of potential barrier at
Nagaland PSC (Degree)-2018, Paper-II
collector base junction is going to increases. Then Base
GATE-1993 width are reduces which base current reduces and
Ans. (c) : Given, collector current IC will be increases.
Q Bandwidth of independent stage = β
DB
n-state tuned Amplifier, such of cascaded n number, fα =
πWB2
Q By using cascading, gain will be increases but 132. A Darlington stage is shown in the figure is, if
bandwidth decreases. the trans-conductance Q1 is gm1 and Q2 is gm2,
So, then the overall trans-conductance gm is given
as a going to more and more number of stages, by
bandwidth are going to reduces further and further but
gain will be increases. Bandwidth lesser than the
previous value. If Assume that all stage connect to
identical nature,

( BW )n = B
1
2 n −1
because 21/ n − 1 < 1 For n > 1
If n = 1 1 (a) gm1 (b) 0.5 gm1
n=2 0.643 (c) gm2 (d) 0.5 gm2
n=3 0.510 GATE-1996
Analog Electronics 323 YCT
Ans. (c) : Given,
A 2 + A3 + .... A 22 + A32 + .....
Trans-conductance, g m1 and g m2 (a) (b)
A1 A1
IC1 I C2
Q g m1 = , g m2 = A 22 + A32 + ..... (A 22 + A32 + .....)
Vbe1 Vbe2 (c) (d)
Q Combined trans-conductance, A12 + A 22 + A 32 ..... A1
I C2 GATE-1998
g mc = Ans. (b) : Given, Distorted sinusoidal has the amplitude
Vbe1 + Vbe2
'A' Assume, A2, A3, ............
I C2 for linear circuit,
g mC = If (Vbe1 = Vbe2 )
2Vbe2
g m2
g mC = = 0.5g m2
2 And for non linear circuit,
But for ideal transistor, It is answer incorrect.
I b ∝ Vbe ⇒ I b = Ib1 e Vbe / ηVT
IC ∝ I b ⇒ IC = βI b
Q For non linear output voltage,
V0 = A1Vm sin ωt + A 2 Vin2 + A 3 Vin3 + ....
↓ ↓
2nd 3rd
So, Total harmonic distortion,
A 22 + A32 + ......
=
A1
And, Vbe2 ≠ Vbe1
134. A multistage amplifier has a low-pass response
with three real poles at s = – ω1, – ω2 and ω3. The
approximate overall bandwidth B of the
amplifier will be given by
1 1 1 1
(a) B = ω1 + ω2 + ω3 (b) = + +
B ω1 ω2 ω3
(c) B = (ω1 + ω2 + ω3)1/3 (d) B = ω12 + ω22 + ω33
GATE-1998
QβI b2 = β(1 + β)I b1 Ans. (b) : As we know, the approximate overall
bandwidth of the amplifier,
Vbe1 = I b1 R i .....(i)
1 1 1 1
Vbe2 = I b2 .R i = + +
B ω 1 ω 2 ω3
= Ie1 R i Cascading of amplifier result in decrease of higher cut
off frequency and increase in lower out-off frequency
= (1 + β ) I b1 R i ......(ii)
f H ↓ an f L ↑
If, Assume from equation (i) and (ii),
BW = f H − f L
Vbe2 = (1 + β) Vbe1
So, bandwidth will be decrease BW ↓
So, Total trans-conductance
135. In the cascode amplifier shown in the figure, if
I (Combined) the common-emitter stage (Q1) has a trans-
gm = c
Vbe (Combined) conductance gm1, and the common base stage
I C2 (Q2) has a trans-conductance gm2, then the
= ≅ g m2 overall trans-conductance g (=i0/Vi) of the
Vbe1 + Vbe2 cascode amplifier is
g m (overall) = g m2

133. A distorted sinusoid has the amplitude, A1 , A2 ,

A3 , .... of the fundamental, second harmonic,
third harmonic, ..... respectively. The total
harmonic distortion is
Analog Electronics 324 YCT
 (a) gm1 (b) gm2
g g
(c) m1 (d) m2 (a)
2 2
GATE-1999
Ans. (a)

(b)

(c)

For Transistor Q1,

ic
gm1 = 1 .....(i)
Vi
and for transistor Q2, (d)
i
g= 0
Vi
Q Transistor are ground, i 0 = i c1 = i e1 GATE-2002
Ans. (b) : Given,
i e1
So, g = ......(ii) Three identical RC-coupled transistor amplifiers are
Vi cascaded.
from equation (i) and (ii) Cascading amplify always result in-
g = g m1 • Increases gain and
Therefore the trans-conductance of the cascode • Bandwidth will be decrease.
amplifier is g m1 . Q BW = f H − f L
136. The current gain of a BJT is So, BW ↓= (f H − f L ) ↓
gm
(a) gmro (b) Given, fL = 20H and fH= 1kHz for single stage, n = 3
ro
fL 20
gm So, f L = = = 39.2Hz
(c) gmrπ (d) 2 −1
1/ n
2 −1
1/ 3

rπ
Nagaland PSC CTSE (Degree)-2017, Paper-II f H = f H 21/ n − 1 = 21/ 3 − 1 × 1kHz = 0.5kHz
GATE-2001 138. The current ib through the base of a silicon npn
Ans. (c) : In π model, hfe is referred to β. transistor is 1 + 0.1 cos (10000 π t) mA. At 300
Q Current gain of a BJT β = ri g m K, the rπ in the small signal model of the
Where r = r transistor is
i π

β = rπ g m
137. Three identical RC-coupled transistor
amplifiers are cascaded. If each of the
amplifiers has a frequency response as shown
in the figure, the overall frequency response is
as given in
(a) 250 Ω (b) 27.5 Ω
(c) 25 Ω (d) 22.5 Ω
GATE-2012
Ans. (c) : Given,
ib = 1+0.1 cos (10000 πt) mA
DC current IB = 1mA

Analog Electronics 325 YCT

 (c) Collector current is to be constant
(d) Base current is to be constant
Nagaland PSC CTSE- 2015, Paper-II
Ans. (a)

rπ = small signal resistance between base to emitter,

Vbe
rπ = ....(i) Vbe = h iei b + h re Vce
ib
For a BJT amplifier mode, i c = h fei b + h oe Vce
Ic  Ie = I0 (eVbe / ηVT ) .....(ii) If d.c. base current ib=0 then, hre and hoe can be solved.
V
Total Instantaneous current (DC+AC) is, h re = be ( at i b = 0 )
i C = i C + IC = I0 (e VBE / ηVT ) = I0 (e(Vbe + VBE ) / VT ) Vce
And h oe = i c / Vce (at ib = 0)
i C = I0 .eVBE / VT .eVbe / VT = i b + IC (IC= DC collector
current) 142. The ideal value of stability factor of a biasing
Sine, Vbe << VT, circuit for transistor is:
(a) 0.7 (b) 1
 V 
IC 1 + be  = i C + IC (c) 2 (d) 10
 VT  OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
V Ans. (b) : Stabilization is about making the Q-point
IC . be = i C independent of changes in temperature and changes in
VT transistor parameters.
IC i  IC  If ICO, VBE and β changes simultaneously then net
= C Q g m =  change in IC.
VT Vbe  VT 
∂I ∂I ∂I
So, ∆IC = C ∆Ico + C × ∆VBE + C ∆β
∂ICO ∂VBE ∂B
iC I
gm = = C ............(iii) ∂IC
Vbe VT Where, = S → current stability factor
From equation (i), (ii) and (iii) ∂ICO
V VT Sideal = 1
rπ = T = (Q VT = 25mV )
I B dc current
25mV
rπ = = 25Ω
(iv) Analysis of FETs circuits
1mA
139. In the high frequency hybrid-π model of a CE 1. The source of a silicon (ni=1010 per cm3) n-
transistor, the conductance gbe is channel MOS transistor has an area of 1 sq µm
(a) hfe/gm (b) gm/hfe and a depth of 1 µm. If the dopant density in
(c) gm/hie (d) hie/gm the source is 1019/cm3, the number of holes in
the source region with the above volume is
Nagaland PSC- 2018, Diploma Paper-II approximately
Ans. (b) : For common emitter amplifier - (a) 107 (b) 100
(c) 10 (d) 0
g
the input conductance g be = m BPSC Asst. Prof. - 12.04.2022
h fe GATE-2012
140. A transistor has hfe = 50, its hfc will be Ans. (d) : Given,
(a) –50 (b) +50 ni = 1010/cm3
A = 1×10–12 m2
(c) –51 (d) +51
d = 10–6m
Nagaland PSC CTSE- 2015, Paper-II Volume of given device,
Ans. (c) : Given hfe = 50 V = A ×d
Q hfc = –(1+hfe) = – (1+50) = –51 V = 10–12×10–6
V = 10–18m3
141. The condition necessary to calculate hoe of
V = 10–12cm3
transistor is that For the semiconductor-
(a) D.C. base current is to be zero
n i2 = n 0 p 0
(b) Base to emitter voltage is to be constant
Analog Electronics 326 YCT
 n i2 1020 Ans. (c) : According to figure we can say that drain is
P0 = = = 10 / cm3 shorted to gate so that's why both MOSFETs are in
n 0 1019 saturation region.
so total number of holes is, So,
P = P0×V I DSN = ISDP
= 10 ×10–12
µ n Cox  W  µ C W
= 10–11 ×   ( VGSN − VTN ) = P ox   ( Vgs − ( VT ) )
2 2

which is approximately equal to zero. 2  L n 2 L

2. A FET has a drain current of 4 mA. If IDSS = 8
300 × 1( V0 − 1) = 40 × 5 ( 4 − V0 − 1)
2 2
mA, VGS(off) = – 6V. The value of VGS will be
(a) – 6 V (b) – 1.76 V 3 ( V02 + 1 − 2V0 ) = 2 ( 9 + V02 − 6V0 )
(c) – 5.24 V (d) – 1.5 V
UPPSC ITI Principal/Asstt. Director-09.01.2022 V02 + 6V0 − 15 = 0
Ans. (b) : As given that, 6 ± 36 + 4 × 15
VGS( off ) = −6V = VP V0 =
2
I D = 4mA, I DSS = 8mA V0 = 1.898V, − 7.89V ( Vo can not − ve )
2
 VGS  ∴ V0 = 1.8V  2V
I D = I DSS 1 − 
4. Consider an ideal long channel nMOSFET
 VGS( OFF) 
(enhancement-mode) with gate length 10 µm
and width 100 µm. The product of electron
2
 V 
4mA = 8mA 1 − GS  mobility (µn) and oxide capacitance per unit
 −6 
2
are (Cox) is µnCox = 1 mA/V2. The threshold
1  VGS  voltage of the transistor is 1 V. For a gate-to-
= 1+
2  6  source voltage VGS = [2 – sin (2t)] V and drain-
to-source voltage VDS = 1 V (substrate
1  VGS  6 + VGS
= = 1 +  = 0.707 = connected to the source), the maximum value of
2  6  6 the drain-to-source current is _______.
4.242 = 6 + VGS (a) 40 mA (b) 20 mA
VGS = 4.242 − 6 (c) 15 mA (d) 5 mA
= –1.758V GATE-2022
 −1.76 V Ans. (c) : Given, µ n C ox = 1mA / V 2 , VT = 1V
3. Consider the CMOS circuit shown in the figure W
(substrates are connected to their respective VDS = 1V, = 10 µm
L
sources). The gate width (W) to gate length (L)
VGS = [ 2 − sin 2t ]
W
ratios   of the transistors are as shown.
 L  VGS = 2 − 1 = 1V
GSmax = 2 − ( −1) = 3V
Both the transistors have the same gate oxide V
capacitance per unit area. For the pMOSFET,
the threshold voltage is –1 V and the mobility VDS = 1V
cm 2 VDS < VGS − VT [ for linear ]
of holes is 40 .
V.s W
( VGSmax − VT ) VDS − VDS2 
1
For the nMOSFET, the threshold voltage is 1 V I D max = µ n Cox 
L 2 
cm 2
and the mobility of electrons is 300 .  1 
V.s ⇒ 1mA / V 2 ×10  2 − 
The steady state output voltage V0 is _______.  2
= 10 [1.5]
= 15mA
5. In the circuit shown in the figure, the
transistors M1 and M2 are operating in
saturation. The channel length modulation
coefficients of both the transistors are non-
zero. The transconductance of the MOSFETs
(a) equal to 0 V (b) more than 2 V M1 and M2 are gml and gm2, respectively, and
(c) less than 2 V (d) equal to 2 V the internal resistance of the MOSFETs M1
GATE-2022 and M2 are ro1 and ro2, respectively.
Analog Electronics 327 YCT
 Replace M2 with small signal model.

Vout −g m2 Vgs ( r02 || R eq )

Ignoring the body effect, the ac small signal
 ∂V  =
voltage gain  out  of the circuit is Vin Vgs
 ∂Vin 
 1 
 1  A V = −g m2  r02 || || r01 
(a) –g m2  ro2  (b) –g m2 ( ro1 ro2 )  g m1 
 ml
g 
6. For an n-channel silicon MOSFET with 10 nm
 1   1  gate oxide thickness, the substrate
(c) –g m2  ro1 ro2  (d) –g ml  ro1 ro2 
 g ml   g m2   ∂VT 
sensitivity 
 ∂ V 
is found to be 50 mV/V at a
GATE-2021  BS 
Ans. (c) : MOSFET M2 acts as common source substance voltage VBS = 2V, where VT is the
amplifier.
threshold voltage of the MOSFET. Assume
that, VBS >> 2φB , where qφB , is the separation
between the Fermi energy level EF and the
intrinsic level Ei in the bulk. Parameters given
are
Electron charge (q)=1.6×10–19C
Vacuum permittivity ( ε 0 ) =8.85×10–12F/m
Relative permittivity of silicon ( εsi ) = 12
Relative permittivity of oxide ( εox ) = 4
The doping concentration of the substrate is
(a) 7.37×1015 cm–3 (b) 4.37×1015 cm–3
Drain to gate connected MOSFET M1 acts as load. 15
(c) 2.37×10 cm –3
(d) 9.37×1015 cm–3
Gate and drain are shorted of MOSFET, we can replace GATE-2021
directly MOSFET by resistance.
Ans. (a) :
VT = VT0 + γ ( | VBS | + | 2φB | − | 2φB | ) ....(i)
VT0 → Threshold voltage |VBS | = 0V

2εs qNa
γ= ……(ii)
ε0x
dVT γ
= = 50mV / V .....(iii)
d | VBS | 2 | VBS | + | 2φB |
For given circuit AC equivalent is as shown. γ
50 × 10−3 V / V = (Q| VBS |>>| 2φB |)
2 2
γ = 0.141
From equation (iii)
2εs qNa t ox 2εs qNa
γ= =
εox εox
t ox
t ox 2εs qNa
γ= ..(iv)
εox

Analog Electronics 328 YCT

 t 
2 tox = 500×10–10 m = 500×10–10 ×39370mil
γ =  ox  .2εs [Link]
2
= 1.97×10–3 mil
 εox  8.99 × 10−16 F / mil
2 Cox =
ε  1 1.97 × 10−3 mil
Na = γ 2  ox  .
 ox 
t 2 ε sq = 4.56×10–13 F/mil2
= = 0.456 ×10–12 F/mil2
2
 4 × 8.854 × 10−14  1 Cox = 0.4PF / mil2
(0.14) 2 .  −9 2  −4
 10 × 10 × 10  2 × 12 × 8.854 × 10 ×1.6 × 10−19
9. For enhancement-type n-channel MOSFET
Na = 7.329 ×1015 cm −3 with drain current ID =10 mA, VGS = 8 V and
7. Maximum drain current IDSS for FET is define VT = 2 V, the device constant k is
when (a) 0.139 mA V 2 (b) 0.278 mA V 2
(a) Vgs = Vds and Vds>Vp
(b) Vgs ≠ 0 and Vds > Vp (c) 0.387 mA V 2 (d) 0.556 mA V 2
(c) Vgs = 0 and Vds > Vp ESE-2021
(d) Vgs > 0 and Vds <Vp Ans.(b) : Let us assume that MOSFET is biased in the
RPSC ACF & FRO 23.02.2021 saturation region-
2
 V  I D = K ( VGS − VT )
2
Ans. (c) : I D = I DSS  1 − GS 
 VP 
Given, I D = 10mA
For maximum drain current-
VGS = 8V
VGS = 0
ID = IDSS VT = 2V
and ID 10 × 10−3
VDS > |VP| K= =
( VGS − VT ) (8 − 2 )
2 2
The region between VP and VDS(max) (breakdown
voltage) is called the constant current region or active
K = 0.278 × 10 −3
region.
∴ This device constant K is 0.278mA V 2
10.

8. A monolithic metal oxide semiconductor

(MOS) non-polarized capacitor which is a
parallel plate capacitor with SiO2 as dielectric.
A surface thin film of metal (aluminum) is the
top plate. The bottom plate consists of the
heavily doped n* region that is formed during
emitter diffusion. What is the typical value of
capacitance for an oxide thickness of 500 Å of
this MOS capacitor?
Take the permittivity of dielectric (εr) as 4.
(a) 0.1 pF/mil2 (b) 0.2 pF/mil2
2
(c) 0.3 pF/mil (d) 0.4 pF/mil2 In the above circuit ID is
ESE-2021 2
 VGS 
εox (a) I D = I DSS 1 − 
Ans.(d) : MOS capacitor Cox =  VGS( off ) 
t ox  
ε ox = 4 × 8.85 × 10−12 F / m  VGS 
= 4×8.85×10–12 F/39370 mil (b) I D = I DSS 1 − 
{Q 1m = 39370mil}  VGS( off ) 
= 8.99 ×10–16F/mil  

Analog Electronics 329 YCT

  VGS 
VGS –VTh = 1–0.5 =0.5V
(c) I D = I DSS 1 −  For t > 0 S1 is open and S2 is closed so
 VDS( off ) 
  VGS = 3 – 4 = –1V
2 then Vth > VGS that MOSFET is OFF condition
 VGS 
(d) I D = I DSS 1 −  So drain current ID = 0µA
 VDS( off ) 
  12. An n-channel MOS transistor is made on a p-
DMRC AM S&T-2020 type substrate with Na = 1015 cm–3 find
2 approximate depletion charge per unit area
 V  (Qd) at strong inversion.
Ans. (a) : I D = I DSS 1 − GS 
 VGS( off ) 
  {
ln(10) = 2.3, 0.046  0.215,n i = 1010 cm −3 }
11. In the given circuit, S1 switch remains closed (a) –6.9×10–8 C/cm2 (b) 6.9×10–8 C/cm2
and S2 remains open for the long time. At t = 0, –8
(c) –3.4×10 C/cm 2
(d) 3.4×10–8 C/cm2
S1 opens and S2 closes and remain in this ISRO Scientist Engg. -2020
position for the long time. Find drain current
for t < 0 and t >> 0 respectively if, µnCox = 100 Ans. (c) : Given,
µA/ V2 and aspect ratio = 2. ln (10) = 2.3, 0.046 = 0.215, n i = 1010 cm −3
N a = 1015 cm–3
Q d = −2 εsi qN A φF
Where,
εsi = 11.7ε 0 = 11.7 × 8.85 ×10 −14 F / cm
εsi = 103.545 × 10−14 F / cm
kT  N A 
φF = ln  
q  ni 
(a) 600 µA, 0 µA (b) 600 µA, 25 µA
KT
(c) 600 µA, –25 µA (d) 0 µA, 600 µA at room temperature = 25ºC is 26mV
ISRO Scientist -2020 q
Ans. (a) : Threshold voltage (Vth) = 0.5V φF = 0.299V
µ n Cox = 100 µA/V2
W Q d = −2 103.545 × 10−14 ×1.6 × 10−19 ×1015 × 0.299V
aspect ratio   = 2
L Q d = −1.4 ×10 −8 C / cm 2
For t < 0 Q d  −3.4 ×10 −8 C / cm 2
Switch S1 is closed and S2 is open
VGS = VG–VS 13. For a p-channel Si FET, Na = 3×1016 cm–3, Nd
= 3V– 0 = 1018 cm–3. Channel thickness dimension is a =
= 3V 0.33 µm. Find approximate pinch-off voltage
VDS = 2–0 = 2V Vp. {ni = 1010 cm–3, VT = 26 mV, ln (3) = 1.098}.
VGS –Vth = 2.5V (a) 2.5 V (b) 1.7 V
VDS < (VGS–Vth) (c) 4.2 V (d) 3.6 V
MOSFET operates in linear region then current across ISRO Scientist Engg. -2020
MOSFET will be Ans. (b) : Given,
VT = 26mV
 W  V2 
I DS = µ n Cox   ( VGS − VTh ) VDS − DS  ln = 1.098
 L  2  ni = 1010cm–3
 ( 2)  Channel thickness dimension (a) = 0.33µm
2

= 100 × 2  2.5 × 2 −  N a = 3 × 1016 / cm3 = 3 × 10 22 / m3

 2 
N d = 1018 / cm3
= 200 × 3
IDS = 600µA Pinch off voltage (VP) =
That case VD = 4V, VS = 2V qN a a 2
− Vbi
VDS = VD–VS 2ε
= 4–2 = 2V N N
VGS = VG –VS Vbi = VT l n a 2 d
= 3–2 = 1V ni

Analog Electronics 330 YCT

 3 × 1016 ×1018 Ans. (b)
Vbi = 26 × 10−3 ln
(10 ) 10 2

3 ×1034
= 26 × 10−3 ln
1020
−3
= 26 × 10 ln 3 × 1014
= 0.866V
qN a a 2 Given, gm = 4mA/V
VP = − 0.866V
2ε rds = 40kΩ

=
(1.6 ×10 ) × 3 ×10
−19 16
(0.33 × 10 −6 ) 2
− 0.866V
RD = 10 kΩ
RS = 50 Ω, Cgs = 4pF, Cgd = 2pF
2 × 8.854 × 10 −14 ×11.7 1 1 1
1.6 × 10−19 × 3 ×1022 × 0.1089 × 10−12 = +
= − 0.866V R L R D rds
17.7 × 10−12 × 11.7 1 1 1
522.72 = +
= − 0.866V R L 10 40
207.09
RL = 8 kΩ
 1.7V
Voltage gain AV = –gm. RL
14. In a MOSFET, SiO2 breaks down at electric = −4mA / V × 8kΩ
field of the order of 5×106 V/cm. For a gate = –32A/V
oxide of thickness 1000 Å and channel
thickness of 2 µm, what is the maximum VGS it Input capacitance Ci = {Cgs + (1+ | A V |)Cgd }
= {4 + (1+ | −32 |) 2}
can withstand?
(a) 5 V (b) 10 V
(c) 100 V (d) None of the above = 4+(2+64)
ISRO Scientist Engg. -2020 = 4+66
Ans. (d) : Given, = 70pF
Electric field (Eox) = 5×106 V/cm 1
input frequency f in =
o
oxide thickness (tox) = 1000 A = 1000×10–8cm 2πCin .R in
channel thickness (tchannel) = 2µm R in = R S || ∞
V 1 1 1
Electric field (Eox) = ox = +
t ox R in 50 ∞
Vox Rin = 50Ω
5 × 106 =
1000 × 10−8 f in =
1
Hz
Vox = 5 × 106 ×1000 × 10−8 2 × 3.14 × 70 ×10−12 × 50
Vox = 5 ×109 ×10 −8 1000
f in = × 106 Hz
Vox = 50V 21.98
VGS = Vox + φS f in = 45.5MHz
Q φS is surface potential is not given 16. For a MOSFET satisfying the relationship
Hence VGS cannot be calculated. VDS < VGS - VTH , where the drain voltage is VDS,
15. For the given amplifier circuit, find the input the gate voltage is VGS, and the threshold
cut-off frequency. FET parameters are gm = voltage of the transistor is VTH, then the
4mA / V, Cgs = 4 pf, rds = 40 kΩ, Cgd = 2pF. transistor is said to operate in:
(a) Pinch off (b) Saturation
(c) Cut off (d) Triode region
UPMRC AM - 2020
Ans. (d) : We know that MOSFET operation in three
regions
(i) Cut off region
(ii) Triode/ohmic region
(iii) Saturation region
(a) 35.5 MHz (b) 45.5 MHz (i) Cut off region → VGS < Vth
(c) 90.5 MHz (d) 10.5 MHz
ISRO Scientist Engg. -2020 I D = 0
Analog Electronics 331 YCT
(ii) ohmic/ Triode region ⇒ VGS > Vth 18. In a direct-coupled FET switching circuit, RG =
2.2kΩ and VDS(on) = 200 mV. If a 2N4856 FET
VDS < VGS − Vth
is used with a 12V supply, calculate the value of
Current equation in ohmic region is RD (for 2N4856, rDS (on) = 25Ω).
W
I D = µ n Cox (a) 3.5kΩ
L (b) 2.5kΩ
 2
VDS  (c) 5.5kΩ
( VGS − Vth ) VDS − 
 2  (d) 1.5kΩ
(iii) Saturation region : VGS > Vth APPSC POLY. LECT. 14.03.2020
VDS > VGS − Vth Ans. (d) : Given, RG = 2.2 kΩ, VDS(on) = 200mV
The current equation for MOSFET in saturation is Q Supply voltage = 12V
1 W R DS( on ) = 25Ω
I D = µ n Cox ( VGS − Vth )
2

2 L
So option (d) Triode region is correct Answer.
17. A MOSFET is biased at a drain current of
0.5mA. If µn Cox = 100µA/V2. W/L = 10, and λ =
0.1V–1, the intrinsic gain gmr0 will be:
(a) 1 (b) 10
(c) 20 (d) 0.05
UPMRC AM - 2020
Ans. (c) : In saturation region the drain current of
MOSFET is
W
I D = µ n Cox   ( Vgs − VT )
1 2

2  L VDS( on )
The trans-conductance gm Drain current ( I D ) =
R D( on )
∂I W
g m = D ⇒ µ n Cox   ( Vgs − VT ) 200mV
∂Vgs  L =
25
The O/P resistance ( r0 ) is. = 8mV
V So, when used the supply voltage 12V, then drain
r0 = A
ID resistance in 2N4856 FET.
12
 1  RD =
V =
 A λ = 10  8 × 10−3
= 1.5kΩ
Now
19. The transconductance gm of an FET in the
W
I D = µ n Cox   ( Vgs − VT )
1 2
saturation region equals
2  L 2
-2I DSS  VGS  -2I DSS  VGS 
I D = 100µ × 10 ( Vgs − VT )
1 2 (a) 1-  (b) 1- 
2 VP  VP  VP  VP 

(V − VT ) = 1 -2I DSS  VGS 

1/2
I
[ I DSS X I DS ]
gs 1/2
(c) 1-  (d)
So now gm will be VP  VP  VP
∂I W
g m = D ⇒ µ n Cox   ( Vgs − VT ) ISRO Scientist Engg.-2011
∂Vgs  L Ans. (a) : VGS( off ) = Vp ( ID = 0 )
g m = 100 ×10 −6 ×10 × 1 ⇒ 10−3 S FET-
V 10  V 
2
r0 = A = = 20kΩ
ID 0.5mA I D = I DSS 1 − GS 
 Vp 

The intrinsic gain of MOSFET = g m r0
Where, I DSS = Saturation drain current
= 10 −3 × 20 × 103
= 20 And I DS = I DSS ( When VGS=0 )

Analog Electronics 332 YCT

 22. The given figure shown a composite transistor
consisting of a MOSFET and a bipolar
transistor in cascode

Q Trans-conductance,
ID
gm = The MOSFET has a trans conductance gm of 2
VGS
( )
VDS = constant
mA/V and the bipolar transistor has β  h fe of
Where gm unit = mA/Volt or A/V (mho)
∂  VGS  1 99. The overall trans conductance of the
gm = 1 − ×− composite transistor is
∂VGS  Vp  Vp
(a) 198 mA/V (b) 19.8 mA/V
 V  1 (c) 1.98 A/V (d) 1.98 mA/V
= 2IDSS 1 − GS  × − IES-1999
 Vp  VP
Ans. (d) :
−2I DSS  VGS 
gm = 1 − 
VP  VP 
20. For an n-channel MOSFET, if condention
parameter (k n ) is 0.249 mA/V 2 , gate to source
voltage VGS is 2VIN where VIN = 0.75V. The
current will be output current
(a) 0.160 mA (b) 0.150 mA gm =
Input voltage
(c) 0.140 mA (d) 0.170 mA
ISRO Scientist Engg.-2016 Where g m = Trans-conductance
Ans.(c): Given value, αI
Condention parameter (kn) = 0.249 mA/V2 gm = E ( I E = ID )
Vgs
Gate to source voltage VGS = 2VIN
Where VIN = 0.75V, ∵ connected Emitter to the drain of MOSFET
µ n = field-limited electron mobility  I  I
gm = α  D  ∵ D = 2m A V
Condition, VDS >> VGS − VT V  Vgs
 gs 
Then,
 β 
I D = k n ( VGS − VIN ) gm =   × 2m A V
2

 1+ β 
I D = 0.249 × 10−3 × [ 2 × 0.75 − 0.75]
2
99
= × 2 = 1.98m A V
 3 100
= 0.249 × 10 –3 × ( 0.75) =
2
 0.75 
 4 g m = 1.98m A V
9
= 0.249 × × 10 –3
 I 
16 Q IC = h fe IB = h fe  E 
I D = 0.140mA  1 + h fe 
21. The relation between ID and VGS in FET is h fe
(a) ID = IDSS (1-VGS/VP) (b) ID=IDSS (1-VGS/VP)2 IC = × (−g m VGS )
1 + h fe
(c) ID = IDSS (VGS/VP) (d) ID =IDSS (1-VP/VGS)
Mizoram PSC AE/SDO 2012-Paper-I IC h 99
= fe × g m = × 2mA / V
Ans. (b) : IDSS is drain to source current Vin 1 + h fe 1 + 99
2
 V  g m1 =
IC
=
99
× 2 = 1.98mA / V
I D = I DSS 1 − GS  Shockley’s equation
 VP  Vin 100

Analog Electronics 333 YCT

23. If the transconductance of MOSFET is 10 28. Consider an n-channel MOSFET with
mmho and its drain resistance is 3KΩ, its parameters Kn = 0.25 mA/V2, VTN = 1V, λ = 0,
voltage gain is Cgd = 0.04 pF and Cgs = 0.2 pF
(a) 0.3 (b) 3 If the transistor is biased at VGS = 3V, the unity
gain bandwidth of an FET will be
(c) 3.3 (d) 30
(a) 626 MHz (b) 646 MHz
Mizoram PSC AE/SDO 2012-Paper-I (c) 663 MHz (d) 683 MHz
Ans. (d) A V = g m R d IES-2020
AV = 10 ×10-3 ×3 ×103 Ans. (c) : Given- K n = 0.25mA / V 2
A V = 30 VTN = 1V
λ=0
24. gm of MOSFET is controlled by Cgd = 0.04 PF
(a) gate-source voltage
(b) drain-source voltage Cgs = 0.2 PF
(c) drain current Unity gain bandwidth FET will be-
(d) gate current gm
=
Mizoram PSC AE/SDO 2012-Paper-I 2π ( Cgs + Cgd )
Ans. (a) : Where, gm = 2k n ( VGS − VTN )
IDSS  VGS  g m = 2 × 0.25 × 10 –3 ( 3 − 1)
gm = 2 1 − 
| VP |  VP 
g m = 10−3
Hence gm can be controlled by gate to source voltage.
gm
Gain bandwidth FET =
2π ( Cgs + Cgd )
25. The drain resistance of JFET is
(a) 1/gm (b) µ/gm
(d) µ gm gm
(c) gm/µ =
Mizoram PSC AE/SDO 2012-Paper-I 2π ( 0.2 + 0.04 ) × 10–12
Ans. (a) : The drain resistance of JFET is the ratio of 10−3
∆VDS and ∆ID . = = 663.48
2π × 0.24 × 10–12
The drain-source channel resistance-
 663 MHz
∆VDS
R DS = 29. A CMOS amplifier when compared to an N
∆ ID
channel MOSFET has the advantage of
1 (a) Higher cutoff frequency
R DS = (b) Higher voltage gain
gm
(c) Higher current gain
26. As compared to transistor amplifier JFET (d) Lower power dissipation
amplifier has Nagaland PSC CTSC (Degree-2017) Paper-1
(a) Higher voltage, less input impedance IES-2015
(b) Less voltage gain, less input impedance Ans. (d) : The two important characteristics of CMOS
(c) Less voltage gain, higher input impedance device are high noise immunity and low power
dissipation.
(d) Higher voltage gain, higher input impedance
Mizoram PSC IOLM -2018, Paper II
Ans. (c) : As compared to transistor amplifier JFET has
less voltage gain and higher input impedance.
27. The best location for setting a Q-point on dc
load line of an FET Amplifier is at
(a) Saturation point (b) Cutoff point
(c) Mid-point (d) None of these
Mizoram PSC IOLM -2018, Paper II
Ans. (c) : The Q-point is the operating point of the CMOS devices dissipate less power than NMOS
transistor. It is selected in the middle of the active devices because the CMOS dissipates power only when
region because it gives maximum possible amplification switching, whereas N-channel MOSFET dissipates
to input sinusoidal signal without any distortion in power whenever the transistor is on because there is a
positive or negative half cycle. current path from VDD to Vss.
Analog Electronics 334 YCT
30. The transistors T1 and T2 shown in figure have The logic levels are not dependent upon the relative
a threshold of 1 volt. The device parameters K1 device sizes so that the transistors can be a minimum
and K2 of T1 and T2 are 36 µA/V2 and 9µA/V2 size.
respectively. The output voltage is nearly. Hence the property 1, 2 and 3 are true.
32. In a CMOS CS amplifier, the active load is
obtained by connecting a
(a) p channel current mirror circuit
(b) n channel transistor
(c) p channel transistor
(d) BJT current mirror
IES-2009
(a) 1 V (b) 2 V Ans. (a) : In a CMOS CS Amplifier, the active load is
(c) 3 V (d) 4 V obtained by connecting a P-channel current mirror
ISRO Scientist Engg.-2016 circuit.
IES-2015 33. Which one of the following gain equations is
Ans. (c) For saturation condition- correct for a MOSFET common-source
VDS ≥ ( VGS − Vth ) amplifier? (gm is mutual conductance, and RD
is load resistance at the drain)
The drain and gate are shorted for both the transistor-
(a) AV = gm/RD (b) AV = gmRD
VDS ∝ ( VGS − Vth )
2
(c) AV = gm/(1 + RD) (d) AV = RD/gm
Current is same in both transistor- IES-2007
36 ( 5 − Vo − 1) = 9 × ( Vo − 1)
2 2 Ans. (b)
−g m rd R D
6 ( 5 − Vo − 1) = 3 ( Vo − 1) AV =
rd (1 + R D rd )
30 − 6Vo − 6 = 3Vo − 3 µ=g r m d
24 + 3 = 3Vo + 6Vo g m → mutual conductance
9Vo = 27 R D → Load Resistance at drain.
27
Vo = AV = gmR D
9
Vo = 3V 34. What is the main advantage of a JFET-cascade
amplifier?
31. Consider the following statements about (a) High voltage gain
CMOS: (b) Low output impedance
1. CMOS logic inverter has maximum signal (c) Very low input capacitance
swing of 0V to VDD. (d) High input impedance
2. The output signal swing is independent of IES-2006
exact value of aspect ratio and other device Ans. (a) : There are two primary advantages of cascade
parameters. Amplifier increased gain and input, and o/p impedance
3. It is a fast switching device with the noise flexibility the need for the gain provided by cascade
margins Amplifier is paramount to the functionality of various
4. It has zero input resistance and infinite applications.
output resistance. 35. In an FET common-source high frequency
Which of these statements are correct? amplifier, which one of the following is the
(a) 1, 2, 3 and 4 (b) 1, 2 and 4 only correct expression for input capacitance?
(c) 1, 3 and 4 only (d) 1, 2 and 3 only (a) Ci = Cgs + (1 – AV) Cgd
IES-2011 (b) Ci = Cgs + (1 – 1/AV) Cgd
Ans. (d) : The main advantage CMOS over NMOS and (c) Ci = Cgd + (1 – AV) Cgs
Bipolar technology is the much smaller power (d) Ci = Cgd + (1 – 1/AV) Cgs
dissipation. The noise margins of symmetrical inverter IES-2006
(Where PMOS and NMOS transistors have equal Ans. (a) : In common source configuration, Cgd will be
current driving strength) approach VDD/2. The steady present between the input node gate and output node
state response is not affected by layout. drain. It can be therefore replaced with Cm and Cn using
When a Low-Level voltage (<Vdd ~ V) applied to the Miller’s theorem as =
Cm = Cgd (1 − A V )
inverter, the NMOS switched off and PMOS switched
on. So the output becomes VDD.
Analog Electronics 335 YCT
  1  Ans. (c) Given-
Cn = Cgd 1 −  g m = 3 × 10 −3 S
 AV 
R s = 3000Ω
Cm → appears parallel with Cgs
1
The input capacitance will be- Ro =
Cin = Cgs + C m 1
gm +
Rs
Cin = Cgs + Cgd (1 − A V ) 1
=
36. The drain gate capacitance of a junction FET is −3 1
3 × 10 +
2 pF. Assuming a common source voltage gain 3000
of 20. What is the input capacitance due to 3000
Miller effect? =
9 × 10−3 × 103 + 1
(a) 21 pF (b) 40 pF
3000
(c) 42 pF (d) 10 pF =
IES-2006 10
Ans. (c) Given- AV = 20 R o = 300Ω
Cgs = 2 pF 39. Consider the following statements describing
Miller capacitance is the property of a complementary MOS
Cmi = (1 + A V ) Cgs (CMOS) inverter
1. It is combination of an n-channel FET and
= (1 + 20 ) × 2 × 10 –12
a p-channel FET
Cmi = 21× 2 × 10 –12
2. There is power dissipation when the input
carries the logical 1 signal.
Cmi = 42 pF 3. There is no power dissipation when the
input carries the logical 0 signal.
37. Consider the following statements:
4. There is power dissipation during
We would be able to achieve broad banding in
transition from 0 to 1 or from 1 to 0.
a common source FET amplifier, by
Which of the statements given above are
1. Resonance between the shunt capacitance correct?
and a compensating inductance.
(a) 1, 2 and 3 (b) 2 ,3 and 4
2. RC compensating network between source
(c) 1, 3 and 4 (d) 1, 2 and 4
and drain
IES-2006
3. Connecting compensating network in
series with the coupling capacitors. Ans. (c) : The property of a complementary CMOS
Which of the statements given above is/are inverter :-
correct? (i) It is combination of an n-channel FET and a P-
channel FET.
(a) Only 1 (b) 1 and 2
(ii) There is no power dissipation when the input
(c) 1 and 3 (d) 2 and 3
carrier the logical 0 signal.
IES-2006 (iii) There is power dissipation during transition from 0
Ans. (c) : Broad Banding in a common source FET to 1 or from 1 to 0.
amplifier, by resonance between the shunt capacitance So the statements 1, 3 and 4 true.
and a compensating inductance, connecting
40. What is the value of RS required to self bias an
compensating Network in series with the coupling
N channel JFET with Vp = – 10V, IDSS = 40 mA
capacitors. and VGSQ = – 5V?
38. (a) 250Ω (b) 500Ω
(c) 750Ω (d) 1500Ω
Nagaland PSC (Degree) - 2018 Paper-II
IES-2005
Ans. (b) : Given-
VP = −10V
I DSS = 40 mA
For the circuit shown if gm = 3 × 10 and RS = VGSQ = −5V
–3

3000Ω, then what is the value of R0? Formula-

(a) 3000Ω (b) 1000/3Ω 2
 V 
(c) 300Ω (d) 100Ω I DS = IDSS 1 − GSQ 
IES-2006  VP 

Analog Electronics 336 YCT

  ( −5 )  Ans. (a) :
2

IDS= 40 ×  1 −  (i) Cascade connection →

 −10 
2
 1
IDS = 40 ×  1 − 
 2
(ii) Cascode connection →
1
I DS = 40 ×
4
I DS = 10mA (iii) Darlington connection →
−VGSQ
RS =
IDS
− ( −5 ) (iv) Parallel connection →
=
10 × 10−3
R S = 500Ω 43. Thermal runway is not possible in FET because
as the temperature of FET increases
41. Consider the following statement : (a) the mobility decreases
In JFET amplifiers, high frequency response
(b) the transconductance increases
can be improved by using peaking circuits
containing inductors (c) the drain current increases
1. in series with drain resistance RD. (d) the mobility increases
2. in series with the coupling capacitance IES-2001
3. as a feedback element between drain and Ans. (a) : The thermal runway is not possible in FET
gate? because as the temperature of FET increases, the
Which of the statement given above are mobility decreases.
correct? Since the current is decreasing with an increase in
(a) 1 and 2 (b) 2 and 3 temperature, the power dissipation at the output thermal
(c) 1 and 3 (d) 1, 2 and 3
of a FET decreases.
IES-2004
44. An FET is a better chopper than a BJT because
Ans. (c) : The junction field effect transistor (JFET) is a
majority charge carrier device hence. It has less Noise. it has
The coupling capacitors in series with inductors will (a) lower off-set voltage
reduce the gain. (b) higher series ON resistance
So the statements 1 and 3 are true. (c) lower input current
42. Match List-I (Circuit name) with List-II (d) higher input impedance
(Circuit diagram) and select the correct answer IES-2000
using the codes given below the lists:
Ans. (a) : FET is a better chopper than a BJT because
List-I List-II
FET typically produces less noise than a BJT.
Relatively Immune to radiation. Exhibits no offset
A. Cascade connection 1. voltage at zero drain current.
45. In a biased JFET the shape of the channel is as
shown in the given figure
B. Cascode connection 2.

C. Darlington connection 3.

because
D. Parallel connection 4. (a) it is the property of the material used
Codes: (b) the drain end is more reverse biased than
A B C D source end
(a) 1 2 3 4 (c) the drain end is more forward biased than
(b) 2 1 3 4 source end
(c) 1 2 4 3 (d) the impurity profile varies with the distance
(d) 2 1 4 3 from source
IES-2001 IES-1999
Analog Electronics 337 YCT
Ans. (b) : When applied gate to source voltage is zero
(0) the maximum drain current will flow through JFET.
As you increase the gate to source voltage the reverse
biasing will increase at the drain side as drain in move
positive than source. Hence penetration of depletion
region is more at the drain side.
46. A three-terminal monolithic IC regulator can
be used as (a) The amplitude as well as the frequency of the
(a) an adjustable output voltage regulator alone waveform will get doubled.
(b) The amplitude will get doubled but the
(b) an adjustable output regulator and a current
frequency will reduce to half its value.
regulator
(c) The amplitude will get doubled but the
(c) a current regulator and a power switch frequency will remain unchanged.
(d) a current regulator alone (d) The Amplitude will remain unchanged but the
IES-1999 frequency will get double.
Ans. (a) : A three-terminal monolithic IC IES-1995
regulator can be used as an adjustable output voltage Ans. (c) :
regulator alone.
47. Match List-I with List-II and select the correct
answer using the codes given below the lists:
List-I List-II
(Name of the (Special
electronic circuit) characteristics)
A. Darlington amplifier 1. Low input The change in the voltage wave form across capacitor,
the Amplitude will get doubled but the frequency will
impedance
remain unchanged.
B. Cascade amplifier 2. Low output
49. The JFET in the circuit shown in figure has an
(FET) impedance
IDSS = 10 mA and VP = –5 V. The value of the
C. Common gate 3. Low input resistance RS for a drain current IDS = 6.4 mA
amplifier capacitance but is (select the nearest value)
high Rin
D. Differential amplifier 4. Large common
mode rejection
ratio.
Codes:
A B C D
(a) 1 2 3 4 (a) 150 ohms (b) 470 ohms
(c) 560 ohms (d) 1 kilo ohm
(b) 1 2 4 3
GATE-1992
(c) 2 1 3 4
Ans. (a) : Given-
(d) 2 3 1 4
I DSS = 10mA
IES-1996
Ans. (d) : VP = −5V
List-I List-II I DS = 6.4mA
Darlington Amplifier - Low output Impedance. RS = ?
Cascade Amplifier - Low input capacitance but 2
high Rin.  V 
I DS = IDSS 1 − GS 
Common gate Amplifier - Low input Impedance  VP 
Differential Amplifier - Large common mode 2
rejection ration.  V 
6.4 ×10−3 = 10 × 10−3 1 − GS 
48. In the circuit of the relaxation oscillator shown  VP 
in the given figure, what will be the change in 2
 V 
the voltage waveform across capacitor, if the 6.4 = 10 1 − GS 
voltage V is doubled?  VP 

Analog Electronics 338 YCT

 2 51. In the MOSFET amplifier of the figure is the
 V 
6.4 = 10 1 − GS  signal output V1 and V2 obey the relationship
 −5 
2
64  VGS 
= 1 − 
100  −5 
8  VGS 
= 1 − 
10  −5 
8 V
− 1 = GS V2 V2
10 5 (a) V1 = (b) V1 = −
−2 VGS 2 2
= (c) V1 = 2 V2 (d) V1 = –2V2
10 5
GATE-1998
10
− = VGS Ans. (c) : The signal output V1 and V2 obey the
10 relationship-
VGS = −1 V1 = I D R D
−VGS IS = I D
Rs =
I DS R D I D R D V1
V2 = IS = =
1 2 2 2
= V1
6.4 × 10−3 V2 =
2
10000
Rs = ≈ 150Ω V1 = 2V2
64
50. Two identical FETs, each characterized by the 52. V0
The voltage gain Av = of the JFET amplifier
parameters gm and rd are connected in parallel. Vi
The composite FET is then characterized by shown in the figure is
the parameters.
g g r
(a) m and 2rd (b) m and d
2 2 2
rd
(c) 2gm and (d) 2gm and 2rd
2
GATE-1998
Ans. (c) : Both FET connected parallel-
Ip ID I
gm = = 1 + P
Vgs Vgs Vgs
IDSS = 10 mA Vp= –5 V
= g m 1 + g m2 (Assume C1, C2 and Cs to be very large)
Both FET identical- (a) +18 (b) –18
(c) +6 (d) –6
g m1 = g m2
GATE-2002
Overall- Ans. (d) : Transconductance
g m = 2g m 2I DSS  VGS 
gm = 1 − 
Vds −VP  VP 
rd =
I d1 + Id 2 From the question we know that
VG = 0, I DSS = 10mA R S = 2.5KΩ
1 1
= = ⇒ rd = rd  rd VS = I D R S ⇒ 1mA × 2.5KΩ
 d1   d 2 
I I 1
+
1
 +
   [ VS ⇒ 2.5V ]
 Vds   Vds  rd 1 rd 2
Both parallel rd1 = rd 2 Now VGS = VG − VS
= 0 − 2.5
rd = rd 2 [ VGS = −2.5]
Analog Electronics 339 YCT
 2 × 10 × 10−3   −2.5  
Now ⇒ g m = 1 −  −5  
−5   
g m = 2ms
A V = −g m R D
= −2 × 10 −3 × 3 × 103
A V = −6 (a)1 V and the device is in active region
53. Consider the following statements in (b)–1 V and the device is in saturation region
connection with the CMOS inverter in the (c)1 V and the device is in saturation region
figure, where both the MOSFETs are of (d)–1 V and the device is in active region
enhancement type and both have a threshold GATE-2005
voltage of 2 V. Ans. (c) : For an n-channel MOSEFT-
Statement 1: T1 conducts when Vi ≥ 2V. If VGS < VT , I D = 0
Statement 2: T1 is always in saturation when V0 If VGS ≥ VT , I D flow
= 0 V. Condition for saturation-
VDS ≥ VGS − VT
VD − VS ≥ VG − VS − VT
VD ≥ VG − VT
5 ≥ 3 −1
=5>2
This is saturation.
56. An n-channel depletion MOSFET has following
two points on its ID – VGS curve:
(i) VGS = 0 at ID = 12 mA and
Which of the following correct? (ii) VGS = –6 volts at Z0 = ∞
(a) Only statement 1 is TRUE Which of the following Q-points will give the
(b) Only statement 2 is TRUE highest transconductance gain for small
(c) Both the statements are TRUE signals?
(d) Both the statements are FALSE (a) VGS = –6 volts (b) VGS = –3 volts
GATE-2002 (c) V GS = 0 volts (d) VGS = 3 volts
Ans. (a) : Statement 2 is false because GATE-2006
VDS will be less than- Ans. (d) : transconductance -
∂I
⇒ VGS − VT ( g m ) = D for
∂VGS
If-
VGS = constant −
Vo = 0
Plotted-
Hence, the correct option (a).
54. The action of a JFET in its equivalent circuit
can best be represented as a
(a) Current controlled current source
(b) Current controlled voltage source
(c) Voltage controlled voltage source
(d) Voltage controlled current source
GATE-2003
Ans. (d) : In JFET equivalent circuit, the output current
is controlled by the gate to source voltage and hence we
can say it is a voltage controlled current source. As I D increases VGS also increases larger VGS will have
55. For an n-channel MOSFET and its transfer high transconductance gain.
curve shown in the figure, the threshold So, according to the option the highest transconductance
voltage is is 3V.
Analog Electronics 340 YCT
57. In the CMOS inverter circuit shown, if the Ans. (c) : NMOS transistors M1 and M2 are connected-
transconductance parameters of the NMOS Vbias both transistors are in saturation condition-
and PMOS transistors are Kn = Kp = ∂I D1
W W g m1 =
µnCox n
= µ p Cox P 2
= 40µA/V and their ∂Vi
Ln LP
In saturation region ID = constant
threshold voltages are VTHn = |VTHp| = 1 V, the
I D1 = I D2
current I is
∂I
g m = out
∂Vi
∂I D2 ∂I D1
=
∂Vi ∂Vi
gm = gm1
So, the equivalent gm of the pair is nearly equal to the
gm of M1.
59. For the circuit shown in the following figure,
(a) 0 A (b) 25 µA transistors M1 and M2 are identical NMOS
(c) 45 µA (d) 90 µA transistors. Assume that M2 is in saturation
GATE-2007 and the output is unloaded.
Ans. (c) : Given-
VGS = 2.5V
VT = 1V
µA
K = 40
V2
K
ID = ( VGS − VT )
2

2
= 20 ( 2.5 − 1)
2

I D = 45µA
The current Ix is related to Ibias as
58. Two identical NMOS transistors M1 and M2 (a) Ix = Ibias + Is
are connected as shown below. Vbias is chosen so
(b) Ix = Ibias
that both transistors are in saturation. The
(c) Ix = Ibias – Is
equivalent gm of the pair is defined to
∂I  V 
be out at constant Vout. (d) Ix = Ibias –  VDD − out 
∂Vi  RE 
GATE-2008
Ans. (b) : Transistors M1 and M2 are identical NMOS
transistor current Ix is related to bias as-
it is a current mirror circuit
IG1 = IG2 = 0
I X = IS
I bias = IS + IG1 + IG 2
The equivalent gm of the pair is
I bias = Is + 0 + 0
(a) The sum of individual gm's of the transistors
(b) The product of individual gm's of the I x = bias
transistors
Hence, the correct option is (b)
(c) Nearly equal to the gm of M1
60. In the circuit shown below, for the MOS
(d) Nearly equal to gm/g0 of M2
transistors, µn Cox = 100 µA/V2 and the
BPSC Poly. Lect. 2014 threshold voltage VT = 1 V. The voltage Vx at
GATE-2008 the source of the upper transistor is
Analog Electronics 341 YCT
 (a) 1 V (b) 2 V (a) Vin < 1.875 V
(c) 3 V (d) 3.67 V (b) 1.875 V < Vin < 3.125 V
GATE-2011 (c) Vin > 3.125 V
Ans. (c) : Let pull up transistor operate in saturation (d) 0 < Vin < 5 V
region- GATE-2012
W
1
( )
2
ID1 = µ n Cox   VGS1 − VT1 Ans. (a) : PMOS is in Linear region and NMOS is in
2  1
L cut-off region similarly for high V in , PMOS is in cut-off
and NMOS is in Linear region and for Vin in between
W
1
( )
2
ID2 = µ n Cox   . VGS2 − VT2 both are in saturation.
2  L 2
So PMOS will be in linear region for.
In saturation condition
Vin < 1.875 V
I D1 = ID2
4 [5 − VX − 1] = 1[ VX − 1]
2 2 63. The small-signal resistance (i.e. dVB/dID) in kΩ
offered by the n-channel MOSFET M shown in
2 [ 4 − VX ] = VX − 1 the figure below, at a bias point of VB = 2 V is
9 = 3VX (device data for M: device transconductance
parameter kN = µnC'OX(W/L) = 40 µ A/V2,
VX = 3V threshold voltage VTN = 1 V, and neglect body
61. An n-Channel JFET has effect and channel length modulation effects)
I DSS = 1µA & Vp = -5V. The maximum trans
conductance is
(a) g m = 0.4 micro mho
(b) g m = 0.04 milli mho
(c) g m = 0.04 mho
(d) g m = 0.4 mho (a) 12.5 (b) 25
BSNL (JTO)-2006 (c) 50 (d) 100
Ans. (a) : IDSS = 1µA GATE-2013
VP = –5V Ans. (b) : Given-
2I VB = 2V
maximum transconductance (gm)max = DSS
| VP |
W
2 ×1µA k N = µ n Cox   = 40µA V 2
= L
| −5 |
VT = 1V
2µA
= d vs
5V =?
d ID
µA
= 0.4. VB = VDS = VGS
V
gm = 0.4 micro mho M → is saturation condition-
62. In the CMOS circuit shown, electron and hole I D = k n ( VGS − VT )
2

mobilities are equal, and M1 and M2 are

equally sized. The device M1 is in the linear I D = 40 ×10−6 ( VDS − VT )
2

region if
Analog Electronics 342 YCT
 ∂I D K n = 0.78 mA / V
= 40 × 10−6 ( 2 − 1)
∂VDS Therefore, for-
VD = 2V
40
= 40 × 10−6 =
I D = 0.78 ( 2 − 0.8 )
2
1000 × 103
∂VDS ∂VB = 0.78 (1.2 )
2
= = 25kΩ
∂I D ∂I D
I D = 1.125 mA
Hence, the correct option (b).
66. What is the voltage Vout in the following
64. In a MOSFET operating in the saturation circuit?
region, the channel length modulation effect
causes
(a) An increase in the gate-source capacitance
(b) A decrease in the transconductance
(c) A decrease in the unity-gain cut-off frequency
(d) A decrease in the output resistance
GATE-2013
Ans. (d) : Without the channel length, modulation the (a) 0 V
drain current of a MOSEFT is given by- (b) (|VT of PMOS| + VT of NMOS)/2
Id = µ 2 × C ( W L )( VGS − VT )
2
(c) Switching threshold of inverter
(d) VDD
∴ dI/dV= 0 GATE-2016, Set-I
dv dI = ∞ Ans. (c)
Rd = ∞
If we consider channel length modulation, the value of
Rd will be always less than ∞. So the channel length
modulation decreases the output resistance.
65. For the n-channel MOS transistor shown in
figure, the threshold voltage VTh is 0.8 V.
Neglect channel length modulation effects.
When the drain voltage VD = 1.6 V, the drain
current ID was found to be 0.5 mA. If VD is
adjusted to be 2 V by changing the values of R The CMOS inverter connected in the feedback loop
and VDD' the new value of ID (in mA) is formed by connecting a 10 kΩ resister between the
output and input, goes and stays at the middle of the
characteristic-
VIR + VTH
Va =
2
Where-
Va → Switching threshold of the inverter.
(a) 0.625 (b) 0.75 67. In the circuit shown in the figure, the channel
length modulation of all transistors is non-zero
(c) 1.125 (d) 1.5 (λ ≠ 0). Also, all transistors operate in
GATE-2014, Set-I saturation and have negligible body effect. The
Ans. (c) : ac small signal voltage gain (Vo/Vin) of the
circuit is
I D = K n ( VGS − VT )
2

ID
Kn =
( VGS − VT )
2

0.5
Kn =
(1.6 − 0.8 )
2

0.5
=
0.64
Analog Electronics 343 YCT
 (a) –gm1 (r01||r02||r03) Vth → threshold voltage
 1  The small signal equivalent circuit of MOSFET in
(b) −g m1  r01 r03 
 g m3  saturation-
 
 1  
(c) −g m1  r01 r02  r03 
 g m2  

 1  
(d) −g m1  r01 r03  r02 
 g m3  

GATE-2016, Set-III
Ans. (c) :
When the channel length modulation effect is
significant in MOSFET can be modeled as a current
source with finite output Impedance.
69. Assuming that transistors M1 and M2 are
identical and have a threshold voltage of 1 V,
the state of transistors M1 and M2 are
respectively

The small signal equivalent + model of NMOS &

PMOS is shown-
According figure, we can write-
Vin = Vgs , and Vo = −Vgs2
The small-signal equivalent of the given circuit will be-
Modal at Vo , we can write-
(a) Saturation, Saturation (b) Linear, Linear
v v v
g m1 v gs1 + o + o + o − g m2 vgs2 = 0 (c) Linear, Saturation (d) Saturation, Linear
ro1 ro2 ro3 GATE-2017, Set-II
1 1 Ans. (c) : Given the circuit-
1 
vo  + + g m2 +  = −g m1Vin VDS1 = 3
 ro ro ro3 
 1
VGS2 − Vt = 2.5 − x − 1
2

The above can be written as-

    = 1.5 − x
vo 1
= −g m1  ro1 ||  ro2 ||
 || ro3  VDS2 is always > VGS2 − Vt
vin   g m2 
 
So, M 2 will always be in saturation current calculation-
68. An n-channel enhancement mode MOSFET is
biased at VGS > VTH and VDS > (VGS – VTH), (I ) = (I )
DSat 1 DSat 2
where VGS is the gate-to-source voltage. VDS is
K n ( VGS − Vt )1 = K n ( VGS − Vt )2
2 2
the drain-to-source voltage and VTH is the
threshold voltage. Considering channel length
( 2 − 1) = ( 2.5 − x − 1)
2 2
modulation effect be significant, the MOSFET
behaves as a 1 = 1.5 − x
(a) Voltage source with zero output impedance
(b) Voltage source with non-zero output x = 0.5
impedance VDS = x − 0
(c) Current source with finite output impedance
(d) Current source with infinite output impedance VDS = 0.5
GATE-2017, Set-II and VGS − Vt = 1V
Ans. (c) : N-channel enhancement mode MOSFET is So,
biased at VGS > VTH and VDS < VGS − Vt
VDS > ( VGS − VTH ) this shows that our assumption is wrong and M1 cannot
Where- VGS → gate- source voltage be in saturation so, M1 → linear region
VDS → Drain-source voltage M 2 → saturation region

Analog Electronics 344 YCT

70. Two identical nMOS transistors M1 and M2 are V = I r + I r − g V r
x x 01 x 02 m 2 g 2 02
connected as shown below. The circuit is used
as an amplifier with the input connected Put –
between G and S terminals and the output Vg2 = −I x r01
taken between D and S terminals, Vbias and VD
are so adjusted that both transistors are in Vx = I x r01 + I x r02 + I x r01 r02 g m2
( )
saturation. The transconductance of this
∂i D Vx = I x ro1 + ro2 + ro1 ro2 g m2 I x
combination is defined as gm = while the
∂VGS The output Resistance-
∂V Vx
output resistance is ro= DS , where iD is the R o = I
∂i D x

current flowing into the drain of M2. Let gm1, = ro1 + ro2 + g m2 ro1 ro2
gm2 be the transconductances and ro1, ro2 be the
( )
output resistance of transistors M1 and M2' ro1 + ro2 will be very small in comparison with
respectively
g m 2 ro1 ro2 −

R o  g m2 ro1 ro2
Since M2 NMOS transistor is acting as a current buffer,
I D2 = ID1
The transconductance
∂I D2
Which of the following statements about g m2 =  g m1
estimates for gm and ro is correct? ∂Vgs
(a) gm ≈ gm1 . gm2 . ro2 and ro ≈ ro1 + ro2
(b) gm ≈ gm1 + gm2 and ro ≈ ro1 + ro2 71. An enhancement MOSFET of threshold
(c) gm ≈ gm1 and ro ≈ ro1 . gm2 . ro2 voltage 3 V is being used in the sample and
hold circuit given below. Assume that the
(d) gm ≈ gm1 and ro ≈ ro2
substrate of the MOS device is connected –10
GATE-2018
V. If the input voltage Vi lies between ± 10 V
Ans. (c) : Given-
the minimum and the maximum values of VG
∂I ∂V
g m = D , ro = DS required for proper sampling and holding
∂VGS ∂I D respectively, are
I D → drain current
g m1 , g m2 → Transconductance
Vo1 ,Vo2 → Output resistance of the transistors M1 and
M2
(a) 10 V and –13 V (b) 13 V and –7 V
Vg2 (c) 10 V and –10 V (d) 3 V and –3 V
GATE-2020
gm2 Vg2
Ans. (b) : Given-
VT = 3V
Vmin = −10V
Vmax = 10V
MOSFET sampling-
Applying KVL from Vg2 to ro1 ground- VGS > VT
We get- VG − Vmax > VT
− Vg2 − I x r01 = 0 VG − 10 > 3
Vg2 = − I x r01 .........(i)
VG > 13V
( )
Vx = ro2 I x − g m2 Vg2 + I x ro1 MOSFET should be since off for holding operation-
= ro2 I x − g m 2 Vg 2 ro2 + I x ro1 VGS < VT

Analog Electronics 345 YCT

VG − Vmin < VT 74.
Select the correct statement (s) regarding
CMOS implementation of NOT gates.
VG − ( −10 ) < VT
(a) Noise Margin High (NMH) is always equal to
VG < 3 − 10 the Noise Margin Low (NML), irrespective of
the sizing of transistors.
VG < −7V
(b) Dynamic power consumption during
Hence maximum and minimum value of VG required switching is zero.
for proper sampling and holding respectively are 13 V (c) For a logical high input under steady state, the
and -7V
nMOSFET is in the linear regime of
72. Using the incremental low frequency small- operation.
signal model of the MOS device, the Norton
equivalent resistance of the following circuit is (d) Mobility of electrons never influences the
switching speed of the NOT gate.
GATE-2022
Ans. (c) : NML = VIL –VOL
(a) NMH = VOH – VIH
VTN = |VTP|
Kn = Kp
V
VIT = DD
1 2
(a) rds + R + gm rds R (b) rds + +R
gm Kp
When, ↑ > 1, VIL ↑, VIH ↑
rds + R K n
(c) rds + R (d)
1 + g m rds NM H ↓ and NM L ↑
GATE-2020
Kp
Ans. (d) : When ↓ < 1, VIL ↓ .VIH ↑
Kn
NM H ↑ and NM L ↑
ie NML and NMH depends on transistor sizing and they
are equal for certain condition only.
(b) Dynamic power consumption during switching is
non-zero due to capacitive loading of next stage.
(c) For, VDD – |VTP| ≤ Vin ≤ VDD ⇒ PMOS → cut off
Norton equivalent resistance of the following circuit is – (d) Switching speed depends on charging and
Vm = −Vx discharging of load capacitor for pull up and pull
down of output voltage respectively.
Vx (1 + g m rds ) = ( rds + R ) I x Propagation delay,.
V R + rds τ + τPHL
RN = x = t p = PLH
I x 1 + g m rds 2
R + rds Where,
RN = CL VDD
1 + g m rds TPHL =
 ω
µ p Cox   ( VGS − VTP )
2
73. A JFET has got the following specifications:
VGS(OFF) = –2V, IDSS = 4 mA. When the applied L
VGS is one fourth of the VGS(OFF) to the JFET, CL VDD
then the drain current of the device would be VPHL =
 ω
µ p C→   ( VGS − VTN )
2
(a) 2.25 mA (b) 4 mA
(c) 0.25 mA (d) 1.0 mA L
TSGENCO AE-2015 using average charge model
Ans. (a) : Drain current Hence, c is only correct.
2 75. An n-channel JFET has 'IDSS' = 1 mA and
 Vgs   −2 
2

I D = I DSS 1 −  ID = 4 1 −  'VP' = –5 V. Its maximum transconductance is

 Vp   −8 
 (a) 0.4 millimho (b) 0.1 millimho
ID = 4 × 0.5625 (c) 1.0 millimho (d) 4.0 millimho
ID = 2.25 mA Kerala PSC Lecturer (NCA) 04.07.2017
Analog Electronics 346 YCT
 2 I DSS Ans. (d) :
Ans. (a) : Maximum Transconductance gm0 =
VP
2 × 1× 10−3
gm0 =
5
gm0 = 0.4 m 
76. A source follower (using a FET) usually has a
voltage gain which is
(a) Slightly less than unity, but positive
(b) Greater than +1
(c) Exactly unity but negative
Rout = –gm1 (r01 R p ) r02
(d) About – 10
Kerala PSC Lecturer (NCA) 04.07.2017 80. An N-Channel JFET has IDSS=8mA and
Ans. (a) : A source followers usually has a voltage gain Vp = –5V. The minimum value of VDs for
slightly less than unity but always +ve. But current of pinch-off region and the drain current IDs for a
this configuration will be high. VGS = –2V are.
77. The pinch off voltage of a JFET is 5V. Its cut (a) 3V and 2.88mA (b) -5V and 1.88mA
off voltage is (c) -2V and 3.12mA (d) -7V and 1.98mA
(a) 51/2 V (b) 2.5 V TNPSC AE- 2019
3/2
(c) 5 V (d) 5.0 V Ans. (a) : Given –
IDSS = 8mA, Vp = -5V, VGS = -2V
Kerala PSC Lecturer (NCA) 04.07.2017
 ( −2 ) 
2
2
Ans. (d) : VP = 5 V  VGs  -3  1 −
ID = IDSS 1 −
  = 8×10  ( −5 ) 
At cut-off the gate to source voltage of JFET is equal to
 Vp   
pinch off voltage. 2
−3  3 
Vgs = VP ≥ Vgs (off) = 8 × 10  
Vgs (off) = 5V 5
78. A certain p channel E-MOSFET has 9
= 8 × 10-3×
VGS(th) = –2V. If VGS = 0V, the drain current is: 25
(a) 0 A (b) ID(ON) = 2.88mA
(c) maximum (d) IDSS VDS ≥ VGS − Vp
RPSC VP/Suptd. ITI 05.11.2019
= −2 − ( −5 ) = 3 V
Ans. (a) : A certain p channel E-MOSFET has a
VGS(th) = – 2V ; VGS = 0V 81. The symbol in figure 1 is
VGS(th) < VGS
E MOSFET in cutt off region
drain current is 0A.
79. During manufacturing, a large parasitic
resistor, Rp, has appeared in a cascade as
shown in the figure below. Determine the
output resistance (a) diode connected FET
(b) triode connected FET
(c) tetrode connected FET
(d) pentode connected FET
TNPSC AE- 2019
Ans. (c) : The tetrode field–effect transistor or field
effect tetrode is a solid–state semiconductor device,
constructed by creating two field-effect channels back-
to-back. It is a four–terminal device. It does not have
specific gate terminals because each channel is a gate
for the other, the voltage condition modulating the
(a) Rout = – gm2 (r01||Rp)r02 current carried by the other channel.
(b) Rout = – gm1 (r02||Rp)r01
82. Which basic FET amplifier configuration is
(c) Rout = – gm1 (r01||r02)Rp also known as the 'Source Follower' and which
(d) Rout = – gm1 (r01||Rp)r02 bipolar transistor amplifier configuration it is
RPSC VP/Suptd. ITI 05.11.2019 analogous to?
Analog Electronics 347 YCT
 (a) Common drain amplifier, Emitter follower Ans. (a) :A junction field effect transistor can operate in
(b) Common source amplifier, common emitter depletion mode only but MOSFET can operate in
amplifier enhancement and depletion mode.
(c) Common gate amplifier, common base 87. Vp is the pinch off voltage for VGS = 0 in an
amplifier FET. When the gate is reverse biased by VGS
(d) Common source amplifier, Emitter follower the pinch off voltage
(a) Will be less than Vp
Nagaland PSC- 2018, Diploma Paper-II
(b) Will be more than VP
Ans. (a) : Common drain amplifier configuration is also (c) Same as VP
known as the source followers. The reason for this is (d) Does not depend on VGS
that the source voltage follows that of the gate. Nagaland PSC CTSE- 2015, Paper-II
83. In a FET, transconductance gm is proportional
Ans. (a) : Vp → Pinch off voltage
to
When the gate is reverse biased by Vds, the pinch off
(a) Ids (b) Ids2 voltage will be less than one because when gate is
(c) Ids (d) I/Ids reversed biased depletion width increases which
decreases the pinch-off voltage.
Nagaland PSC- 2018, Diploma Paper-II
88. The MOSFET switch in its on-state may be
Ans. (a) : Trans conductance for FET is given by considered equivalent to :
2I  V  (a) Resistor (b) Capacitor
gm = DSS 1 − Gs  (c) Inductor (d) Battery
Vp  Vp 
RRB SSE 21.12.2014, (Red)
IDSS ⇒ maximum drain current. Ans. (b) : The MOSFET switch in its on-state may be
84. In JFET, dynamic drain resistance rd is of the considered equivalent to capacitor. In on-state there is a
order of conducting channel between Drain and source.
(a) 1 KΩ (b) 10 KΩ The structure of MOS is like–
• GATE (metal)
(c) 10 MΩ (d) 100 MΩ
• Oxide (SiO2) layer
Nagaland PSC- 2018, Diploma Paper-II • Conductive channel
Ans. (a) : Dynamic resistance of JFET is of the order of N-channel MOSFET:-
1 kΩ. (a) Enhancement Mode :-
transconductance = 0.1 ms to 10ms
85. The parameters of an FET are gm=3mA/V,
rd = 30K. RL=3K as a source follower load, the
output impedance is given by
(a) 333 ohms (b) 2.7 K ohms
(c) 3 K ohms (d) 300 ohms
Nagaland PSC CTSE- 2015, Paper-II
Ans. (d) :
RL (b) Depletion Mode
R0 =
1 + gmR L
R L = R 2 || rd
3 × 30
=
33
= 2.7 k Ω
 3k Ω

3k It is also a voltage-controlled resistor in which the

R0 = channel thickness depends on the gate to source.
1 + 3 × 10 –3 × 3 × 103
89. For a Common Source (CS) MOSFET
= 300 Ω
amplifier, what is the input capacitance Cin for
86. A junction field effect transistor can operate in
(a) Depletion mode only the following conditions:
(b) Enhancement mode only C gs = 4pF, C gd = 1pF, and A v = 5.

(c) Depletion and Enhancement modes (a) 10 pF (b) 16 pF

(d) Neither depletion nor Enhancement modes (c) 14 pF (d) 12pF
Nagaland PSC CTSE- 2015, Paper-II UPPCL AE-05.11.2019
Analog Electronics 348 YCT
Ans. (a) : Given as due to virtual ground,
Cgs = 4pF , Cgd = 1pF, and Av = 5 Va = 2.5V
As we know 2.5 2.5 − 5 2.5 − Vb
Therefore, + + =0
Cin = Cgs + Cgd(1–Av) 3.3 3 10
Q Common source Amplifier gain is always negative Vb = 1.75V
(-Ve) Time constant - τ = 100kΩ × 1nF
∴ AV = –5
Cin = 4+1 [1–(–5)] τ = 100 × 103 × 10−9 = 100µs
Cin = 4+6 = 10pF And now the gate voltage is given by
90. In a Common Drain (CD) MOSFET amplifier VG = 5 (1 − e − t τ )
with voltage divider bias with R1 and R2 equal
to 1.5 MΩ and 1 MΩ respectively, the input ⇒ 0.7 = 5 (1 − e − t 100µs )
impedance Zi is: t = 15µs
(a) 220 kΩ (b) 600 kΩ
When MOSFET ON VG > Vt ( 0.7V )
(c) 470 kΩ (d) 200 kΩ
After 15µs, VG > Vt
UPPCL AE-05.11.2019
MOSFET ON behaves as comparator for positive logic.
Ans. (b) : Given as, R1 = 1.5MΩ , R2 = 1MΩ
So, Before 15µs ( Vt > VD ) MOSFET off behaves as
R ⋅R comparator for negative logic.
R in = R1 || R 2 = 1 2 After 100µs, we have
R1 + R 2
5
1.5 ×106 × 1× 106 Vt = t
R in = T
(1.5 + 1) ×106 5
⇒ 1.75 = ×t
R in = 0.6MΩ ⇒ R in = 600kΩ 100
175
91. The ramp signal (voltage: 0 to 5 V) is compared t = = 35µs
with the soft-start signal provided by N- 3
channel MOSFET (Q1) for amplifier (A1) After 135µs, the comparator behaves for negative logic
output. If Q1 having low threshold voltage of up to 200µs
0.7 V and negligible ON resistance. What is the
Duty cycle-
duty of output signal of comparator (C1) after
100 µs ? T 35
D = ON = × 100
T 100
= 35% ≅ 34.8%
92. What is the value of Rs required to self bias N-
channel JFET with Vp = –10V, IDSS = 40 mA
and VGSQ = –5V?
(a) 250Ω (b) 500Ω
(c) 750Ω (d) 1500Ω
LMRC AM (S&T)-13.05.2018
2
 V 
(a) 17.4% (b) 34.8% Ans. (b) : We know that I D = I DSS 1 − gs 
(c) 0% (d) 50%  VP 
ISRO Scientist December, 2017 2
−3   −5  
Ans. (b) : Given I D = 40 × 10 1 −  
  −10  
[ ID = 10mA ]
Vgs 5
Rs = = = 500Ω
ID 10 × 10−3
93. A JFET has Idss = 5 mA and gmo = 5000 µS.
What is the value of VGS (off) and for VGS = –
KCL at node Va 1V gm is:
Va Va − Vcc Va − Vb (a) VGS(off) = –2V, gm = 7500 µS
+ + =0
3.3 3 10 (b) VGS(off) = –1V, gm = 7500 µS

Analog Electronics 349 YCT

 (c) VGS(off) = –1V, gm = 2500 µS 1 1
(a) − (b) −
(d) VGS(off) = –2V, gm = 2500 µS 400 600
LMRC AM (S&T)-13.05.2018 1 1
(c) − (d) −
−2I DSS 2000 31000
Ans. (d) : VGS( off ) =
g mo DRDO-2009
Given ⇒ I DSS = 5mA g mo = 5000µS Ans. (c) :
−2 ( 5mA )
VGS( off ) =
5000µS
VGS( off ) = −2V
Use formula-
 V 
g m = g mo 1 − GS 
 VGS( off ) 
 
 1V 
g m = ( 5000µS) 1 − 
 2V  1
Slope = −
R D + RS
g m = 2500µS
1
94. A CMOS Inverter is shown below in the figure. = −
For Vin = Vout = 2.5 V, which one of the 1600 + 400
following is true if the threshold voltage of the ⇒ − 1
NMOS transistor is 1 V and that of PMOS 2000
transistor is –1 V. 96. An n-type MOSFET and an npn BJT are
biased so that IC = ID = 1 mA, VGS = 1.3 V and
VBE = 0.7 V. Threshold voltage for the
MOSFET is 0.8 V and thermal voltage at the
ambient temperature is given to be 25 mV.
Transconductances of the BJT and the
MOSFET are :
(a) gmBJT = 40 mA/V and gmMOSFET = 4 mA/V
(b) gmBJT = 40 mA/V and gmMOSFET = 2.5 mA/V
(a) NMOS is Linear region, PMOS in saturation (c) gmBJT = 80 mA/V and gmMOSFET = 2 mA/V
(b) NMOS in saturation region, PMOS in (d) gmBJT = 80 mA/V and gmMOSFET = 4 mA/V
saturation DRDO-2009
(c) NMOS is saturation region, PMOS in linear
region Ans. (a) : Trans-conductance of BJT is the ratio of
(d) NMOS in Linear region, PMOS in Linear output drain current with respect to change in the input
region gate voltage it is presented by g m
−3
BSNL (JTO)-2001 g = IC = 1× 10 = 40mA / V
VT 25 × 10−3
m
Ans. (b) : If the threshold voltage of the NMOS
transistor is 1V and that of PMOS transistor is –1V in Trans conductance of MOSFET anode current divided
this condition NMOS will be in saturation region and by the corresponding change in the cathode voltage.
PMOS will also in saturation region.
2ID 1×10-3 × 2
95. The slope (in A/N) of the ID – VDS load line for g m MOSFET = = = 4mA/V
Vgs − VT 1.3-.8
the circuit shown in figure below is :
97. In a P-well fabrication process, the substrate is
(a) N-type semiconductor and is used to build P-
channel MOSFET
(b) P-type semiconductor and is used to build P-
channel MOSFET
(c) N-type semiconductor and is used to build N-
channel MOSFET
(d) P-type semiconductor and is used to build N-
channel MOSFET
DRDO-2008
Analog Electronics 350 YCT
Ans. (a) : In a P-well fabrication process the substrate is Ans. (d) : Given,
N Type semiconductor and used to build P channel VGS1 = 900mV = 0.9 V
MOSFET.
I D1 = 1mA
VGS2 = 1400mV = 1.4V
VTH = 0.4V
I D ∝ ( VGS − VTH )
2

( )
2
I D1 = K VGS1 − VTH .................(i)

= K (V )
2
I D2 GS2 − VTH ……………….(ii)
98. An N-channel enhancement mode MOSFET
with threshold voltage of 1 V is biased at By equation (i) and (ii)
2
VGS = 2 V and VDS = 2V. If the drain voltage is I D2  VGS2 − VTH 
doubled to 4 V, the drain-to-source current = 
will: I D1  VGS1 − VTH 
(a) double (b) more than double
(1.4 − 0.4 )
2
ID2
(c) increase only slightly (d) become half =
BSNL(JTO)-2002 1m A ( 0.9 − 0.4 ) 2

Ans. (b) : I D = K ( VGS − VT ) (1) ×1mA

2 2
I D2
=
( 0.5 )
2
Where, 1
I D → Drain current 1
= mA
VGS = Gate source voltage 0.25
VT = Threshold voltage ID2 = 4mA
99. An n-channel JFET has IDSS =2mA and 101. The drain of an n-channel MOSFET is shorted
Vp= –4V. It's transcoductance gm (in mA/V). to the gate so that VGS=VDS. The threshold
When applied gate to source voltage VGS –2V is voltage (VT) of MOSFET is 1 V. If the drain
(a) 0.25 (b) 0.5 current (ID) is 1 mA for VGS=2V, then for VGS =
(c) 0.75 (d) 1.0 3V, ID is
GATE- 1999 (a) 2mA (b) 3mA
Ans. (b) : Given, (c) 9mA (d) 4mA
IDSS = 2mA = 2×10–3A GATE-2004
VP = – 4V Ans. (d) : Given, VGS = VDS, VT = 1V
VGS = –2V I D2 = 1mA
gm = ?
drain current ID = 1mA
2I DSS  VGS  VGS1 = 2V
gm = 1 − 
| VP |  VP 
VGS2 = 3V
2 × 2 × 10−3  ( −2 ) 
gm = 1 −  I D ∝ ( VGS − VT )
2

| − 4 |  ( −4 ) 
( )
2
I D1 = K VGS1 − VT …………………(i)
g m = 0.5mA / V
= K (V −V )
2
100. When the gate-to-source voltage (VGS) of a I D2 GS2 T ………………..(ii)
MOSFET with threshold voltage of 400 mV, By equation (i) and (ii)
working in saturation is 900 mV, the drain
( )
2
current is observed to be 1 mA. Neglecting the I D2 VGS2 − VT
channel length modulation effect and assuming =
( )
2
that the MOSFET is operating at saturation,
I D1 VGS1 − VT
the drain current for an applied VGS of
1m A ( 2 − 1)
2
1400 mV is =
( 3 − 1)
2
(a) 0.5 mA (b) 2.0 mA I D2
(c) 3.5 mA (d) 4.0 mA
ID2 = 4mA
GATE- 2003
Analog Electronics 351 YCT
102. The drain current of a MOSFET in saturation (a) 4.5×1011 cm–2 (b) 6.0×1011 cm–2
11 –2
2
is given by ID=K(VGS–VT) where K is a (c) 7.2×10 cm (d) 8.4×1011 cm–2
constant. The magnitude of the trans- GATE- 2016
conductance gm is Ans. (b) : Given,
K(VGS – VT ) 2 VG1 = 0.8V, VG2 = 1.3V, VG3 = 1.8V
(a) (b) 2K(VGS – VT )
VDS Q = 2 × 1011 cm −2 , Q = 4 × 1011 cm −2 , Q = ?
1 2 3

ID K(VGS – VT ) 2 We know that-

(c) (d)
VGS – VDS VGS Q ∝ (VG − VT )
GATE-2008 VG1 − VT Q1 0.8 − VT 2 × 1011
∴ = ⇒ =
Ans. (b) : Given- ID = K (VGS -VT)2 VG 2 − VT Q 2 1.3 − VT 4 × 1011
where K is constant VT = 0.3V
dId VG 2 − VT Q 2 1.3 − 0.3 4 × 1011
Transconductance gm = Now- = = =
dVGS V = Constant
ds
VG3 − VT Q3 1.8 − 0.3 Q3
d.K Q3 = 6 × 1011 / cm 2
gm = (VGS − VT ) 2
dVGS
105. Two n-channel MOSFETs, T1 and T2, are
or gm = 2K (VGS –VT) identical in all respects except that the width of
103. The measured trans-conductance gm of an T2 is double that of T1. Both the transistors are
NMOS transistor operating in the linear region biased in the saturation region of operation,
is plotted against the gate voltage VG at a but the gate overdrive voltage (VGS–VTH) of T2
constant drain voltage VD. Which of the is double that of T1, where VGS and VTH are the
following figures represents the expected gate-to-source voltage and threshold voltage of
dependence of gm on VG? the transistors respectively. If the drain
current and transconductance of T1 are ID1 and
gm1 respectively, the corresponding values of
these two parameters for T2 are
(a) 8 ID1 and 2 gm1 (b) 8 ID1 and 4 gm1
(c) 4 ID1 and 4 gm1 (d) 4 ID1 and 2 gm1
GATE- 2017
Ans. (b) : Given,
W2 = 2W1 = 2W
and (VGS – VTh)2 = 2(VGS–VTh)1 = 2(VGS –VTH)
W1 ( VGS − VTh )1
2
I D1 W1 (VGS − VTH )2
= =
8W1 ( VGS − VTh )2 8W1 (VGS − VTH )2
2
I D2
GATE-2008 I D2 = 8I D1
Ans. (c) : Drain current ID in the linear region is given Similarly
by- g m1 W (V − Vth )1
 VDS2  = 1 GS
I D = K ( VGS − VT ) VDS − g m2 W2 (VGS − Vth ) 2
 2 
g m1 W1 (VGS − Vth )
∂I D =
gm = = K ( VGS − VT ) VDS g m2 2W 1 2(VGS − Vth )
∂VGS V =Constant
DS g m2 = 4g m1
g m ∝ VDS 106. The figure shows the high-frequency C-V curve
Hence, gm is independent of VGS for linear region of a MOS capacitor (at T=300K) with
operation of N-MOS. φms = 0V and no oxide charges. The flat-band,
104. A voltage VG is applied across a MOS capacitor inversion, and accumulation conditions are
with metal gate and p-type silicon substrate at represented, respectively, by the points
T=300 K. The inversion carrier density (in
number of carriers per unit area) for VG= 0.8 V
is 2×1011 cm–2. For VG= 1.3 V, the inversion
carrier density is 4 ×1011 cm–2. What is the
value of the inversion carrier density for
VG=1.8 V?
Analog Electronics 352 YCT
 (a) Q, R, P (b) P, Q, R 2
qN D 2  b 
(c) Q, P. R (d) R, P, Q = a 1 – 
2ε  a
GATE-2019 2
Ans. (a) : The flate band voltage where no charge VP  b
= VP 1 –  From equation (ii)
present in the oxide surface as Va increase more electrons 4  a
are attracted to the oxide semiconductor inter face a n- 2
1  b
type channel is formed the inversion takes place R for = 1 – 
negative gate voltage, mover holes are accumulated near 4  a
the gate. Accumulation takes place at P. b 1
1– =
a 2
b 1
=
a 2
a
b=
2
3
b = µm
107. Determine the channel half-width for an n- 2
channel silicon FET having Gate-to-Source b = 1.5µm where b=channel width
voltage, VGS =Vp/4, where Vp is the Pinch-off
voltage and drain current Id=0. (Consider (a) 108. A high gain MESFET packaged device of case-
Donor Concentration ND=1015 electrons/cm3 (b) to-channel thermal resistance of the device is
Channel half-width for VGS= 0 V is 3 µm ). 4.5° C/Watt provides 8W RF output power
(a) 2.25 µm (b) 3 µm taking 20W DC power. What will be the
channel temperature of the device if the case
(c) 1.5 µm (d) 0.75 µm temperature of the device maintained at 55°C?
ISRO Scientist Engg.-2018 (a) 109°C (b) 145°C
Ans.(c): Given, (c) 59.5°C (d) 91°C
VP ISRO Scientist Engg. -2015
Gate to source voltage VGS = Ans. (a) : Given,
4
drain current ID = 0 thermal resistance = 4.5°C / W
15
donor concentration ND=10 electron/cm 3 P o = 8W, Pi = 20W, Tcase = 55ºC
channel half width for VGS=0V is 3µm T – Tcase
Thermal resistance = channel
We know, Pi – P0
2εV  1 1  4.5 =
Tchannel – 55
depletion width (W) =  + 
q  NA ND  20 – 8
Acceptor concentration NA is very higher than ND then 4.5 × 12 = Tchannel – 55
1 1 Tchannel = 54 + 55
is very low so is neglected
NA NA Tchannel = 109°C
2εV  1  109. A unilateral transistor has an output
w=  
q  ND  impedance Zout = (10 – j10)Ω. Value of the
series and shunt components of the matching
2εV 1
w2 = . network for complex conjugate match at the
q ND output of the device to 50Ω load are:
qN D 2
V= w ...............(i)
2ε
2a
channel width = =a=3µm (given)
2
at pinch off voltage VP=V and VGS=VP
qN D 2
Vp = a ..........(ii) (a) X1 = –j25, X2 = +j30
2ε (b) X1 = +j25, X2 = +j30
VGS=VP/4 (c) X1 = –j25, X2 = –j3
VP qN D
= (a – b)
2 (d) X1 = +j2, = –j30
4 2ε ISRO Scientist Engg. -2015
Analog Electronics 353 YCT
Ans. (a) : Given,
Zout = (10–j10)Ω
(Zout + X2) || X1 = 50Ω
( Zout + X 2 ) .X1 = 50
Zout + X 2 + X1
{(10 – j10 ) + X }.X
2 1
= 50
(10 – 10 j) + X 2 + X1
(10 – j10 ) X1 + X1X 2 = 50 ...............(i)
(10 – 10 j) + X 2 + X1 (a) 3.45 V (b) 1.5 V
This equation is satisfied when (c) 2.85 V (d) 2.3 V
X1= –j25 & X2 = j30 UPPCL AE- 31.12.2018
110. For the circuit shown above if gm = 3 × 10–3 and Ans. (c) : VDS ≥ (VGs – VTh)
Rs = 3000Ω, then the approximate value of R0 is µCox W
I DS = ( VGS − VT )
2

2 L
1
VG = 10 × = 5V
2
VS = IDS × RS
I DS = 12.5µ ( 4 − i D × 50 )
2

(a) 3000 Ω (b) 1000/3Ω

I D sat = 12.5 16 + 2500 I2Dsat × 106 − 4 × 105 I DS 
(c) 300Ω (d) 100Ω
ISRO Scientist Engg.-2008 From here
Ans. (c) : Given, gm = 3×10 –3 ID = 0.043 mA or 0.1489 mA
Rs = 3000Ω for ID = 0.1489 mA VD = − ve so
1 VD = 10–0.1489mA ×75K
drain resistance (rd) =
transconductance (g m ) = –1.167V (this is not possible)
1 ID = 0.043 mA
= VD = 10 – 0.043 × 75 K
3 ×10−3
VD = 6.775 V
103
= VS = 0.043 × 50K
3
1000 Vs = 2.15V
rd = Ω
3 VDS = VD – VS
R 0 = rd || R s VDS = 6.775 – 2.15
VGS = VG–VS = 5 – 2.15
1 1 1
= + VGS = 2.85 V
R 0 rd R s
1 1 1 112. The drain of an N-channel MOSFET is shorted
= + to the gate such that VGS = VDS. The threshold
R 0 1000 3000 voltage (VT) of MOSFET is 1 volt. If the drain
3 current (ID) is 1 mA for VGS = 2V, then for
1 3 1 VGS = 3V, the drain current ID is-
= +
R 0 1000 3000 (a) 4 mA (b) 3 mA
(c) 5 mA (d) 6 mA
R 0 = 300Ω UPPCL AE-16.11.2013
111. Find the gate source voltage VGS for the given ISRO Scientist-2007
N-MOSFET with parameters VT = 1V, Kn = Ans. (a) : For n channel MOSFET-
the I D = K n [2VDS ( VGS − Vth ) − VDS ] , VDS < (VGS – Vth)
W 2
µ 0C0x = 25 µA/V 2 . Assume that
L 2
MOSFET is not operating in the cutoff mode, ID = K n  VGS − Vth  VDS > VGS – Vth.
and also assume an ideal MOSFET with gate
current equal to zero. In problem, VDS = VGS So VDS > VGS − VT

Analog Electronics 354 YCT

Hence this is in saturation region. Tjmax − Tamb
From the given value Pmax =
θ2 − θ1
ID = Kn [VGS – VT]2
1500º C − 300º C
1 mA = Kn (2 – 1)2 =
( 600 − 1)
0
Kn = 1 mA/V2 C/ W
Now when VD = 3V, VGS = 3V 1200º C
ID = Kn [VGS – VT]2 =
5990 C
I D = 1[3 − 1] mA
2
Pmax  2W
ID = 4 mA 115. A MOSFET in saturation has a drain current
113. The pinch - off voltage of n-channel junction of 1 mA for VDS = 0.5 V. If the channel length
FET is VP = –4V and the drain to source modulation coefficient is 0.05 V–1, the output
saturation current IDSS= 2mA. Its trans resistance (in kΩ) of the MOSFET is
conductance (gm) for an applied gate to source (a) 15 (b) 20
voltage VGS of –2V is- (c) 18 (d) 23
(a) 1.0 mA/V (b) 0.25 mA/V Nagaland PSC CTSE (Diploma)-2017, Paper-I
(c) 0.75 mA/V (d) 0.5 mA/V Ans. (b) : IDSat = 1mA , λ = 0.05
UPPCL AE-16.11.2013 VDS = 0.5V
Ans. (b) : Given, Modulation coefficient = 0.05/V
VP = –4V, IDSS = 2mA, VGS = –2V I D = I Dsat (1 + λVDS )
2
 V  dI D 1
= = λ I Dsat
ID = IDSS 1 − GS 
 VP  dVDS r0
1
r0 =
2
  −2  
I D = 2 × 10−3 1 −    λI Dsat
  −4  
1
 1
2 =
−3
I D = 2 × 10 1 −  0.05 × 1× 10−3
 2 = 20kΩ
1 116. An N-channel JFET, having a pinch-off voltage
I D = 2 × 10−3 ×
4 (Vp) of –5V, shows a trans conductance (gm) of
ID = 0.5 mA 1 mA/V when the applied gate-to-source
I voltage (VGS) is –3V. Its maximum trans
gm = D conductance (in mA/V) is
| VGS | (a) 1.5 (b) 2.0
0.5mA (c) 2.5 (d) 3.0
gm =
| −2 | Nagaland PSC CTSE (Degree)-2017, Paper-I
0.5 Ans. (c) : VP = –5V
gm = mA gm = 1mA/V
2
g m = 0.25mA / V VGS = –3V
−2I DSS  VGS 
114. A certain power MOSFET has a maximum gm = 1 − 
junction temperature specification of 1500ºC, a VP  VP 
junction-to-case thermal resistance of −2I DSS  3 
1.00 0C/W, and a junction-to ambient thermal 1= 1 − 
resistance of 600 0C/W. If the ambient −5  5 
temperature is 300ºC then the maximum 25
allowable power dissipation in the device will be. I DSS =
4
(a) 1.52 W (b) 1.75 W
−2I DSS
(c) 1.92 W (d) 2.00 W gm(max) =
RPSC LECTURER-10.01.2016 VP
Ans. (d) : Given, −2 × 25 1
= ×
Tjmax = 1500ºC 4 −5
θ1 = 1.000 C / W 10
=
θ2 = 6000 C / W 4
Tamb = 300ºC gm(max) = 2.5mA/V

Analog Electronics 355 YCT

117. What is the drain current for a D-MOSFET Ans. (a) :
having the characteristic values IDSS of 10 mA,
VGS(off) of –4V and VGS of + 2 V?
(a) 22.5 mA (b) 17.5 mA
(c) 12.5 mA (d) 2.5 mA
IES-2019
Ans. (a) : Given that-
IDSS = 10mA
VP = VGS( off ) = −4V
VGS = 2V
2
Given that-
 V  VTP = –1.4V
drain current ID = IDSS 1 − GS 
 VP  I DSS  VGS 
and gm = 1 −  L = 2µm, λ = 0
2
 2 VP  VP 
∴ I D = 10mA × 1 + 
 4 if IDS = –0.1mA and VDS = –2.4V
ID = 22.5mA From Circuit-
118. For an n-channel silicon JFET with a = 2 × 10–4 9–VDS–VS = 0
cm and channel resistivity ρ = 5Ω-cm, ∴ VDS = VGS → Saturation Condition
µn = 1300 cm2/V– s and ε0 = 9 × 10–12 F/m, the so, = –2.4V
pinch-off voltage, Vp, is nearly 1 W
I D = K P   ( VGS − VT )
2
(a) 2.30 V (b) 2.85 V 2  
L
(c) 3.25 V (d) 3.90 V
IES-2018 −0.1× 10−3 = × 25 × 10−6 × W
1
(–2.4+1.4)2
−6
Ans. (b) : Given that- 2 2 × 10
Channel width (a) = 2×10–4cm 1
0.1× 10−3 = × 25 × W
µn = 1300cm2/v-s 4
−12 −14
ε 0 = 9 × 10 F / m = 9 × 10 F/cm W = 16µm
ρ = 5Ω − cm applying KVL in circuit-
2 9 − VGS − I D R = 0
a
Now Vp = IDR = 9+VGS
2ερµ n
9 + VGS 9 − 2.4 6.6
a2 R= ⇒R= −3
=
ID 0.1×10 0.1×10−3
2ε0 ε r ρµ n
R = 66kΩ

=
( 2 × 10 )
−4 2
120. The data sheet for a certain JFET ( Junction
2 × 9 × 10−14 × 11.9 × 5 ×1300 Field Effect Transistor) indicates that IDSS
Where for Si, ε r = 11.7 ± 0.2 (drain to source current with gate shorted) = 15
mA and VGS(off) (Cut-off value of gate to source
VP  2.85V
voltage) = – 5V. What is the drain current for
119. The PMOSFET circuit shown in the figure has VGS = – 2V?
VTP = – 1.4 V, K P = 25 µA / V L = 2 µm, λ = 0.
' 2 (a) 58.8 mA (b) 29.4 mA
If IDS = – 0.1 mA and VDS = – 2.44 V then the (c) 9.6 mA (d) 5.4 mA
width of channel W and R are respectively: IES-2008
Ans. (d) : Given that-
I DSS = 15 mA
VGS ( off ) = −5V
VGS = –2V
VGS ( off ) = VP
(a) 16 µm and 66 kΩ (b) 18 µm and 33 kΩ  V 
2

(c) 16 µm and 33 kΩ (d) 18 µm and 66 kΩ ∴ I D = I DSS  1 − GS 

 VP 
IES-2016
Analog Electronics 356 YCT
 123. The JFET in the circuit shown in figure has an
 −2 
2

= 15 ×10−3  1 −  IDSS = 10 mA and Vp = – 5V. The value of the

 −5  resistance Rs for a drain current IDS = 6.4 mA is
15 × 10−3 × 9 (select the nearest value)
=
5× 5
27 ×10−3
=
5
ID = 5.40 mA
121. The pinch-off voltage VP = +6 V for a P- (a) 156 Ω (b) 150 Ω
channel JFET. If VGS = +2 V, what is the value
of VDS at which it will enter into saturation (c) 560 Ω (d) 1000 Ω
region ? NIELIT Scientists- 2017
(a) – 6V (b) – 4V Ans. (a) : Given,
(c) + 8V (d) + 4V IDSS = 10 mA, Vp = –5V, ID = 6.4 mA
MIZORAM PSC Jr. Grade-2018, Paper-I Rs = ?
2
IES-2007  V 
Ans. (c) : Given that- ID = IDSS 1 – GS 
VP = 6V  VP 
2
VGS = 2V ID  V 
For saturation state = 1 – GS 
IDSS  VP 
VDS = VGS+VP
VDS = 2+6 6.4 V
= 1 – GS
VDS = 8V 10 VP
122. The trans conductance 'gm' of a JFET is equal VGS 8
1− =
2I 2 VP 10
(a) − DSS (b) I DSS I DS
VP VP VGS 8
= 1−
2I DS I DSS  VGS  VP 10
(c) − (d) 1 − 
VP VP  VP  VGS 1
=
IES-1999 VP 5
Ans. (b) : The drain current in saturation for a JFET is 1
given by: VGS = −5 × V
5
2
 V  VGS = –1V
I D = I DSS  1 − GS  ..........(i)
 VP  VGS = –ID⋅RS.
1
∂I D 2I  V  Rs =
= DSS  1 − GS  ....(ii) 6.4mA
∂VGS VP  VP 
Rs = 156 Ω
2
 VGS  ID 124. In figure T1, T2 and T3 are p-channel MOS
1 −  = transistors, and T4, T5 and T6 are n-channel
 VP  IDSS
MOS transistors. A, B and C are binary
 VGS  1D signals. The output f(A, B, C) is
1 − =
 VP  I DSS
put in equation (ii)
2IDSS ID
gm =
VP I DSS

2 I2DSS I D
gm =
| VP | IDSS
2
gm = I DSS .I D
| VP |

Analog Electronics 357 YCT

 (a) A ( B + C ) (b) A + BC Ans.(a) : The relation between the drain current and
gate to-source voltage is defines.
(c) A (B + C) (d) ABC 2
BSNL (JTO)-2001  VGS 
I D = I DSS  1 −  this relation is a non linear
Ans. (a) : B and C are connected in series and A is  VP 
connected in parallel to BC The minimum current for JFET occurs of pinch off
then output (f ) = A + BC voltage defined by VGS = VP
2
= [Link]  V 
I D = I DSS  1 − GS 
= A(B + C)  VP 
125. Two MOSFETs M1 and M2 have channel When VGS = VP
widths and lengths of W, L and 2 W, L/2, and ID = 0
drain currents of ID1 and ID2, respectively.
Assuming that both M1 and M2 are On, under 127. The ideal long channel nMOSFET and
the same temperature and biasing voltages, pMOSFET devices shown in the circuits have
which one of the following is TRUE? threshold voltages of 1 V and –1V, respectively.
(a) ID2=ID1/4 (b) ID2=ID1/2 The MOSFET substrates are connected to their
(c) ID2=2ID1 (d) ID2=4ID1 respective sources. Ignore leakage currents and
DRDO-2009 assume that the capacitors are initially
discharged. For the applied voltages as shown,
Ans. (d) : MOSFET M1
the steady state voltage are _________.
channel width = W
length = L
drain current = ID1
MOSFET M2,
channel width = 2W
length = L/2
drain current = ID2
W
drain current I D1 ∝
L
kW (a) V1 = 5 V, V2 = 5 V
I D1 = .....(I) (b) V1 = 5 V, V2 = 4 V
L
where k is proportionality constant (c) V1 = 4 V, V2 = 5 V
k.2W (d) V1 = 4 V, V2 = –5 V
I D2 = GATE-2022
L/2
Ans. (c) : n MOSFET,
W
I D2 = 4k VT = 1V
L P MOSFET,
from equation (i) VTH = –1V
ID2 = 4 × I D1
126. Consider the following statements regarding
JFET:
1. The relationship between the drain
current and gate-to-source voltage of a
JFET is a nonlinear.
2. The minimum current for JFET occurs at
pinch-off voltage defined by VGS =VP.
3. A current controlled device is one in which
a current defines the operating conditions n MOFET will provide
of the device. V1 = 5V–VT
Which of the above statements are correct? = 5V –1V
(a) 1 and 2 only (b) 1 and 3 only = 4V
(c) 1, 2 and 3 (d) 2 and 3 only P MOSFET will provide
ESE-2021 V2 = 5V
Analog Electronics 358 YCT
 Ans. (b) : Given VCC = 24V
(v) Power amplifiers VL(P) = 22V
π VL (P)
η= ×100
1. Crossover distortion is the characteristic of 4 VCC
(a) Class A output stage π 22
(b) Class B output stage η = × ×100
4 24
(c) Class AB output stage = 71.99
(d) Common basic output stage 72%
UPPSC ITI Principal/Asstt. Director-09.01.2022
5. The common source stage of a CMOS amplifier
Nagaland PSC (degree) - 2018, Paper-II provides:
GPSC Asstt. Prof. 11.04.2017 (a) moderate voltage gain, low input impedance
Nagaland PSC CTSE (Degree)-2017, Paper-II and moderate output impedance
TSPSC Manager Engg-2015 (b) moderate voltage gain, high input impedance
GATE-1999 and high output impedance
Ans. (b) : Crossover distortion occurs in class B (c) moderate voltage gain, low impedance
amplifiers because the amplifier is biased at its cut-off (d) moderate voltage gain high input impedance
point. and moderate output impedance
UPMRC AM - 2020
2. Circuit diagram of a transformer coupled
Ans. (d) : The common source stage of a CMOS
audio power amplifier is shown here. Max. amplifier provides–
voltage on collector of transistor will be
1. Input impedance = High ( MΩ )
2. Output impedance = moderately high ( kΩ )
3. Voltage gain = moderately high.
6. An optical amplifier has population density of
electrons in the lower state N1 and in the higher
state N2 with relationship for high
amplification as:
(a) N2 << N1 (b) N2 < N1
(c) N2 > N1 (d) N2 = N1
UPMRC AM - 2020
Vcc
(a) Vcc (b) Ans. (c) : The energy of the emitted photon is the
2 difference between energy level.
(c) 2Vcc (d) 2Vcc E = E 2 − E1
UPPSC ITI Principal/Asstt. Director-09.01.2022 and
Ans. (b) : Transfer coupled audio power amplifier
hc
V E = hν =
vmax = cc λ
2
From population inversion condition, the higher energy
3. Operating cycle of Class-C amplifier is state E2 will have a higher population of electrons than
(a) 180º the lower energy state (E1) .
(b) Less than 180º So, N 2 > N1
(c) 360º
(d) 180º to 360º 7. In a cellphone, a power amplifier delivering
1W to the antenna may pull several watts from
UPPSC ITI Principal/Asstt. Director-09.01.2022
the battery. If the power conversion efficiency
KVS TGT (WE)- 2016 is 30% then the above cellphone translates to a
Ans. (b) : Operating cycle of class C amplifier is less power drain of:
than one - Half cycle means the conduction angle is less (a) 1 W from the battery
than 180º and its typical values is 80º to 120º. (b) 1.3 W from the battery
4. The efficiency of a Class - B amplifier for a (c) 0.3 W from the battery
supply of VCC = 24 V and peak output voltages (d) 3.33 W from the battery
VL(P) = 22 V is UPMRC AM - 2020
(a) 41.2% (b) 72% Ans. (d) : Given
(c) 19.6% (d) 29.1% Pout = 1W
UPPSC ITI Principal/Asstt. Director-09.01.2022
Efficiency ( η) = 30%
KVS TGT (WE)- 2018

Analog Electronics 359 YCT

 Pout Ans. (b) : BW1 = BW 21/ n − 1
Q η= × 100%
Pin BW1 = 20 × 103 21/ 2 − 1
So, 30 =
1
× 100 BW1 = 20 × 0.41 × 103
Pin BW1 ≅ 12.9 kHz
Pin = 3.33W
10. The class of amplifier operation characterized
8. A signal of 1 kHz is to be amplified, but the by highest efficiency, high distortion is:
circuit board and wires pick up and store 60 (a) Class - A (b) Class - B
Hz component from a nearby electric line. If (c) Class - C (d) Class - AB
this component is 40 dB higher than the desired Nagaland PSC CTSE (Diploma)-2018, Paper-I
signal, what filter stop band attenuation is
necessary to ensure the signal remains 20dB Nagaland PSC (Degree)-2018, Paper-II
above the interferer level? Nagaland PSC CTSE (Degree)-2016, Paper-II
(a) High pass filter with stop band attenuation of KVS TGT (WE)-2017, 2016
60 dB at 60 Hz UKPSC Assistant Radio Officer Screening Exam.-2011
IES-2000
(b) LPF with SBA of 60 dB at 1 kHz
(c) HPF with SBA of 60dB at 1 kHz Ans. (c) : Class-C amplifiers have high circuit
(d) Low pass filter with stop band attenuation of efficiency of about 90% and highest distortion.
60 dB at 60 Hz Power Conduction Maximum
UPMRC AM - 2020
amplifier angle Efficiency
Ans. (a) : Desired signal has a high frequency 1KHz
therefore we need to attenuate the low frequency 60Hz. Class A 360º 50%
They are used a high pass filter. Class B 180º 78.5%
Class AB 180º −360º 50 − 78.5%
Class C < 180º ≥ 90%
11. While designing a low noise amplifier, what is
the importance of the noise resistance of a
A transistor?
Q 20log10 = dB
B (a) It gives the effective impedance offered by
B the input with respect to noise current
Initially, 20log = 40 ……….. (i) (b) It defines the criterion for conjugate matching
A
of input impedance
And after passing through the filter
(c) It tells us the resistance that would generate
A the same amount of noise at room
20log = 20 ……….. (ii)
Bf temperature
From equation (i) and (ii) (d) It tells us how rapidly the noise figure
B A increases as we move away from the optimum
20log + 20 log = 60 source impedance
A Bf ISRO Scientist Engg. 2009
B A  Ans. (d) : On designing a low noise amplifier the
20log  ×  = 60 importance of the noise resistance of a transistor is that,
 A Bf  it tells us how rapidly the noise figure increases as we
B move away from the optimum source impedance.
20log = 60
Bf 12. Consider a 565 PLL with RT = 10kΩ and
B CT = 0.01 µF. what is the output frequency of
20log f = −60 the VCO?
B
So, Bf is the attenuated version of B, by an attenuation (a) 10 kHz (b) 5 kHz
factor of 60dB at 60 Hz. (c) 2.5 kHz (d) 1.25 kHz
9. An amplifier has two identical cascaded stages. IES-2009
Each stage has bandwidth of 20 kHz. The Ans. (c) : Given, RT = 10 kΩ, CT = 0.01 µF
overall bandwidth shall approximately be Output frequency of the VCO,
equal to - 1
(a) 10 kHz (b) 12.9 kHz f0 =
4R T CT
(c) 20 kHz (d) 28.3 kHz
LMRC Am (S & T), 13.05.2018 1
=
Punjab PSC Poly. Lect. 20.08.2017 4 ×10 × 10 × 0.01× 10 –6
3

AAI - 2015 = f0 = 2.5 KHz

Analog Electronics 360 YCT
13. The phase shift oscillator of fig. below operates T0 = 300 K
at f = 80 kHz. The value of resistance RF is
 2β 
Te =   T0
 NF 
Where Te = Equivalent noise temperature
T0 = ambient temperature
 2 × 50 
Te =   300K
 10 
= 3000K
16. Consider a single stage tuned amplifier having
(a) 148 kW (b) 236 kW 3 dB bandwidth of 100 kHz. Determine the
(c) 438 kW (d) 814 kW bandwidth if two such single tuned amplifiers
Mizoram PSC IOLM-2010, Paper-II are cascaded :
(a) 100 kHz (b) 10 kHz
Ans. (b) : Resistance in phase shift oscillator,
(c) 41.4 kHz (d) 64.3 kHz
1
R= ISRO Scientist Engg.-2014
2πfC 6 Ans. (d) : Given,
1 3dB BW frequency = 100 kHz
R=
2 × 3.14 × 80 × 103 × 100 × 10−12 6 n=2
1
106 106 So, over all Bandwidth = BW 2 n − 1
= =
61.5311 123.06 1

= 8.12kΩ = 100 × 103 2 2 − 1

RF = 64.34 kHz
= 29 17. In case of an ideal class-F microwave power
R
amplifier, time domain voltage and current
RF = 29R
waveform of the device have:
RF = 29× 8⋅12 = 235.48kΩ (a) 50% overlap
RF 236KΩ (b) Maximum overlap
(c) No overlap
14. Approximate equivalent noise temperature (d) Less than 80% overlap
(deg. K) of an amplifier with a noise factor of
ISRO Scientist Engg. -2015
1.04 is
Ans. (c) : In Class-F microwave power amplifier there
(a) 301.6 (b) 11.6
is no overlap of time domain voltage and current
(c) 278.4 (d) 5.8 waveform of the device.
ISRO Scientist Engg. 2009 18. DC to RF efficiency of an ideal class-F
Ans. (b) : Given, Noise factor (F) = 1.04 amplifier is:
Equivalent noise temperature Teq = T0 ( F − 1) (a) 100% (b) 78.4%
(c) 50% (d) < 80%
Where,
ISRO Scientist Engg. -2015
T0 = 290 K(standard noise temperature)
Ans. (a) : For ideal class-F amplifier
Teq = T0(F-1)
= 290×(1.04–1) ηdc / rf = 100%
= 290×0.04 Class-F amplifier are capable of high efficiency of more
Teq = 11.6 K than 90%.
19. For a class B amplifier providing a 20V peak
15. An amplifier has a gain of 50 dB, and noise
signal to 16Ω load and a power supply of VCC =
figure of 10 dB. Assuming an ambient
30V, the efficiency will be.
temperature of 300 K, what will be the total
(a) 52.3% (b) 25.65%
equivalent noise temperature at the input of the
(c) 75% (d) 78.6%
amplifier? DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
(a) 760 K (b) 360 K ISRO Scientist Engg.-2011
(c) 2700 K (d) 3000 K Ans. (a) : Given, Peak voltage Vm = 20
ISRO Scientist Engg.-2014 RL = 16Ω
Ans. (d) : Given, VCC = 30V
Gain ( β ) = 50 dB 2V 2 × 20
Idc = m = = 0.796A
Noise figure (NF) = 10dB πR L π× 16

Analog Electronics 361 YCT

Pdc = VCC × Idc = 30 × 0.796 = 23.9W Ans. (d) : A class-D amplifier or switching amplifier is
Q Power delivered by load an electronic amplifier in which the amplifying devices
operates as a electronic switch and this switches are
Vm2 400 mostly MOSFETs power switches.
PL = = = 12.5W
2R L 32 25. The power rating of the amplifier is 100 watts
So, the efficiency of class B amplifier- then the transistor can only operate at______
P × 100 12.5 × 100 (a) Power higher than 100 W
η(%) = L = = 52.3% (b) Power lower than 100 W
Pdc 23.9
(c) Power near to 100 W
20. Which of the following principles is applied (d) Power lower than 200 W
while designing the output matching network
Nagaland PSC (CTSE) Diploma-2017, Paper II
for a high power Class-C amplifier?
(a) Maximum Power Transfer Theorem Ans. (b) : If the power rating of the amplifier is 100W
(b) Norton's Theorem that is maximum allowable power uses of a transistor
beyond which it may damage. If power is less than
(c) Thevenin's Theorem
100W, the circuit operates perfectly.
(d) Power = (voltage)2/RL
ISRO Scientist Engg.-2010 26. Input stage of power amplifier is also
called_____
Ans. (a) : Maximum power transfer theorem is applied
(a) First op (b) Beginning stage
while designing the output matching network for a high
power class-C amplifier. (c) Front end (d) Normal stage
Nagaland PSC (CTSE) Diploma-2017, Paper II
21. Which device was used for the amplification of
audio signals before the invention of power Ans. (c) : Input stage of power amplifier is also called
amplifiers? the front end amplifier.
(a) Op - amp (b) Vacuum tubes 27. For a perfect power amplifier output power
(c) SCR (d) Diode rating will be______if the output impedance is
Nagaland PSC (CTSE) Diploma-2017, Paper II halved.
Ans. (b) : Before the invention of power amplifier, (a) Halved (b) Squared
vacuum tubes are used for audio signal amplification (c) Doubled (d) Square rooted
which consumes large space and costly. Nagaland PSC (CTSE) Diploma-2017, Paper II
22. Power amplifier directly amplifies______ Ans. (c) : The power is proportional to the square of the
(a) Voltage of signal voltage and inversely proportional to the resistance, if
(b) Current of the signal output impedance is halved then output power will be
(c) Power of the signal doubled.
(d) All of the mentioned 28. Transistor in power amplifier is_______
Nagaland PSC (CTSE) Diploma-2017, Paper II (a) An active device
Ans. (d) : A power amplifier is designed to increase the (b) A passive device
magnitude of power of a given input signal. Power (c) A on-amp
amplifiers increases voltage as well as current. Increase (d) A voltage generating device
in voltage or current is small as compared to normal Nagaland PSC (CTSE) Diploma-2017, Paper II
amplifier. Ans. (a) : A transistor is an active device since
23. Which of the following audio speaker will be transistor contain voltage source which are necessary
hard to be driven by a power amplifier? for amplification.
(a) 4 ohm (b) 8 ohm 29. A tuned amplifier uses…………load
(c) 12 ohm (d) 2 ohm (a) Resistive (b) Capacitive
Nagaland PSC (CTSE) Diploma-2017, Paper II (c) LC tank (d) Inductive
Ans. (d) : If the resistance of the audio amplifier is less, Nagaland PSC (CTSE) Diploma-2017, Paper II
the output power of the transistor will be high since, KVS TGT (WE)- 2017
output current is increasing. Ans. (c) : The tuning circuit can be built with various
Hence, to drive a 2 Ω speaker twice as much power is components like inductor (L) and capacitor (C). The
required as compared to a 4 Ω speaker. parallel combination of the inductor and capacitor is
24. Which of the stages listed below would drive called a tuned circuit. So, a turned amplifier uses LC
the loudspeaker, in a class D amplifier? tank load.
(a) A comparator 30. Which of the following is NOT amplified by an
(b) A low pass filter amplifier?
(c) A pulse width modulator (a) current (b) resistance
(d) A mosfet power switch (c) power (d) voltage
Nagaland PSC (CTSE) Diploma-2017, Paper II RRB SSE 03.09.2015 Shift-II
Analog Electronics 362 YCT
Ans. (b) : Amplifier circuit is an electronics circuit in Ans. (c) :
which input is low quality signal and gives output as
strong signal. Commonly transistors are used for the Power Conduction Maximum
process of amplification, amplify the signal current, amplifier angle Efficiency
power and voltage but can not amplify resistance.
Class A 360º 50%
31. Linear amplifier with a gain of 30 dB is fed
with 1.0µW power, the output power of the Class B 180º 78.5%
amplifier Class AB 180º −360º 50 − 78.5%
(a) 1.0 W (b) 0 dBm
(c) 30 dBm (d) -30 dBm Class C < 180º ≥ 90%
ISRO Scientist Engg.-2006 34. Harmonic generators use which amplifier?
Ans. (b) : Given, (a) class- A (b) class- AB
Pin = 1µW (c) class- C (d) class- B
Mizoram PSC AE/SDO-2012 Paper-III
gain = 30dB
Ans. (c) : Harmonic generators use class-C amplifier.
We known- Application of Class C amplifier
P • RF oscillators • Booster amplifier
gain = 10log10 out
Pin • RF amplifier • High frequency repeaters
P • FM transmitters • Tuned amplifier
30 = 10log10 out 35. A cascaded amplifier has the advantage of
1µW
(a) Low input capacitance
P
3 = log10 out (b) Low input impedance
1µW (c) High trans conductance
P (d) Large voltage gain
103 = out Mizoram PSC IOLM -2018, Paper II
1µW
Pout = 1mW Ans. (a) : A cascaded amplifier has the advantage that it
has low input capacitance.
P0 ( dBm ) = 0
36. An amplifier circuit has an overall current gain
32. An amplifier has an input power of 2 of -100 and an input resistance of 10kΩ with a
microwatts. The power gain of the amplifier is load resistance of 1 kΩ. The overall voltage
60 dB. The output power will be gain of the amplifier is
(a) 6 microwatts (b) 120 microwatts (a) 5 dB (b) 10 dB
(c) 2 microwatts (d) 2 watts (c) 20 dB (d) 40 dB
ISRO Scientist Engg.-2008 Mizoram PSC IOLM -2018, Paper II
Ans. (d) : Power gain = 10 log Ap Ans. (c) : β = 100
 P0  input impedance R1 = 10 kΩ
60 = 10 log10  
output impedance R2 = 1 kΩ
 Pi 
R
 P0  Voltage gain Av = β× 2
6 = log10   R1
 Pi 
1
P0 = 100 × = 10
10 =
6
10
Pi Voltage gain (in dB) = 20log1010
P0 = Pi × 106 = 20 dB
−6 37. Heat sink are used in the power amplifier
= 2 × 10 × 10 6

= 2W circuits
(a) To increase the output power
33. For power amplifiers, which of the statements
are correct. (b) To reduce the heat losses in the transistor
I. Class A : The output stage conducts for a full (c) To increase the voltage gain of the power
360 0 amplifier
II. Class B : The output stage conducts for 180 0 (d) To increase the collector dissipation rating of
III. Class C : The output voltage conducts for the transistor
0 Mizoram PSC IOLM -2018, Paper II
more than 180
IV. Class B : The maximum efficiency is 78.5% Ans. (d) : Heat sink are used for power transistor as the
(a) I. II and III (b) II and III power dissipated at their collector junction is large.
(c) I, II and IV (d) I, II, III and IV By using heat sink, thermal runaway can be prevented
RPSC ACF & FRO 23.02.2021 and power handling capacity can be increased.

Analog Electronics 363 YCT

38. An amplifier has an output signal power of 10 Ans. (d) : In Class-B amplifier, the maximum power
W and an output noise power of 0.01W. The
V2
signal-to-noise power ratio is Pmax = CC
(a) 10 dB (b) 20 dB 2.R L
(c) 30 dB (d) 60 dB 43. Conduction extends over 3600 in a class A
Mizoram PSC IOLM-, Paper-III amplifier because Q point is
Ans. (c) : Given, (a) Centred on load line
Output signal power (Ps) = 10W, (b) Located at or near cut off point
Output noise power (PN) =0.01W (c) Located on load line
(d) Located near saturation point
P  MPPSC Forest Service Exam.-2014
SNR = 10log  s  dB
P
 N Ans. (a) : In class A amplifier conduction extends over
3600 because the operating point is located in the centre
 10 
= 10 log   of load line, because it provide less distortion.
 0.01  44. The bandwidth of a Class C amplifier
= 10 log101000 decreases when the
= 10 × 3 (a) Resonant frequency increases
(SNR)dB = 30 dB (b) Q increases
39. Class - C power amplifiers are generally- (c) XL decreases
(a) Low frequency amplifier (d) Load resistance decreases
(b) Wide band amplifier Nagaland PSC CTSE (Degree)-2016, Paper-II
(c) Transformer coupled between stages 1
(d) Tuned RF amplifier Ans. (b) : We know that, Q ∝
BW
UPPCL AE-16.11.2013 So, bandwidth of class-C amplifier decreases with the
Ans. (d) : The Class-C power amplifier is one kind of quality factor(Q) increases.
amplifier, where the transistor conduct for less than 45. In class B Push-pull operation the power
180º. A Class-C amplifier is used in the applications delivered to the load RC = 8 ohms is Pac=16
like RF oscillator and RF tuned amplifier. watts. Then the Peak load current Im is given
40. Which of the following indicates 2nd harmonic by
distortion in power amplifier? (a) 16 amp (b) 2 amp

(a)
A2
(b)
A3 1
(c) 2 amp (d) amp
A1 A2 2
A4 A1 Nagaland PSC CTSE (Degree)-2016, Paper-II
(c) (d)
A2 A2 Ans. (c) : Given, Pac = 16 watt RC = 8 Ω,
SAIL- 2014 We know, Pac = I m × R C
2

nd
Ans. (a) : 2 harmonic distortion in power amplifier P 16
A2 ⇒ I m = ac = = 2 amp
indicates . R C 8
A1 46. The reason for cross-over distortion in a push-
41. Transconductance amplifier is a pull amplifier is that
(a) Voltage to current converter (a) The transistors are overdriven at the cross-
(b) Current to voltage converter over points
(c) Current controlled current source (b) Current switching from one transistor to
(d) Voltage controlled voltage source another
TNPSC AE-2014 (c) The combined transfer characteristics of the
two transistors in most non linear at zero base
Ans. (a) : Transconductance amplifier– The current
transconductance amplifier is an amplifier whose (d) The input signals rise fast at its zero
differential input voltage produces an output current. Nagaland PSC CTSE (Degree)-2016, Paper-II
Thus, it is a voltage controlled current source.
Ans. (b) : The reason for cross-over distortion in a
42. In Class-B amplifier, the maximum power Pmax push-pull amplifier is that Current switching from one
equals transistor to another.
VCC2 VCC
(a) (b)
RL 2R L
VCC2 VCC2
(c) (d)
2 RL 2R L
TNPSC AE-2013
Analog Electronics 364 YCT
47. Which distortion is least objectionable in case Ans. (d) : Given,
of audio amplifiers? Zero signal power dissipation, Pdc = 10Watt
(a) Phase distortion
(b) Frequency distortion A.C Power output, P0 = 4W
(c) Harmonic distortion P0
(d) Inter-modulation distortion So, collector efficiency = × 100
Pdc
Nagaland PSC CTSE (Degree)-2016, Paper-II
4
Ans. (a) : Phase distortion is least objectionable in case = × 100
of audio amplifiers. 10
= 40%
48. Which class of amplifier has the lowest
collector circuit efficiency 53. In an amplifier, fT is the unit gain frequency. If
(a) A (b) AB gain increased by 25%, then effect on Band
(c) B (d) C Width?
Nagaland PSC CTSE (Diploma)-2018, Paper-I (a) Increased (b) Decreased by 20%
(c) No change (d) Decreased by 25%
Ans. (a) : Class A amplifier has lowest efficiency and
SAIL- 2014
the efficiency of this amplifier is 50%.
Ans. (b) : Unit gain frequency = gain × BW
Power Conduction Maximum  25 
G1 × BW1 = 100 +  G1 × BW2
amplifier angle Efficiency  100 
Class A 360º 50% 5
BW1 = BW2
Class B 180º 78.5% 4
Class AB 180º −360º 50 − 78.5% 4
BW2 = BW1
Class C < 180º ≥ 90% 5
 1
49. Crossover distortion takes place in BW2 = 1 −  BW1
(a) Tunned amplifier  5
(b) Power amplifier BW2 = Decreased by 20%
(c) Small signal amplifier Hence, bandwidth is decreased by 20%
(d) Video amplifier 54. The bandwidth for double tuned amplifier is 20
Nagaland PSC CTSE (Diploma)-2018, Paper-I kHz. Calculate the bandwidth if such three
Ans. (b) : Cross over distortion takes places in push stages are cascaded –
pull amplifier. A push pull amplifier is basically a (a) 7.14 kHz (b) 14.28 kHz
power amplifier because of it is used to supply high (c) 21.42 kHz (d) 28.56 kHz
power to the load. RPCS Lect.-2011
50. Which power amplifier can deliver maximum Ans. (b) : (BW)1 = 20 kHz
load power? If 'N' identical double tuned amplifier are cascaded then
(a) Class A (b) Class AB overall B.W. will be
(c) Class B (d) Class C BW = (BW)1 4
21/ N − 1
Mizoram PSC Jr. Grade-2015, Paper-II
Ans. (d) : The efficiency of class C amplifier is high. BW = 20k 4 21/ 3 − 1
So by using class-C amplifier we can deliver the BW = 14.28 kHz
maximum load power. 55. The advantage of using a class-B push pull
51. In class-A power amplifier the collector transistor amplifier over a class-A push pull
dissipation is maximum when transistor amplifier is
(a) No signal is present (a) A negligible power loss at no input signal
(b) Signal swing is maximum (b) Harmonic distortion is lower
(c) Signal swing is (1/2) of its maximum (c) Self bias can be used
(d) None of the above (d) Supply voltages have good regulation
Mizoram PSC IOLM-2010, Paper-II IES-2020
Ans. (a) : In class-A power amplifier the collector Ans. (a) : The advantage of using a class-B push pull
dissipation is maximum when no signal is present. transistor amplifier over a class-A push pull transistor
52. A power transfer used in class A amplifier has amplifier is a negligible power loss at no input signal.
zero signal power dissipation of 10 Watts. If the The only difference is that there are no biasing resistors
AC power is 4 W. Calculate collector efficiency. for a class-B push pull amplifier. Class-A amplifier
(a) 60% (b) 30% produces least distortion in the output among all power
(c) 90% (d) 40% amplifier. In class-B amplifier, quiescent power (Q-
RPCS Lect.-2011 power) dissipation is almost zero.

Analog Electronics 365 YCT

56. The Class-B push-pull amplifier is an efficient 2
two-transistor circuit, in which the two IC max =
transistors operate in the following way: 12
(a) Both transistors operate in the active region IC max = 0.16667 amp, IC max = 166.7 mA
throughout the negative ac cycle
59. A power amplifier with a gain of 100 ∠0º has
(b) Both transistors operate in the active region an output of 12 V at 1.5 kHz along with a
for more than half-cycle but less than a whole second harmonic content of 25 percent. A
cycle. negative feedback is to be provided to reduce
(c) One transistor conducts during the positive the harmonic content of the output to 2.5
half-cycle and the other during the negative percent. What should be the gain of the
half-cycle feedback path and the level of signal input to
(d) Full supply voltage appears across each of the the overall system, respectively?
transistors. (a) 0.9 and 0.12 V (b) 0.9 and 12 V
IES-2016 (c) 0.09 and 1.2 V (d) 9 and 0.12 V
Ans. (c) : The class-B push pull amplifier is an efficient IES-2014
two-transistor circuit, in which the two transistors Ans. (c) : Given,
operate as one transistor conducts during the positive Gain A = 100, Output signal level = 12 V
half-cycle and the other during the negative half-cycle. 2nd harmonic distortion becomes 2.5% from 25%
25
Distortion reduced by factor = = 10
2.5
Distortion Reduced by factor = (1 + Aβ)
10 = 1 + Aβ
Aβ = 9
57. Which of the following is the principle factor
that contributes to the doubling of the 9
β= = 0.09
conversion efficiency in a transformer coupled 100
amplifier? Gain of the output signal level
(a) Reducing the power dissipated in the = Distortion Reduced by factor × Input signal level.
transistor Output signal level = (1 + Aβ) × input signal level
(b) Eliminating the power dissipation in the Output signal level
transformer Input signal level =
(c) Elimination of dc power dissipation in the (1 + Aβ)
load 12
=
(d) Impedance matching of the transformer 10
LMRC AM- 16.07.2021 Input signal level = 1.2 V
IES-2015
Ans. (c) : Elimination of DC power dissipation in the 60. An output signal of a power amplifier has
load is the principle factor that contributes to the amplitudes of 2.5 V fundamental, 0.25 V
doubling of the conversion efficiency in a transformer second harmonic and 0.1V third harmonic.
coupled amplifier. Conversion efficiency is a measure The total percentage harmonic distortion of
of the ability of a power amplifier to convert DC power the signal is
into AC power. (a) 12.8% (b) 10.8%
AC output power (c) 6.4% (d) 1.4%
η= IES-2012
DC power taken from biasing supply
Ans. (b) : Give, First Harmonic, D1 = 2.5 V
P Second Harmonic, D2 = 0.25 V
%η = AC × 100%
PDC Third Harmonic, D3 = 0.1 V
Total percentage harmonic distortion of signal -
58. A power amplifier operated from 12 V battery 2 2
gives an output of 2W. The maximum collector  D 2   D3 
current in the circuit is THD% =   +   × 100
 D1   D1 
(a) 166.7 µA (b) 166.7 mA
(c) 166.7 A (d) 16.67 mA 2
 0.25   0.1 
2

IES-2015 THD% =    +  ×100

 2.5   2.5 
Ans. (b) : Given,
VCC = 12 V, Pout = 2W 1 1
THD% = + × 100
P = VI, Pout = VCC. IC 100 625
P THD% = 10.777%
IC max = out
VCC THD% ≈ 10.8%

Analog Electronics 366 YCT

61. Using transistors, 64. Consider the following?
1. Class-A power amplifier has a minimum 1. Distortion
efficiency of 50%. 2. Gain
2. Class-B push-pull power amplifier gives
rise to crossover distortion. 3. Bias stabilization
3. Class AB push-pull power amplifier has 4. Sensitivity
higher efficiency than Class-B power 5. Frequency response
amplifier. Which of these properties of the Power
4. Class-C power amplifier is generally used Amplifier one should concentrate upon while
with tuned load for RF amplifications. designing a good Power Amplifier circuit?
Which of these statements are correct? (a) 1, 2 and 3 (b) 1, 3 and 4
(a) 1, 2, 3 and 4 (b) 2 and 4 only
(c) 2, 3 and 4 (d) 4 and 5
(c) 3 and 4 only (d) 1 and 3 only
KVS TGT (WT)-2018 IES-2009
Kerala PSC Lecturer (NCA)-04.07.2017 Ans. (a) : Following properties of the power amplifier
IES-2011 should be considered while designing a good power
Ans. (b) : • Class-B push-pull power amplifier gives amplifier circuit-
rise to crossover distortion. • High gain
• Class-C power amplifier is generally used with • Bias stabilization
tuned load for RF amplifications. • Less distortion.
Power Amplifier Efficiency 65. What is the collector circuit efficiency of a class
Class -A 50% (Maximum) B push-pull amplifier if
Class-B 78.5% Vm = peak load voltage, and
Class-AB 50-78.5% VCC = collector supply voltage
Class-C 87.5% π Vm π Vm
62. Which one of the following statements is not (a) η = × 100% (b) η = × 100%
correct with regard to Power Amplifier? 4 VCC 2 VCC
(a) The collector current is large. π VCC π VCC − Vm
(b) They are used as the front end of multistage (c) η = × 100% (d) η= ×100%
2 Vm 4 Vm
Amplifiers.
(c) They are used near the end of the multistage IES-2008
Amplifiers. Ans. (a) : Efficiency of a class B push-pull amplifier
 1  Vm = Peak load voltage
(d) They have a high power rating  > W  . VCC = Collector supply voltage
 2 
IES-2009 1
AC output power PAC = Vm .I m
Ans. (b) : Power amplifiers are not used as the front end 2
of multistage amplifiers. Power amplifiers are used only 2V .I
near the end of multistage amplifier. DC input power, PDC = CC m
π
Power amplifier uses special transistor called power
transistor which has greater power rating and large AC output power
Efficiency η% = × 100
collector current. DC power taken fromsupply
63. Consider the following statements regarding PAC
the Class-B power Amplifiers (Complement- η% = × 100
ary symmetry type). PDC
1. The efficiency of the Amplifier is higher than 1
that of class-A Amplifier. Vm .I m
2. The power output is low. η% = 2 × 100
2VCC .Im
3. Cross-over distortion is present.
4. The standby power dissipation is absent. π
Which of the statements are correct? π V
η% = . m × 100%
(a) 1, 2 and 3 (b) 1, 2 and 4 4 VCC
(c) 1, 3 and 4 (d) 2, 3 and 4
IES-2009 66. In a class A amplifier, VCE(max) = 15 V and
Ans. (c) : 1. The efficiency of the amplifier is higher VCE(min) = 1V. The conversion efficiency for a
than that of class-A amplifiers. series fed load will be equal to
2. Class-B amplifier suffers from the problem of (a) 25% (b) 23.33%
crossover distortion. (c) 12.5% (d) 11.67%
3. The output of power amplifier is high. IES-2008
4. The standby power dissipation is absent. Mizoram PSC [Link] 2018, Paper-II
Analog Electronics 367 YCT
Ans. (b) : Given, VCC = VCE(max) = 15 V 69. In an amplifier, the power output is 2W at 5
VCE(min) = 1 V kHz, and 0.5 W at 50 Hz. If the input power is
P constant at 10 mW, what is the variation
Conversion Efficiency % η = AC × 100% (approximate) of power gain in dB at two
PDC frequencies? (log102 ≈ 0.30)
1 V (a) 6 dB (b) 8 dB
%η = . m × 100%
4 VCC (c) 3 dB (d) 16 dB
∵ Vm = (VCC – Vmin) IES-2007
Ans. (a) : Given,
1 V − Vmin
%η = . max × 100 Output power, Pout = 2 W
4 Vmax Input power, Pin = 0.5 W
15 − 1 P 
= ×100 Variation of Power gain (in dB) = 10log10  out 
4 × 15
1400  Pin 
=  2 
60 = 10log10  
%η = 23.33%  0.5 
= 10log10 4
67. Match List-I (Name of the circuit) with List-II
(Property of the circuit) and select the correct = 10log1022
answer using the codes given below the lists: = 20log102
List-I List-II = 20×.30 = 6dB
A. Preamplifier 1. Non-linear circuit Variation = 6dB
B. Power amplifier 2. Lumped, linear,
passive, bilateral, 70. A power supply has a full-load voltage of 24 V.
finite circuit What is its no-load voltage for 5% regulation
C. Rectifier circuit 3. Large signal (rounded off do the nearest integer)?
amplifier (a) 12 V (b) 23 V
D. Purely resistive 4. Small signal (c) 25 V (d) 6 V
circuit amplifier IES-2007
Codes: Ans. (c) : Given,
A B C D No load voltage VNL = ?
(a) 4 2 1 3
Full load voltage VFL = 24 V
(b) 1 3 4 2
(c) 4 3 1 2 % Regulation R = 5%
(d) 1 2 4 3 V − VFL
%R = NL × 100%
IES-2008 VFL
Ans. (c) : Preamplifier is a small signal amplifier.
V − 24
Power amplifier is large signal amplifier. 5 = NL ×100
Rectifier circuit consist of non-linear circuit element. 24
Lumped, linear, passive, bilateral and finite circuits VNL = 1.2 + 24
are purely resistive circuit. VNL = 25.2 Voltage
68. In a class-B push-pull operation, the d.c. power
drawn is 28 W. What is the power delivered by VNL ≃ 25Volt
the amplifier at the ideal maximum efficiency
of power conversion? 71. Match List-I (Type of Amplifier) with List-II
(a) 28W (b) 14W (Property) and select the correct answer using
(c) 22W (d) 7W the codes given below the lists:
IES-2007 List-I List-II
Ans. (c) : Given, A. Single ended 1. Medium efficiency with
We know that efficiency for class-B amplifier. class A minimum distortion
η = 78.5 % (for Class B amplifier) B. Class AB 2. High efficiency with
Pin (max) = 28 W push-pull crossover distortion
Pout(max) = η Pin (max) C. Class B 3. Harmonic generator

Pout(max) =  78.5  push-pull with highest possible
 × 28 conversion efficiency
 100 
Pout(max) = 21.98 W D. Class C 4. Poor conversion
Pout(max) ≃ 22W efficiency with minimum
distortion.
Analog Electronics 368 YCT
 Codes: 24
A B C D =
0.8
(a) 2 3 4 1
Pin = 30 W
(b) 4 1 2 3
(c) 2 1 4 3 Current drawn from Battery,
(d) 4 3 2 1 P 30
Iin = in =
IES-2005 Vin 12
Ans. (b) : Class-A Amplifier :- In class-A amplifier, its Iin = 2.5 A
conversion efficiency is (25 to 50)%. In this power
amplifier quiescent power (Q-power) dissipation is very 74. The power input to an amplifier is 2µW. The
large. power gain of the amplifier is 40 dB. The
Class-B Amplifier - In this amplifier we get high output power of the amplifier is
efficiency (78.5%) with crossover distortion. (a) 80 µW (b) 200 µW
Class-AB push-pull amplifier - In this amplifier we (c) 20 mW (d) 80 mW
get medium efficiency (50% to 78.5%) with minimum RPSC Vice Principal ITI -2016
distortion. IES-2002
Class-C Amplifier - In this amplifier we get maximum Ans. (c) : Given,
efficiency (87.5%) with Harmonic generator class-C Input Power, P = 2µW
in
amplifiers output is heavily distorted.
Power Gain in dB, A ( dB ) = 40dB
72. An amplifier has a D.C. power supply of 15V
and draws a current of 10 mA. It produces an A ( dB ) = 10 log ( A )
output of 5V peak across a load resistance of
40 = 10log ( A )
600Ω for a signal frequency of 1 kHz. What
will be its A.C. power output? A = 104
(a) 260 mW (b) 20.8 mW A = 10000
(c) 520 mW (d) 40.6 mW
P
IES-2004 Gain, A = out
Pin
Ans. (b) : Given,
Peak voltage, VP = 5 V, P out = A × P in

Load Resistance, RL = 600Ω = 10000 × 2 × 10–6

= 10 4 × 2 × 10 −6
VP2
Po( ac ) = Pout = 20 mW
2R L
52 75. A class-B push-pull type amplifier with
Po ( ac ) = transformer coupled load used two transistors
2 × 600 rated 10W each. What is the maximum power
25 output one can obtain at the load from this
= circuit?
1200
(a) 40 W (b) 50 W
Po( ac ) = 20.8mW (c) 60 W (d) 70 W
73. A D.C. to D.C. converter has an efficiency of IES-2002
80% and is supplying a load of 24 W at 240 V. Ans. (b) : Given,
What is the current drawn from the battery if Power dissipation across each transistor = 10W
the converter is working from a battery of Total rating of transistor = 20W.
12V? Class-B push pull amplifier figure of merit (F) = 0.4
(a) 0.1 A (b) 2.0 A Pdc( max )
(c) 2.5 A (d) 10 A ∵ Figure of merit (F) =
PAC( max )
IES-2004
Ans. (c) : Given, 20
PAC( max ) = = 50Watt
Efficiency, η = 80% = 0.8 0.4
Input voltage, Vin = 12 V 76. Consider the following statements:
Output Power Po = 24 W Sziklai pair
P 1. Is also called complementary Darlington
η= o 2. Acts like a single p-n-p transistor with a
Pin
very high current gain
Po 3. Can be used in class B push-pull power
Pin =
η amplifier

Analog Electronics 369 YCT

 Which of these statements are correct? 0.1×10−6
(a) 1 and 2 (b) 1 and 3 D% = × 100
5 × 10−6
(c) 2 and 3 (d) 1, 2 and 3 D = 0.02 × 100
IES-2000
D = 2%
Ans. (b) : Sziklai pair :-
79. Consider the following statements:
A class-B amplifier
1. Is biased just at cut-off
2. Has a high theoretical efficiency of 78.5%
because its quiescent current is low.
3. Is biased at the mid-point of load line
of these statements
(a) 2 and 3 are correct (b) 1 alone is correct
(c) 2 alone is correct (d) 1 and 2 are correct
TSPSC Manager (Engg.)-2015
TNPSC AE-2008, IES-1998
Ans. (d) : An amplifier in which operating point is
located at an extreme end of load line (i.e. either in
Sziklai Pair transistor is also known as compound or saturation region or in cut-off region) is known as
pseudo-Darlington pair. This transistor pair consists of Class-B amplifier.
two bipolar transistor pairs, where one is npn and A Class-B amplifier has a high theoretical efficiency
another is pnp. of 78.5% because its quiescent current is low.
The Sziklai pair looks similar to the Darlington pair. 80. The dissipation at the collector is zero in the
Sziklai pair is also called complementary Darlington. quiescent state and increase with excitation in
Sziklai pair can be used in class B push-pull power the case of a
amplifier. (a) Class A series-fed amplifier
77. Which of the following contributes to (b) Class A transistor coupled amplifier
harmonics distortion in amplifiers? (c) Class AB amplifier
(a) Non-linearity in active device (d) Class B amplifier
(b) defective device IES-1997
(c) presence of noise Ans. (d) : The dissipation at the collector is zero in the
(d) positive feedback quiescent state and increase with excitation in the case
RRB SSE 21.12.2014, (Yellow) of a Class-B amplifier. In Class-B amplifier output
signal is half-sinusoidal or distorted.
Ans. (a) : Harmonics distortion in amplifier is mainly
caused by the nonlinearities of the active elements 81. Match List-I with List-II and select the correct
(transistors). answer using the codes given below the lists:
Harmonics distortion is the distortion in output List-I List-II
waveform due to the generation of harmonics. (Amplifier type) (Circuit/property)
A. Class A single 1. Requires PNP
78. If a class-C power amplifier has an input signal
ended & NPN
with frequency of 200 kHz and the width of transistor pairs
collector current pulses of 0.1 µs, then the duty
B. Class B push pull 2. Prevents cross-
cycle of the amplifier will be
transformer over distortion
(a) 1 % (b) 2 % coupled
(c) 10 % (d) 20 % C. Class AB push- 3. has maximum
IES-1999 pull efficiency
Ans. (b) : Given, among these
Frequency, f = 200 kHz amplifiers
Pulse width, τ = 0.1 µs D. Class AB 4. Has minimum
= 0.1 × 10–6sec complementary efficiency
symmetry among these
1
Time period, T = amplifiers
f Codes:
1 A B C D
=
200 × 103 (a) 4 3 2 1
T = 5 µsec (b) 4 2 3 1
T = 5 × 10–6 sec (c) 1 2 3 4
τ (d) 3 2 1 4
For class-C amplifier duty cycle D = IES-1996
T
Analog Electronics 370 YCT
Ans. (a) : Class-A amplifier has minimum efficiency C. Complementary 3. A Circuit with
among all amplifier. Its conversion efficiency is (0 to Symmetry overall voltage
50%). Amplifier gain close to 1
Class-B push pull transformer coupled amplifier has and very large
maximum efficiency among the given amplifiers. input
Class-AB push-pull amplifier prevents cross-over impedance.
distortion. D. Cascode 4. A Circuit with
Class-AB complementary symmetry requires PNP Amplifier low input
and NPN transistor pairs. impedance
82. A class-B push-pull power amplifier uses two mainly used in
transistor each having a power dissipation high frequency
capacity of 2 watts. The maximum power that applications.
the circuit can deliver to the load without Codes:
extending the power dissipation capacity of the A B C D
transistor is (a) 1 2 3 4
(a) 1 Watts (b) 2 Watts (b) 2 1 4 3
(c) 5 Watts (d) 10 Watts (c) 3 4 1 2
IES-1995 (d) 4 3 2 1
Ans. (b) : The push-pull amplifier is a power amplifier IES-1994
is used in the output stages of electronic circuits. It is Ans. (c) :
used whenever high output power at high efficiency is • Darlington amplifier is a circuit with overall voltage
required. In the Class-B push-pull amplifier at a time gain close to 1 and very large input impedance.
only one transistor will be conduct. Hence overall • Common base amplifier is a circuit with low input
power dissipation will be equal to that of a single impedance mainly used in high frequency
transistor Pd = 2 watt. applications.
83. Consider the following statements: • Complementary symmetry amplifier is a circuit using
A power amplifier uses bridge rectifier with two (npn and pnp) transistors used in power
capacitor input filter. If one of the diode is amplifier.
defective, then. • Cascode amplifier is a common-source amplifier
1. The dc load voltage will be lower than its driving a common gate amplifier.
expected value.
85. Match the following:
2. Ripple frequency will be lower than its
expected value List-I List-II
3. The surge current will increase many fold. (efficiency) (class of amplifier)
Which of the statements are correct A. < 50% (1) A
(a) 1 and 2 are correct B. > 50% (2) AB
(b) 1 and 3 are correct C. 78.5% (3) B
(c) 2 and 3 are correct D. 100% (4) C
(d) 1, 2 and 3 are correct Codes:
IES-1995 A B C D
(a) 2 1 4 3
Ans. (d) : A power amplifier used bridge rectifier with
(b) 1 3 4 2
capacitor input filter. If one of the diode is defective,
then the DC load voltage will be lower than its expected (c) 1 2 3 4
value. The surge current will increase many fold. (d) 4 1 2 3
84. Match List-I with List-II and select the correct KVS TGT (WE)- 2016
answer using the codes given below the lists: IES-1991
List-I List-II Ans. (c) :
(Name of the circuit) (Characteristics of Class of Amplifier Efficiency
the circuit) Class-A 50% (Maximum)
A. Darlington 1 A circuit using Class-B 78.5%
Amplifier pnp and npn Class-AB 50% - 78.5%
transistors used
in power Class-C >90%
amplifier. 86. An amplifier has an input power of 2
B. Common base 2. A Common- microwatts. The power gain of the amplifier is
Amplifier source Amplifier 60 dB. The output power will be
driving a (a) 6 microwatts (b) 120 microwatts
common gate (c) 2 milliwatts (d) 2 watts
amplifier. IES-1991
Analog Electronics 371 YCT
Ans. (d) : Given, Pi = 2 µW = 2 × 10–6 W 89. For a class-A FET power amplifier with 10V
Gain = 60 dB drain supply and 2A drain current bias
providing RF load current of 1A amplitude.
Gain ( dB ) = 10log ( Gain ) What is the DC to RF efficiency for load
60 = 10 log (Gain) resistance of 5Ω?
Gain = 106 (a) 50% (b) 25%
(c) 35% (d) 12.5%
Pout ISRO Scientist Engg. -2015
Gain =
Pin Ans. (d) : Given,
Pout Drain supply voltage VDD = 10V, Drain current ID = 2A
10 =
6

2 × 10−6 RF load current IL = 1A =

1
A(r.m.s value)
Pout = 2W 2
Load resistance RL = 5Ω
87. Match List-I with List-II and select the correct
answer using the codes given below the lists: V ×I
% RF efficiency η = CE L × 100
List-I List-II VDD × I D
(Maximum (Amplifiers) 2
efficiency in  1 
I 2L × R L   ×5
percentage)
= × 100 =  2
×100
A. 25 1. Class-B transformer VDD × I D 10 × 2
coupled
B. 78.5 2. Class- A RC coupled 5
C. 100 3. Class- A transformer = 2 × 100 ⇒ η = 12.5%
coupled 20
D. 50 4. Class- D switching mode 90. A class – A transformer coupled, transistor
Codes: power amplifier is required to deliver a power
A B C D output of 10 watts. The maximum power rating
(a) 1 2 3 4 of the transistor should not be less than
(b) 2 3 4 1 (a) 5 W (b) 10 W
(c) 2 1 4 3 (c) 20 W (d) 40 W
(d) 3 4 1 2 GPSC Asstt. Prof.11.04.2017
Nagaland PSC (Degree)-2018, Paper-II GATE-1994
Mizoram PSC Jr. Grade- 2015, Paper-II Ans. (c) : Given,
IES-1991 Deliver a power output, PAC = 10 W
Ans. (c) : Po( max )
Class of Amplifier Efficiency ∵ = 2 (For class A amplifier FOM = 2)
PAC( max )
Class-A (for transformer 50%
coupled) Maximum power Rating of the Class-A transformer
Class-A (for RC coupled) 25% coupled amplifier
Class-B 78.5% Po( max ) = 2PAC( max )
Class-AB 50% - 78.5% = 2 × 10
Class-C >90% Po( max ) = 20W
88. An amplifier's power level is changed from
8, watts to 16 watts, equivalent dB gain is 91. Unit of thermal resistance that is used in the
design of heat sinks (for power amplifiers) is
(a) 2 dB (b) 6 dB (a) Ohms (b) ºC
(c) 3 dB (d) 5 dB (c) ºC/Ohms (d) ºC/Watt
TNPSC AE-2013 TSGENCO AE-2015
P  Ans. (d) : Thermal Resistance- Absolute thermal
Ans. (c) : Gain dB = 10log  2  resistance is the temperature difference across a
 P1  structure when a unit of heat energy flows through it in
unit time.
 16 
= 10log   It is the reciprocal of thermal conductance. SI unit of
8 thermal resistance is Kelvin per watt (K/W) or °C/W.
= 10 × 0.3010 It is used in design heat sink.
= 3.010 dB 92. The voltage gain of a common emitter
3dB amplifier is :
(a) directly proportional to collector bias current
Analog Electronics 372 YCT
 (b) inversely proportional to collector bias Ans. (a) : Bandwidth equation of double tuned
current transformer
(c) independent of collector bias current BWdt = k.f r
(d) proportional to square of collector bias k is coupling coefficient
current fr is resonant frequency.
BSNL(JTO)-2002 97. In a common source amplifier, the mid-band
Ans. (a) : The voltage gain of a common emitter voltage gain is 40 dB and the upper cut-off
amplifier is directly proportional to collector bias frequency is 150 kHz. Assuming single pole
current. approximation for the amplifier, the unity gain
frequency fT is
Ic
β= (a) 6 MHz (b) 15 MHz
Ib (c) 150 MHz (d) 1.5 GHz
DRDO-2008
β − Rc
AV = Ans. (b) : Given,
Rb Mid-band voltage gain = 40 dB
93. Class A amplifiers are characterized by 40dB = 20log10 ( A V )
(a) Maximum efficiency and minimum distortion A = 100
V
(b) Minimum efficiency and maximum distortion
For amplifier gain bandwidth product is constant
(c) Maximum efficiency and maximum distortion
(d) Minimum efficiency and minimum distortion So, f T = 100 × 150 × 10
3

Kerala PSC Lecturer (NCA) 04.07.2017 = 15 × 10

6

Nagaland PSC CTSE 2015, Paper-II = 15MHz

Ans. (d) : Class A amplifier has minimum efficiency 98. From a measurement of the rise time of the
and minimum distortion. Class A amplifier is a high output pulse of an amplifier whose input is a
gain amplifier with high linearity. small amplitude square wave, one can estimate
94. An amplifier power level is changed from 8 the following parameter of the amplifier
watts to 16 watts, equivalent dB gains is (a) Gain-bandwidth product
(a) 2 dB (b) 3 dB (b) Slew rate
(c) Upper 3 dB frequency
(c) 6 dB (d) 5 dB
(d) Lower 3 dB frequency
Kerala PSC Lecturer (NCA) 04.07.2017
Nagaland PSC (Degree) 2018, Paper-II
 P2 
Ans. (b) : Gain in dB = 10 log   0.35
 P1  Ans. (c) : t r =
f rdB
 16  ∴ Upper 3 dB frequency can be found.
G = 10 log  
8 99. A power amplifier can safety deliver a load
G = 10 log 2 power of 10 W at an ambient temperature of
G = 10 × 0.3010 25ºC. If the maximum allowable junction
G = 3.01 dB temperature is 125ºC, how much power can be
safely delivered to the load if the ambient
95. The main function of the transformer used in temperature increase in 75ºC?
the output of a power amplifier is (a) 7.5 W (b) 2.5 W
(a) to step up the voltage
(c) 8 W (d) 5 W
(b) to step down the voltage
(c) to match the load impedance with dynamic BSNL (JTO)-2001
output resistance of the transistor Ans. (d) : Given,
(d) to increase voltage gain Delivered a load power = 10W
TSPSC Manager (Engg.) - 2015 T1 = 125, T2 = 25
Ans. (c) : An output transformer improves the 125 − 25
efficiency of the amplifier by matching the impedance K = 10 = 10 º C W
of the load with that of amplifier output impedance.
125 − 75
96. The bandwidth of a double tuned transformer Therefore, P = = 5W
10
coupled amplifier can be adjusted by varying
100. For a class-A power amplifier, supply dc
the
(a) coupling coefficient voltage is ± 12 V, the quiescent collector
current is 72 mA and the load resistance is 100
(b) value of the inductance
Ω. If the output voltage across the load is 12 V
(c) value of the emitter biasing resistance peak-to-peak, the efficiency of the amplifier is
(d) value of resistance (neglect the loss occurring in the biasing
TSPSC Manager (Engg.) - 2015 resistors) :
Analog Electronics 373 YCT
 (a) 10.4% (b) 20.8% Ans. (b) : η = 50% for Class - A Amplifier
(c) 25% (d) 33.3%
DRDO-2009 Po( AC)
η=
Ans. (b) : Given value, PI( DC)
Supply dc voltage - 1 1.25
VCC = 12V =
2 PI(DC)
Quiescent collector current, IC = 72mA PI(DC) = 2.50 Watt
Peak-to-peak output voltage 104. Class-B amplifier has less efficiency compared
Vp− t − p = 12V to
Max output voltage- (a) Class-A
1 12 (b) Class-AB
Vm = Vp − t − p = = 6V (c) Class-C
2 2 (d) Class-A, Class-AB and Class-C
Output current-
Nagaland PSC CTSE- 2015, Paper-II
V 6
Im = m = = 0.06A Ans. (c): Class-B amplifier has less efficiency
R L 100 compared to class-C amplifier
So, efficiency of the amplifier, Class of Amplifier Efficiency
1 Class-A (for transformer 50%
Vm Im
coupled)
%η = 2 × 100
VCC IC Class-A (for RC coupled) 25%
1 Class-B 78.5%
× 6 × 0.06 Class-AB 50% - 78.5%
%η = 2 × 100
12 × 72 × 10−3 Class-C 90%
%η = 20.8% 105. Push-pull amplifier has high power efficiency
because
101. Where does the operating point of class-B
(a) Transistors are placed in CE configuration
power amplifier lie?
(b) There is no quiescent collector current
(a) At the middle of A.C. load line
(c) Each transistor conducts on different input
(b) Approximately at collector cutoff on both the
cycles
D.C. and A.C. load lines
(d) Low forward biasing voltage is required
(c) Inside the collector cutoff on both the D.C.
and A.C. load lines MPPSC Forest Service Exam.-2014
(d) At the middle point D.C. load line Nagaland PSC CTSE- 2015, Paper-II
Nagaland PSC (Degree) 2018, Paper-II Ans. (b) : The efficiency of power push pull amplifier
ISRO Scientist Engg.-2008, IES - 2006 is much higher due to distortion keep within acceptable
limit and there is no quiescent collector current.
Ans. (b) : The operation point of class B amplifier lies
approximately at collector cut-off on both D.C. and 106. At lc=2.5 mA (at room temperature 2950 K)
A.C. load lines. rπ = 1000 Ω . β is given by
102. A Tuned amplifier cannot be used in (a) 2500 (b) 250
(a) Television receiver (b) Radio transmitter (c) 1000 (d) 100
Nagaland PSC CTSE- 2015, Paper-II
(c) Power supply (d) Radio receiver
TNPSC AE- 2019 Ans. (d) : Given : IC = 2.5 mA, rπ = 1000 Ω
Ans. (c) : A tuned amplifier is an electronic amplifier β = gm rπ
which includes band pass filtering components within I C × rπ 2.5 × 10 –3 × 1000  IC 
the amplifier circuitry. They are widely used in a variety β = V = 25 × 10 –3 Q g m = 
VT 
T 
of wireless applications. There are several tuning
schemes in use, staggered tuning where each amplifier β = 100
stage is tuned to a slightly different frequency. So tuned 107. Which of the following statement(s) is/are true?
amplifier cannot be used in power supply. I. An amplifier must be powered and have an
input signal to develop a normal output
103. Single stage transformer coupled class A signal.
amplifier delivering the A.C. power to load of II. An amplifier has a voltage gain of 50. If the
1.25 watts. The D.C. power from the D.C. input signal is 2 mV, the output signal should
supply is be 50 mV.
(a) 1.25 W (b) 2.5 W III. The input signal to an amplifier is 100 μV,
(c) 5 W (d) 0.65 W and its output signal is 50 mV, so its voltage
Nagaland PSC CTSE- 2015, Paper-II gain is 500.
Analog Electronics 374 YCT
 (a) II and III (b) I only 111. Class AB operation is often used in power
(c) I and III (d) I and II amplifiers in order to
NLC GET -24.11.2020 (a) get maximum efficiency
Ans. (c) : Given value, (b) remove even harmonics
Statement -I Amplifiers produces no output till a (c) overcome a cross-over distortion
signal is fed to the input. (True). (d) reduce collector dissipation.
Statement II- A V = 50, Vin = 2mV KVS TGT (WE)- 2017, BEL-2015
then output voltage will be TRB Poly. Lect. -2012
Vo = 50 × 2mV Ans. (c) : Class-A amplifier - No cross over distortion
occurs as they are biased in the centre of the load line.
= 100mV ( false ) Class-B amplifier- Large amount of cross distortion
Statement - III - Vin = 100µV due to biasing at the cut off point.
Class- AB amplifier- Crossover distortion is biasing
Vo = 50mV level is avoid the cut off.
−3
V 50 ×10 112. Which power amplifier conducts from 0° to
then A V = o = −6 180°
Vin 100 ×10
(a) Class-A (b) Class-B
A V = 500 ( True ) (c) Class-AB (d) Class-C
108. The cross-over distortion in class B push-pull AAI-2015
amplifier is eliminated by Ans. (b) :
(a) Operating the amplifier as class C 1. Class- A Amplifier conduct from full cycle (360º)
(b) Operating the amplifier as class AB 2. Class-B Amplifier conduct from 0º to 180º.
(c) Eliminating the output transformer 3. Class-C Amplifier conduct from less than half cycle
(d) Reducing the biasing of the transistors of the input signal.
Nagaland PSC CTSE- 2015, Paper-II 113. Class C amplifier operates
Ans. (d) : A simple way to eliminate crossover (a) Entire cycle of input signal
distortion in a class B amplifier is to add two small (b) Half of the cycle of input signal
voltage to the circuit to bias both the transistor at a point (c) Slightly more than half of the cycle of input
slightly above their cut off. signal
109. The output voltage two stage amplifier as (d) Less than half of the cycle of input signal
shown in figure is : ISRO Scientist- May, 2017
UJVNL AE-2016, TNPSC AE-2013
Ans. (d) : The class C power amplifier is one kind of
amplifier where the transistor conduct for less than 180º
(One-half cycle of the input signal) and its typical value
is 80º to 120º.
114. A particular amplifier circuit used for
(a) 10 V (b) 8.1 V frequency doubling is
(c) 9 V (d) 7.3 V (a) Push-push (b) Push-pull
MPSC HOD Govt. Poly. -2013 (c) Pull-push (d) Pull-pull
V ISRO Scientist- May, 2017
Ans. (a) : 0 = A v1 × A v2 Ans. (a) : Frequency doubler means Amplifier should
Vin
work like a full wave rectifier.
V0 Push-push amplifier allows for a fully active full wave
= 100 × 100
1mV rectifier. Centre tapped full wave and bridge rectifier
−3
V0 = 10 × 10 × 10 3 can work as a frequency doubler.
V0 = 10V 115. A single stage non-inverting amplifier has
R F = 220kΩ and R 1 = 10kΩ. If two such stages
110. One of the advantage of base modulation over
collector modulation of a transistor Class C are cascaded, find the mid frequency gain of
amplifier is the cascade.
(a) The lower modulating power required (a) 27.23 dB (b) 54.47 dB
(b) Higher power output power required (c) -54.47 dB (d) -27.23 dB
(c) Higher power output per transistors UPPCL AE-05.11.2019
(d) Better efficiency RF
Nagaland PSC CTSE (Degree)-2017, Paper-II (b) : A V = 1 + R
1
Ans. (a) : One of the advantages of base modulation
over collector modulation of a transistor class C A = 1 + 220
V = 23
amplifier is the lower modulating power required. 10
Analog Electronics 375 YCT
∴ A V 1 = A V2 = 20log 23 = 27.23 dB. Feedback factor - β = 0.008
Barkhausen criterion for oscillatory system -
A V = A V1 + A V2 = 27.23 + 27.23
Aβ = 1 ................ (i)
A V = 54.46 dB Equivalent gain A = A × A × A
116. The amplifier which retains the shape of the
A = (A)
3

input signal at the output are called−

(a) Distortion amplifier (b) Pulse transformer  A0 
3

(c) Non-linear amplifier (d) Linear amplifier A =  

RRB JE-01.09.2019, 3:00 PM – 5:00 PM  2 
Ans. (d) : The amplifier on which the given input signal A3
A = 0 ................ (ii)
does not change in the shape of the signal received at its 8
output. From equation (i) & (ii)
It is called linear amplifier. 1
In linear amplifier the signal at the output is in the same A =
β
shape as the input. When the input signal delivered to a
device is low, an amplifier is placed or used before the A 30 1
device to amplify. There are mainly four types of =
8 0.008
amplifiers.
8000
(a) Class A amplifier A 30 =
(b) Class B amplifier 8
(c) Class C amplifier A 30 = 1000
(d) Class D amplifier A 0 = 10
117. A circuit designed to increase the level of its
input signal is called: 2. For negative feedback amplifiers, which one of
(a) an amplifier (b) a modulator the following statement is true?
(c) an oscillator (d) a receiver (a) Its output impedance and distortion increases
RRB SSE 03.09.2015 Shift-II (b) Its input impedance and distortion increases
Ans. (a) : A circuit designed to increase the level of its (c) Its gain and distortion decreases
input signal is called amplifier. (d) Its gain and B.W. decreases
The only use of amplifier in a circuit is to provide UPPSC ITI Principal/Asstt. Director-09.01.2022
strength to signal. GPSC Asstt. Prof.-11.04.2017
Ans. (c) : Negative feedback amplifier
(vi) Feedback amplifiers Af =
A
1 + Aβ
1. Three amplifiers of gain Reduces the distortion
A  Reduces noise
A =  0  ∠ - 60º Increase bandwidth
 2 
Reduce the gain
are connected in tandem. The feedback loop is
closed through a positive gain of 0.008 : Increase stability
3. An amplifier has an open loop gain of 200, an
input impedance of 2KΩ and an output
impedance of 200Ω. If a feedback network
with a feedback factor 0.99 is connected in a
voltage series feedback mode, then new input
impedance and output impedance are
(a) 398 kΩ and 1 kΩ (b) 398 kΩ and 1Ω
(c) 398 Ω and 1kΩ (d) 398Ω and 1 Ω
The magnitude of A0 for the system to be
BPSC Asst. Prof. - 12.04.2022
oscillatory will be
(a) 0.2 (b) 0.1 Ans. (b) : Given,
(c) 5.0 (d) 10.0 A = 200 , β = 0.99 , R i = 2kΩ , R 0 = 200Ω
UPPSC ITI Principal/Asstt. Director- 09.01.2022 So, 1 + Aβ = 1 + 200 × 0.99
IES – 2019, 2005 = 1 + 198
Ans. (d) : Given, = 199
 A0  In voltage series feedback
A=  ∠ − 60º R if = R i (1 + Aβ )
 2 

Analog Electronics 376 YCT

 R if = 2kΩ (199 ) GATE-2009, 2005, 2004, 2002, 1998, 1995
BSNL (JTO)-2002, 2001
= 398kΩ
Ans. (d) :
R0 Feedback Input Output Gain Input Output
R of = Resistance
1 + Aβ Resistance
Voltage Voltage Voltage AV Increase Decrease
200
R of = series
199 Current Voltage Current GM Increase Increase
R of = 1.005 series
R of 1Ω Voltage Current Voltage RM Decrease Decrease
shunt
4. With reference to the negative feedback voltage Current Current Current AI Decrease Increase
- series configuration, which of the following Shunt
statements is/are correct? 7. Which of the following describe the correct
1. Bandwidth increases. properties of an emitter follower circuit ?
2. Non-linear distortion decreases. 1. It is a voltage series feedback circuit.
Select correct answer. 2. It is a current series feedback circuit.
(a) Only 1 (b) Only 2 3. Its voltage gain is less than unity.
(c) Both 1 and 2 (d) Neither 1 nor 2 4. Its output impedance is very low.
UPPSC ITI Principal/Asstt. Director-09.01.2022
Select the correct answer from the codes given
Ans. (c) : Negative feedback voltage series below:
configuration voltage series configuration (a) 1, 3 and 4 (b) 2, 3 and 4
(1) Bandwidth increases. (c) 2 and 3 only (d) 2 and 4 only
(2) Non - linear distortion decreases. Nagaland PSC-2018 Diploma Paper-II
5. Voltage gain with feedback Avf = . KVS TGT (WE)- 2017
(a) Vo – Vi (b) Vs × Vo Nagaland PSC (CTSE) Diploma-2017 Paper-II
V Nagaland PSC (CTSE) Diploma-2015 Paper-II
(c) Vi + Vo (d) o IES - 2009
Vs
Ans. (a) : Common collector circuit is also known as
UPRVUNL AE -19.07.2021, Shift-II emitter follower. Emitter follower's voltage gain is
Xo Vo slightly less than unity. Its current gain is high. Emitter
Ans. (d) : A vf = = follower uses voltage-series feedback. Its input
Xs Vs resistance is high and output resistance is low. This
6. Match List-I (Type of Feedback) with List-II makes it an ideal circuit for impedance matching.
(Effect on Rin and Rout) and select the correct 8. Negative feedback amplifier is a –––––––
answer using the code given below the lists (a) Degenerative feedback
List-I List-II (b) Regenerative feedback
(A) Voltage series 1. Rin increase and (c) Both
Rout decreases (d) None
(B) Voltage Shunt 2. Rin and Rout SAIL- 2014
decrease
Ans. (a) : Negative feedback also referred as
(C) Current Series 3. Rin and Rout
degenerative feedback is a widely used type of feedback
increase in the control system. Here the signal at the output
(D) Current shunt 4. Rin decreases and which is out of phase with respect to the input is fed
Rout increases. back to the input.
Codes: 9. The amplifier A shown in the figure has open
A B C D loop gain of 100, input impedance Zin, of 1 kΩ
(a) 1 4 3 2 and output impedance Z0 of 100Ω. If a negative
(b) 3 2 1 4 feedback factor β = 0.99 is used, the new values
(c) 3 4 1 2 of Z1 and Z0 are respectively:
(d) 1 2 3 4
Nagaland PSC CTSE (Degree)2018, Paper-II
KVS TGT (WE)-20017
Nagaland PSC CTSE (Degree)2017, Paper-II
GPSC Asstt. Prof.-11.04.2017
Punjab PSC Poly. Lect.20.08.2017
Mizoram PSC IOLM- 2010, Paper-II
Nagaland PSC CTSE -2015, Paper-II
IES – 2009, 2008, 2007, 2003 1992
Analog Electronics 377 YCT
 (a) 10 Ω and 1 Ω (b) 10 Ω and 10 Ω
104
(c) 100 kΩ and 1 Ω (d) 100 kΩ and 10 Ω Av =
KVS TGT (WE)-2018, BPSC Poly. Lect.-2014  2 ×106 
1+  3 
IES-2013, GATE-1999  100 × 10 
Ans. (c) : Given value – 104
Input impedance Zin = 1kΩ Av =
1 + 20
Output impedance Z0 = 100Ω A v = 2182.179
Gain A = 100
log A v = 3.33
β = 0.99
20log A v 66.66dB
Q Input resistance with feedback
12. If an amplifier with gain of -1000 and feedback
Zif = Zin (1 + Aβ ) factor of β = -0.1 had a gain change of 20% due
Zif = 1 × 103 (1 + 100 × 0.99 ) to temperature, the change in gain of the
feedback amplifier would be
= 103 × (1 + 99 ) (a) 10% (b) 5%
= 100 × 103 (c) 0.2% (d) 0.01%
= 100kΩ TNPSC AE- 2019
Q Out put resistance with feedback IES - 1997
Kerala PSC Lecturer (NCA) 04.07.2017
Z0
Zof = Ans. (c) : Given,
1 + Aβ Open loop gain = –1000
Zof =
100
=
100 100
= Feedback factor, β = – 0.1
1 + 100 × 0.99 1 + 99 100 Gain change of 20%
Zof = 1Ω ∂A
= 20% = 0.20
10. The voltage gain of an amplifier is 100. A A
negative feedback is applied with β = 0.03. The Gain change with feedback
overall gain of the amplifier is: ∂A f ∂A . 1
(a) 70 (b) 25 =
Af A 1 + Aβ
(c) 99.97 (d) 3
Nagaland PSC CTSE (Diploma)-2018, Paper-I 1
= 0.20 ×
TSPSC Manager (Engg.) - 2015 1 + ( −1000 )( −0.10 )
IES - 2013
∂A f 0.20
Ans. (b) : Given, =
Gain, A = 100 Af 101
Feedback, β = 0.03 ∂A f 0.20
A %= × 100%
Overall gain, A f = A f 101
1 + Aβ ∂A f
100 % = 0.198%
= Af
1 + 100 × 0.03
∂A f
A f = 25 % ≃ 0.2%
Af
11. The voltage gain of an amplifier decreases at 20
dB/decade above 100 kHz. If the mid band 13. If each stage has a gain of 10 dB, and noise
frequency gain is 80 dB. What is the value of figure of 10 dB, then the overall noise figure of
the voltage gain at 2 MHz? a two-stage cascade amplifier will be
(a) 60 dB (b) 52 dB (a) 10 (b) 1.09
(c) 54 dB (d) 64 dB (c) 1.0 (d) 10.9
TNPSC AE-2014 ISRO Scientist Engg.-2008
Ans. (d) : 20log A v = 80dB Ans. (d) : G1 = 10dB
f1 = f2 =10 dB
80dB
log A v = f −1
20 The overall noise figure (f) = f1 + 2
A = 10 4 G1
v
10 − 1
Av ( mid ) = 10 +
Av = 10
2
 f  = 10 + 0.9
1+  2 
f  = 10.9

Analog Electronics 378 YCT

14. A 10dB attenuator is put at the input of a low
noise amplifier having 3dB noise figure. Now
the noise figure of the cascaded amplifier will
be
(a) 3dB (b) 12dB
(c) 7dB (d) None of the above
ISRO Scientist Engg.-2013
Q 40kΩ and 60 kΩ act as voltage dividers for V0 ,
Ans. (c) :
V × 60 60 6
( SNR )i / p Vi = 0 =
60 + 40 100
V0 = V0
Noise figure = 10
( SNR )o / p 3
Vi = V0
( N.F.)dB = (SNR )i / p  dB − ( SNR )o / p  dB 5
Q Ideal op-amp A v = ∞
Given value, ( SNR )i / p = 10dB V V
Vid = 0 = 0 = 0 = V + − V −
(SNR ) = 3dB
o/p
A v V∞
So, noise figure of the cascaded amplifier, V+ − V− = 0
( N.F.)dB = 10 − 3 = 7dB V + = V − (virtual ground)
Q Vz = Vi − VBE
15. Negative feedback in amplifiers
(a) improves the signal to noise ratio at the I/P Where VBE = 0.7V, Vz = 5.3V
(b) improves the signal to noise ratio at the O/P 3
5.3 = V0 − 0.7
(c) Doesn't affect the Signal to Noise ratio at the 5
O/P 3
(d) All of these V0 = 6
5
ISRO Scientist Engg.-2016 V = 10V
0
GATE-1993
17. The gain of an amplifier without feedback is
Ans.(b): Negative feedback-
100 db. If a negative feedback of 3 db is
A applied, the gain of the amplifier will
Af =
1 + Aβ become……..
(a) 5 db (b) 300 db
Reduces the distortion
(c) 103 db (d) 97 db
Reduces noise Nagaland PSC (CTSE) Diploma-2017, Paper II
Increase bandwidth
Ans. (d) : AV = 100 dB
Reduce the gain
β = 3dB
Increase stability
Av= [20 log AV] –[ 20 log β ]
Negative feedback in amplifiers improves the Signal to
Noise ratio at the O/P = 100 -3
16. In the given circuit, Vbe = 0.7 V, Vz = 5.3V, β = A v = 97dB
100. Vo is 18. A feedback circuit usually employs….network
(a) Resistive (b) Capacitive
(c) Inductive (d) None of the above
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (a) : A feedback circuit should not vary with time.
Hence resistor is used as feedback element because it
always constant with respect to time and frequency.
19. The gain of an amplifier with feedback is
known as……….gain
(a) 5V (b) 10V
(a) Resonant (b) Open loop
(c) 15V (d) 20V
(c) Closed loop (d) None of the above
ISRO Scientist Engg. -2020
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (b) : Given value,
Ans. (c) : The gain of an amplifier is known as open
Vbe = 0.7V loop gain but when feedback is connected, this loop
Vz = 5.3, β = 100, find V0 = ? gain is called close loop gain.

Analog Electronics 379 YCT

20. Current gain with feedback Aif = . If Vf
(c) β = (d) β =
(a) Io + Ii (b) Is – Io Vo Io
I TNPSC AE – 2018
(c) Ii × Io (d) o
Is Ans. (a) : Feedback factor ( β ) - The feedback factor
UPRVUNL AE -19.07.2021, Shift-II for a voltage shunt feedback amplifier is the ratio of
XO Vf
Ans. (d) : Gain of feedback Amplifier = feedback current and output signal voltage β =
Xs V0
I0 25. In a voltage-voltage feedback as shown below,
∴ Current gain with feedback = which one of the following statements is TRUE
Is
if the gain k is increased?
21. For a voltage series feedback topology, if β =
0.01, A = 50 and R1 = 2.87 kΩ, then the Rif is
.
(a) 4.30 kΩ (b) 3.43 kΩ
(c) 1.78 kΩ (d) 1.91 kΩ
UPRVUNL AE -19.07.2021, Shift-II
Ans. (a) : Given, (a) The input impedance increases and output
β = 0.01 impedance decreases
A = 50 (b) The input impedance increases and output
impedance also increases
R1 = 2.87kΩ
(c) The input impedance decreases and output
In voltage series F.B, Rif = Ri × D impedance also decreases
D = 1+βA (d) The input impedance decreases and output
= 1+0.01(50) impedance increases
3 GATE-2013
D= Nagaland PSC (CTSE) Diploma -2017 paper-II
2
Ans. (a) :
Rif = Ri×D
3
= 2.87 ×
2
R if = 4.305kΩ
22. The positive feedback reduces
(a) Instability (b) Distortion
(c) Noise (d) Bandwidth A voltage-voltage feedback in the above figure is also
TNPSC AE – 2018 known as voltage-series feedback amplifier. In voltage-
UPRVUNL AE– 11.06.2014 series feedback amplifier, the input impedance increases
and output impedance decreases.
Ans. (d) : A positive feedback is used to increase gain
and phase margin. Zi = Z'i (1 + A 0 k )
Hence the band width will reduce. A positive feedback Z'0
system is used as an oscillator. Z0 =
(1 + A 0 k )
23. Which one of the following is wide band
amplifier? 26. Voltage amplifier uses feedback
(a) RF amplifier (b) IF amplifier topology.
(c) Video amplifier (d) AF amplifier (a) current series (b) voltage shunt
IES-2004 (c) voltage series (d) current shunt
UPRVUNL AE -19.07.2021, Shift-II
Ans. (c) : Video amplifier is wide band amplifier.
Video amplifier is used in television, radar, Ans. (c) :
oscillographs and other equipment to amplify video
signal. Video amplifier has large bandwidth which is
required for video signal.
24. The feedback factor β for a voltage shunt
feedback amplifier is given by
V I
(a) β = f (b) β = f
Vo Io

Analog Electronics 380 YCT

 Type of Negative feedback (a) Decreases (b) Becomes unity
Charact (c) Remains constant (d) Increases
eristic Nagaland PSC (Degree)-2018, Paper-II
Voltage Voltage Current Current Mizoram PSC IOLM -2018, Paper II
series shunt series shunt
ISRO Scientist Engg.-2014
Voltage Decrease Decrease Decrease Decrease
gain Ans. (c) : Cascading increase lower cut-off and
Bandwidth Increase Increase Increase Increase decrease higher cut-off frequency, decrease bandwidth.
In cascading connection, voltage gain increases which
Ri Increase Decrease Increase Decrease
in turn reduces the bandwidth to maintain a constant
R0 Decrease Decrease Increase Increase gain-bandwidth product.
Harmonic Decrease Decrease Decrease Decrease 31. If gain of positive feedback amplifier is 18 and
distortion
feedback factor is 0.5, the gain of the amplifier
Noise Decrease Decrease Decrease Decrease without feedback will be -
27. The open loop transfer function of an amplifier (a) 1.8 (b) 2
with resistive negative feedback has two poles (c) 3.6 (d) 5
in the left half s-plane. Then the amplifier. UPPCL AE-16.11.2013
(a) will always be unstable at high frequencies
Ans. (a) : Given,
(b) will be stable at all frequencies
β = 0.5
(c) may become unstable depending upon
feedback factor A f = 18
(d) will oscillate at low frequencies A
Mizoram PSC IOLM-2010, Paper-II A f = 1 − Aβ
IES-2013
A
Ans. (b) : The stability of a linear closed loop system 18 =
can be determined from the locations of closed-loop 1 − 0.5A
poles in the s-plane. 18 − 9A = A
If all the roots of the characteristics equation lie on the A = 18 A = 1.8
left half of the ‘s’ plane, i.e., if all the roots have 10
negative real parts, then the system is said to be a stable 32. Which of the following can be magnified by
system. magnetic amplifiers
28. An amplifier without feedback has a voltage (a) Voltage (b) Current
gain 50 and input resistance of 1 kΩ. The input (c) Power (d) None of the above
resistance of the current-shunt negative UJVNL AE-2016
feedback amplifier using the above amplifier
Ans. (c) : A magnetic amplifier can amplify the power.
with a feedback factor of 0.2 is Magnetic amplifiers are used to amplify electrical
(a) 1/11 kΩ (b) 1/5 kΩ signals, it can either be voltage or current amplifier, in
(c) 5 kΩ (d) 11 kΩ both cases actually power is increasing P = V ⋅ I
Punjab PSC Poly. Lect.-20.08.2017 33. The noise in a negative feedback amplifier
GPSC Asstt. Prof. 11.04.2017 (a) Increases
Ans. (a) : Input Resistance with feedback for current (b) Decreases
shunt (c) First increases and then decreases
' Ri (d) First decreases and then increases
Ri =
1 + βA TNPSC AE-2014
R i = 1kΩ β = 50 A = 0.2 Ans. (b) : The numerous advantage of negative
feedback–
1 1
R 'i = = (1) higher fidelity i.e. more linear operation.
1 + 10 11 (2) highly stabilized gain.
29. Required bandwidth of wideband amplifier to (3) increased bandwidth i.e. improved frequency
reproduce a pulse faithfully, depends upon response.
.............. of the pulse (4) Reduced noise.
(a) width (b) rise time (5) Less harmonic distortion.
(c) fall time (d) frequency 34. Three identical single tuned amplifiers are
Mizoram PSC AE/SDO-2012 Paper-III connected in cascade. The 3 dB bandwidth of
Ans. (b) : Required bandwidth of wideband amplifier to each amplifier is 100 kHz. The overall 3 dB
reproduce a pulse faithfully, depends upon Rise time of bandwidth will be approximately.
the pulse. (a) 300 kHz (b) 100 kHz
30. By increasing the number of identical stages in (c) 50 kHz (d) 33 kHz
an amplifier, the gain bandwidth product TNPSC AE-2013
Analog Electronics 381 YCT
Ans. (c) : n = 3, fH = 100 kHz 39. In high frequency region, an amplifier
behavior like a
'
H f = fH 2 − 1
13
(a) Band pass filter
f H = 100 2 − 1
' 1/ 3
= 100 1.25 − 1 (b) Low pass filter
(c) High pass filter
f H' = 100 × 0.25 (d) Any of the above
f H' = 50kHz Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (b) : In high frequency region an amplifier behave
35. An amplifier has gain of 20 without feedback. like low-pass filter.
If 10% of the output voltage is feedback by
means of a resistance negative feedback circuit, A
the overall gain would be 40. For feedback amplifier with gain
1− T
(a) 16.55 (b) 19.8 feedback reduces the internally generated noise
(c) 10.85 (d) 6.67 by a factor
TNPSC AE-2013 (a) T (b) (1 – T)
Ans. (d) : New gain with negative feedback
1 1
Av 20 (c) (d)
Av =
'
=
1 + A vβf 1 + 20 × 1
T (1 − T )
10 Nagaland PSC CTSE (Degree)-2016, Paper-II
20 Nagaland PSC CTSE- 2015, Paper-II
A 'v = Ans. (b) : Noise reduced by factor of (1-T) in case of
3
Negative feedback amplifier.
A 'v = 6.67 41. One of the following types of distortions is not
36. One of effect of negative feedback in amplifier objectionable in audio amplifiers
is to (a) Harmonic distortion
(a) Decrease the harmonic distortion (b) Intermediations distortion
(b) Increase the harmonic distortion (c) Frequency distortion
(c) Decrease the bandwidth (d) Phase distortion
(d) Increase the noise Nagaland PSC CTSE (Diploma)-2018, Paper-I
MPPSC Forest Service Exam.-2014 Ans. (d) : Phase distortion has least effect on audio
GATE-1993 amplifiers. It is also known as delay distortion.
Ans. (a) : Negative feedback reduces gain of the 42. Negative feedback in an amplifier results in
amplifier. It also reduces the distortion, noise and (a) More gain, more bandwidth
instability. But increase bandwidth and improve input (b) More gain, less bandwidth
impedance.
(c) Less gain, more bandwidth
37. An amplifier without feedback has a gain of (d) Less gain, less bandwidth
1000. The gain with negative feedback of 0.009
Mizoram PSC Jr. Grade-2018, Paper-II
will be
(a) 125 (b) 10 Nagaland PSC CTSE (Diploma)-2018, Paper-I, II
(c) 900 (d) 100 GATE-1999
MPPSC Forest Service Exam.-2014 Ans. (c) : In negative feedback, the feedback energy is
out of phase with input signal. Negative feedback
Ans. (d) : A = 1000 β = 0.009 reduce gain of the amplifier. It also reduce distortion,
A 1000 noise. This feedback increase bandwidth and improve
AF = ⇒ AF =
1 + Aβ 1 + 0.009 × 1000 input impedances and Output impedances decreases.
1000 43. In a push pull circuit
AF = (a) each transistor conducts for 180º
10
A F = 100 (b) each transistor conducts for more than 180º
but less than 360º
38. The unity gain bandwidth of an inverting (c) each transistor conducts for less than 180º
amplifier is 10 MHz What would be the (d) the period of conduction of each transistor
bandwidth if the gain is increased to 10V/V? depends on circuit configuration
(a) 100 MHz (b) 1 MHz Mizoram PSC Jr. Grade-2015, Paper-II
(c) 10 MHz (d) 1 kHz
Ans. (a) : In push pull circuit each transistor conducts
RPSC LECTURER-10.01.2016 for 180º. So that complete conduction for 360º occurs.
Ans. (b) : Gain × bandwidth = Constant Hence minimum distortion and maximum efficiency.
So, G1×(BW)1 = G2×(BW)2 44. What is the percentage reduction in gain of an
1×10×106 = 10×B2 amplifier due to introduction of 20 dB of
B2 = 1MHz negative feedback?
Analog Electronics 382 YCT
 (a) 100% (b) 50% Ad 133.3
(c) 90% (d) 70% Af = =
1 + A dβ 1 + 133.3 × 0.03
Mizoram PSC Jr. Grade -2018, Paper-II
Af = 26.7
Ans. (c) : Given,
gain = 20dB 47. A negative feedback of β = 2.5 × 10-3 is applied
20 log Af = 20 to an amplifier of open-loop gain 1090. What is
the change in overall gain of the feedback
A f = 10 amplifier, if the gain of the internal amplifier is
So it will be reduced 90% reduced by 20% ?
(a) 295.7 (b) 286.7
45. The circuit shown in the figure below is an (c) 275.7 (d) 266.7
example of feedback of which of the following
types? IES - 2015
Ans. (c) : Given,
Open loop gain, A= 1090
Feedback factor, β = 2.5 ×10 −3 = 0.0025
A
A f1 =
1 + Aβ
1090
=
(a) Voltage series (b) Voltage shunt 1 + 1090 × 0.0025
(c) Current series (d) Current shunt A f1 = 292.617
BPSC Polytechnic Lecturer-2014 After 20% reduction
Ans. (b) : 80
A 2 = 1090 ×
100
= 1090 × 0.8
A2 = 872
A2
A f2 =
1 + A 2β
872
=
The circuit shown in the figure below is an example of 1 + 872 × 0.0025
feedback Voltage shunt. A f2 = 274.2
46. An amplifier, without feedback, has a gain A.
The distortion at full output is 10%. The A f2 ≃ 275.7
distortion is reduced to 2% with negative
48. An amplifier with mid band gain A = 500 has
feedback (feedback factor β = 0.03). The values
negative feedback β = 1/100. If upper cut-off
of A and A' (i.e. the gain with feedback) are,
without feedback were at 60 kHz, then with
respectively, nearly feedback it would become
(a) 133.3 and 18.5 (b) 133.3 and 26.7 (a) 10 kHz (b) 360 kHz
(c) 201.3 and 26.7 (d) 201.3 and 18.5 (c) 12 kHz (d) 300 kHz
IES - 2018 KVS TGT (WE)- 2014, IES - 2014
KVS TGT (WE)- 2016
Ans. (b) : Given,
Ans. (b) : Given, Mid band gain |A| = 500
distortion of basic amplifier Ad = 10% 1
Feedback Adf = 2% Feedback gain |β| =
100
β = 0.03 Without feedback upper cut-off frequency f = 60 kHz
u

∵ A df =
Ad Upper cut-off frequency after feedback = f u (1+ | Aβ |)
1 + A dβ
 500 
= 60 ×103 1 + 
10%  100 
2% =
1 + A d × 0.03 = 60 × 10 × 6
3

1 + 0.03A d = 5 = 360 kHz

49. The second harmonic component in the output
4
⇒ Ad = of a transistor amplifier, without feedback is
0.03 B2. The second harmonic component with
Ad = 133.3 negative feedback B'2 is equal to (where A =
∴ Negative feedback, gain reduced by ( 1+ Aβ), Amplifier gain and β = feedback factor).

Analog Electronics 383 YCT

 B2 Ans. (b) :
(a) (b) B2 (1 + Aβ)
1 + Aβ
B2 B2
(c) (d)
β Aβ
Sikkim PSC SI (Mains)-2018
IES - 2012
Ans. (a) : Given,
The second harmonic component in the output without
feedback, = B'2
Harmonic with feedback = B2
feedback factor = β
B2 RF is the element responsible for feedback and it is
B'2 = directly connected to the output node, so voltage
1 ± Aβ
sampling is done and it is also directly connected to the
The value of second harmonic component in output of input node, so shunt mixing is there. Hence, the
transistor with feedback is feedback is voltage shunt.
52. The given circuit represents the amplifier type
B2
B'2 = (for negative feedback) as :
1 + Aβ
50. In a transconductance amplifier, the device
output
(a) voltage depends upon the input voltage.
(b) voltage depends upon the input current.
(c) current depends upon the input voltage.
(d) current depends upon the input current. (a)
voltage-series feedback
IES - 2012 (b)
voltage-shunt feedback
(c)
current-series feedback
Ans. (c) : In a transconductance amplifier, the device (d)
current-shunt feedback
output current depends upon the input voltage. APPSC Poly. Lect. 15.03.2020
Iout Ans. (b) : From output, we take V0 as feedback which it
Transconductance = A V
Vin makes shunt at input. Hence it is voltage shunt
feedback.
51. The amplifier circuit shown in the figure is an
53. 1 dB corresponds to ________ change in power
example of level.
(a) 35% (b) 26%
(c) 50% (d) 14%
RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (b) : Given that dB = 1
P
dB = 10log 0
P1
P0
1 = 10log10
P1
1 P
= log10 0
10 P1
Antilog–
(a) voltage series feedback
P0
(b) voltage shunt feedback Anti log [ 0.1] =
P1
(c) current series feedback
P0
(d) current shunt feedback 1.259 =
P1
IES - 2011
Analog Electronics 384 YCT
 P0 = 1.1 MHz
1.26 = Lower cut-off frequency with feedback-
P1
fℓ
P0= 1.26P1 fL =
Change in power level, (1 + Aβ )
∆P P0 − P1 1.26P1 − P1 1×103
% = × 100 = × 100 =
P P0 P1 1 + −100 ( 0.1) 
(1.26 − 1) P1 1000
= × 100 = 26% = Hz
P1 11
54. A feedback amplifier has an open loop gain of - Feedback = 20 logβ
100. If 4% of the output is fed back in a = 20 log(0.1)
degenerative loop, what is the closed loop gain = –20
of the amplifier ?
(a) – 33.3 (b) – 25 56. An amplifier has an open loop gain of 1000±10.
(c) – 20 (d) + 20 Negative feedback is provided such that the
IES - 2008 gain variation remains within 0.1%. What is
Ans. (c) : Given, the amount of feedback βF ?
Open loop gain, A = –100 (a) 1/10 (b) 1/9
Feedback factor, β = –4% = –0.04 (c) 9/100 (d) 9/1000
A IES - 2006
Closed loop gain, A f = Ans. (d) : Given, A = 1000
1 + Aβ
∂A 10
−100 =
= A 1000
1 + ( −100 )( −0.04 )
∂A F
−100 = 0.1%
Af = AF
5
∂A F 1 ∂A
A f = −20 = .
A F 1 + Aβf A
55. An amplifier has gain A = 100∠180º, upper
0.1 1 10
cut-off frequency of 100 kHz and lower cut off = ×
frequency of 1 kHz. A negative feedback of 100 1 + 1000βf 1000
β=0.1 is added. Which one of the following is 1 1 1
not correct ? = ×
(a) Gain becomes 100/11 1000 1 + 1000 β f 100
(b) Lower cut off frequency becomes (1000/11) 1 + 1000βf = 10
kHz
(c) Upper cut off frequency becomes 1.1 MHz 9
βf =
(d) dB of feedback is 20log10 11 1000
IES - 2008 57. A negative feedback is applied to an amplifier
Ans. (d) : Given, with the feedback voltage proportional to the
Gain, A = –100 output current. This feedback increase the
fu = 100 kHz, f L = 1 kHz (a) input impedance of the amplifier
Feedback factor (β) = 0.1 (b) output impedance of the amplifier
A (c) distortion in the amplifier
Closed loop gain, (A f ) = (d) gain of the amplifier
1 + Aβ
DRDO-2008
−100
= Ans. (a) : In voltage series feedback the input of the
1 + ( −100 )( 0.1) system is series connected with the feedback loop
−100 therefore the input impedance will be increased.
Af = 58. The voltage gain of an amplifier without
11
feedback and with negative feedback
Upper cut-off frequency with feedback-
respectively are 100 and 20. The percentage of
f U' = f u (1 + Aβ ) negative feedback (β) would be
= 100 ×10 1 + ( −100 ) × ( 0.1) 
3 (a) 4% (b) 5%
(c) 20% (d) 80%
= 100 × 103 × 11 IES - 2002
Analog Electronics 385 YCT
Ans. (a) : Given, gm
g mf =
Gain without feedback, A =100 D
Gain with feedback, Af = 20 g m = −50mA / V
A For degenerative feedback
Af =
1 + Aβ D = 1 + βg m

20 =
100 50 = 1 + β× ( −50 ×10−3 )
1 + 100β
49
1 + 100β = 5 β=
−50 × 10−3
100β = 4
β = −0.98
4
β=
100 Feedback voltage R E IC
β= =
4 output voltage VO
β% = ×100 = 4%
100 −0.98
RE = = 0.98kΩ
β = 4% −1mA / V
61. The given circuit has a feedback factor of
59. The feedback amplifier shown in the figure
below :

(a) is stable for all values of R and C

(b) is stable only for R1R2 = R3 (a) -RC/RS (b) -RE/RC
(c) is stable only for R1C = R1R3 (c) -RE/RS (d) -RC/RE
(d) is stable is R1/R2 = C / R3 IES - 1999
IES - 2002 Ans. (b) :
Ans. (a) :

In given diagram voltage gain is negative. Negative

feedback tends to maintain a constant value of amplifier Given,
voltage gain against variations in transistor parameter. Output Collector Resistance, = RC
So stability increases as gain reduces hence it is stable Emitter resistance or feedback resistance = RE
for all values of R and C. Current series feedback configuration has given in
60. If a common emitter amplifier with an emitter above circuit -
resistance Re has an overall trans-conductance Output voltage, V0 = R C IC
gain of - 1 mA/V, a voltage gain of -4 and
desensitivity of 50, then the value of the emitter Feedback voltage, Vf = R E IC
resistance Re would be : Vf
Then, Feedback factor, β =
(a) 50Ω (b) 0.98kΩ V0
(c) 50kΩ (d) 0.98Ω
R E IC
IES - 2000 =
−R C IC
Ans. (b) : Given, D = 50
Basic amplifier is trans-conductance amplifier −R E
β=
A = g mf = −1mA / V RC

Analog Electronics 386 YCT

62. It is desired to reduce total harmonic distortion B. CE = 0, 2. Current series negative
of an amplifier from 8% to 2% by use of 5% R f1 = ∞ , feedback
feedback. What is the gain of the amplifier with
original distortion and with reduced R f2 = ∞ and
distortion? output is taken
(a) 60, 15 (b) 15, 90 from collector
(c) 6, 1.5 (d) 1.5, 6 point.
IES - 1995 C. R f2 = ∞ and 3. Voltage shunt negative
Ans. (a) : Given, feedback
output is taken
8 from collector
Initial distortion, D1 = 8% =
100 point.
2 D. CE = 0, 4. Current shunt positive
Final distortion, D2 = 2% = R f1 = ∞ and feedback
100
Feedback factor, β = 5% = 0.05 output is taken
D1 from collector
D2 = point.
1 + Aβ
Codes:
2 8 100
= A B C D
100 1 + A × 0.05 (a) 1 3 4 2
1 1 (b) 2 3 4 1
=
4 1 + 0.05A (c) 3 2 1 4
1 + 0.05A = 4 (d) 4 3 2 1
0.05A = 3 IES -1993
Ans. (b) : Given,
A = 60
Gain with feedback,
A
Closed loop gain, A f =
1 + Aβ
60
Af =
1 + 60 × ( 0.05)
60
Af =
3 +1
A f = 15
63. The given feedback amplifier circuit is List-I List-II
modified according to List-I and the possible 1. RC = 0, CE = 0, Voltage series negative
feedback is as per List-II. Match the two lists
and select the correct answer using the codes R f1 = ∞ , R f2 = ∞ feedback
given below the lists : and output is
taken from
emitter point.
2. CE = 0, R f1 = ∞ , Current series negative
feedback
R f2 = ∞ and
output is taken
from collector
point.
3. R f2 = ∞ and Voltage shunt negative
feedback
List-I List-II output is taken
A. 1. Voltage series negative from collector
RC = 0, CE = 0,
point.
R f1 = ∞ , feedback
4. CE = 0, Current shunt positive
R f2 = ∞ and R f1 = ∞ and feedback
output is taken output is taken
from emitter from collector
point. point.
Analog Electronics 387 YCT
64. In the circuit shown in the given figure, RF Ans. (a, c) : Given,
provides First gain = A = 1
Other gain = 20
We know that
Gain × Bandwidth = Constant
G × B.W. = Constant
Gain, (A) = 1
G × B.W1 = Constant
1 × B.W1 = Constant _________ (1)
Gain, A = 20
20 × B.W2 = Constant ________ (2)
eq.n (1) = eq.n (2)
1 × B.W1 = 20 × B.W2
(a) Current series feedback B.W1
(b) Current shunt feedback B.W2 =
20
(c) Voltage series feedback
(d) Voltage shunt feedback As compared to the unity gain amplifier, the amplifier
IES - 1991 with gain twenty has less bandwidth and less negative
feedback.
Ans. (d) :
67. Consider the following:
I. Oscillator
II. Emitter follower
III. Cascaded amplifier
IV. Power amplifer
Which of the following use feedback
amplifiers?
(a) I and II (b) I and III
(c) II and IV (d) III and IV
Rf is the element responsible for feedback and it is
TRB Poly. Lect. -2012
directly connected to the output node, so voltage
sampling is done and it is also directly connected to the Ans. (a) : Oscillator and emitter follower circuit are
input node, so shunt mixing is there. Hence, the positive and negative feedback amplifiers.
feedback is voltage shunt. 68. Which type of negative feedback is used to
65. A two stage amplifier with negative feedback improve performance of current amplifier?
(a) Becomes unstable at very high and very low (a) Current shunt feedback
frequencies if A is very large (b) Voltage shunt feedback
(b) Can become unstable for larger values of β (c) Current series feedback
(c) Becomes unstable when the pole frequencies (d) Voltage series feedback
become complex MPSC HOD Govt. Poly. -2013
(d) Is always stable Ans. (a) : In current-shunt feedback, as the feedback
Nagaland PSC CTSE (Degree)-2016, Paper-II circuit is connected in series with the output, the output
Ans. (d) : Negative feedback amplifier subtracts a impedance is increased and due to parallel connection
fraction of its output to it’s input so that negative with the input, the input impedance decrease. So
feedback opposes the original signal. performance will be improved.
The applied negative feedback improves its’ 69. The feedback scheme used in a simple op-amp
performance namely gain stability, linearity, frequency based non-inverting amplifier is :
response, step response and reduce sensitivity to (a) series-series (b) series-shunt
parameter variations. Hence a two stage amplifier with (c) shunt-series (d) shunt- shunt
negative feedback is always stable. DRDO-2009
66. Two non-inverting amplifiers, one having a Ans. (c) : Shunt series feedback scheme used in a
unity gain and the other having a gain of simple op-amp based non-inverting amplifier.
twenty, are made using identical operational
amplifiers. As compared to the unity gain 70. Consider the following statements for negative
amplifier, the amplifier with gain twenty has feedback:
(a) Less negative feedback 1. It has more linear operation.
(b) Greater input impedance 2. It has improved frequency response.
(c) Less bandwidth 3. It has better stabilized voltage gain.
(d) None of the above 4. It has higher output impedence.
GATE-1991 Which of the above statements are correct?
Analog Electronics 388 YCT
 (a) 1 and 2 only (b) 2 and 3 only 73. A system has 3-stage cascaded amplifier, each
(c) 1, 2 and 3 only (d) 2, 3 and 4 only stage having a power gain of 10dB and noise
ESE-2021 figure of 6 dB. The overall noise figure is
Ans.(c) : Advantage of negative feedback of op- (a) 1.38 (b) 6.8
amp- (c) 4.33 (d) 10.43.
(1) It has more linear operation. TRB Poly. Lect. -2012
(2) It has improved frequency response. Ans. (c) : Overall noise figure of cascaded device is
(3) It has better stabilized voltage gain. F − 1 F3 − 1 F −1
(4) It has reduced noise. Fn = F1 + 2 + + ...... + n
G1 G1G 2 G1G 2 .....
(5) It has less distortion.
So option (c) is the correct. Given;
71. Which one of the following statements is Gain = 10dB and noise figure F = 6dB
correct regarding shunt-series feedback 6 = 10log ( F )
amplifier topology? F = 100.6
(a) The currents are compared and the output
F = 3.98
voltages are sampled.
(b) The currents are compared and the output So, overall noise figure = 3.98 + 3.98 − 1 + 3.98 − 1
currents are sampled. 10 100
(c) The voltages are compared and the output 2.98 2.98
currents are sampled. = 3.98 + +
10 100
(d) The voltages are compared and the output = 3.98 + 0.298 + 0.0298
voltages are sampled.
= 4.3078
ESE-2021
4.33
Ans.(b) : For shunt series feedback amplifier topology
the currents are compared and the output currents are 74. In a trans-conductance amplifier, it is desirable
sampled. to have
(a) A large input resistance and a large output
72. An amplifier without feedback has a voltage
resistance
gain of 50, input resistance of 1 kΩ and output
resistance of 2.5 kΩ. The input resistance of the (b) A large input resistance and a small output
current-shunt negative feedback amplifier (c) A small input resistance and a large output
using the above amplifier with a feedback resistance
factor of 0.2 is (d) A small input resistance and a small output
(a) 1/11 kΩ (b) 1/5 kΩ resistance
(c) 5 kΩ (d) 11 kΩ Nagaland PSC (Degree) 2018, Paper-II
Punjab PSC Poly. Lect.-20.08.2017 GATE-2017, 2014, 2007, 2006
GATE-2003 Ans. (a) : In a trans-conductance amplifier, it is
Ans. (a) : Given, desirable to have a large input resistance and a large
Gain, A = 50 output resistance. It is also known as current-series
Feedback factor, β = 0.2 feedback. For ideal trans-conductance input impedance
and output impedance are infinite.
Input Resistance, Ri = 1 kΩ
Output Resistance, Ro = 2.5 kΩ 75. In the ac equivalent circuit shown in the figure,
For current shunt negative feedback amplifier input if iin is the input current and RF is very large,
1 the type of feedback is
resistance decrease with and output increase
(1 + Aβ )
with (1 + Aβ).
So, input resistance with negative feedback
Ri
R if =
(1 + Aβ )
1× 103
=
1 + 50 × 0.2
(a) Voltage-voltage feedback
1× 103
R if = (b) Voltage-current feedback
11
(c) Current-voltage feedback
1 (d) Current-current feedback
R if = kΩ
11 GATE-2014, Set-I
Analog Electronics 389 YCT
Ans. (b) : Ans. (d) : A good transimpedance amplifier has low
input impedance and low output impedance. It is also
known as voltage shunt feedback. In voltage-shunt
feedback amplifier input impedance and output
impedances are decreased.
78. In with a negative feedback, the system gain
and stability respectively
(a) Decreases, Increases
(b) Increases, Decreases
(c) Decreases, Decreases
Voltage current feedback is in the above figure. (d) Increases, Increases
In the given figure sampling of current and mixing of RPSC VP/Suptd. ITI 05.11.2019
voltage. Ans. (a) : With a negative feedback, the system gain
76. The feedback topology in the amplifier circuit decreases and stability increases respectively. Negative
(the base bias circuit is not shown for feedback in a control system reduces the overall gain
simplicity) in the figure is and increases stability. It reduces the sensitivity of
output to input variation, distortion and noise reduction.
79. An amplifier has gain of 800. After adding
negative feedback, the gain is measured as 25.
The feedback factor is
(a) 25 (b) 0.0412
(c) 0.0388 (d) 0.01
Punjab PSC Poly. Lect. 20.08.2017
Ans. (c) : A (open loop gain) = 800
Av (feedback gain) = 25
(a) Voltage shunt feedback β (feedback factor)
(b) Current series feedback A
(c) Current shunt feedback Av =
1 + Aβ
(d) Voltage series feedback
800
UPPSC ITI Principal Asstt. Director-09.01.2022 25 =
GATE-2014, Set-II 1 + β(800)
Ans. (b) : 25 + 25 × 800β = 800
775
β=
25× 800
β = 0.0388
80. Roll-off factor is defined as
(a) The bandwidth occupied beyond the Nyquist
Bandwidth of the filter
(b) The performance of the filter or device
(c) Aliasing effect
(d) None of the above
In given circuit it is a current series feedback. In
current-series feedback, input and output impedance are Nagaland PSC- 2018, Diploma Paper-II
high, and infinite for ideal. In a current series feedback, Ans. (a) : Roll off Factor- Roll off factor is a measure
current is sampled from the output and voltage is of the excess bandwidth of filter. For Roll off factor of
feedback to the source. zero of an ideal rectangular nyquist pulse is obtained
77. A good transimpedance amplifier has this is called as nyquist minimum band width case.
(a) Low input impedance and high output 81. When positive feedback amplifiers are used as
impedance oscillators, the condition Aβ=1 is known as
(b) High input impedance and high output (a) Barkhausen criterion of oscillation
impedance (b) Pakinson criterion of oscillation
(c) High input impedance and low output (c) Positive criterion of oscillation
impedance (d) None of the above
(d) Low input impedance and low output KVS TGT (WE)- 2016
impedance Nagaland PSC CTSE- 2015, Paper-II
GATE-2018 KVS TGT (WE)- 2014
Analog Electronics 390 YCT
Ans. (a) : An oscillator is naming but an amplifier with Ans. (d) : Darlington pair : CC-CC :-
positive feedback is given by Af = A/1–Aβ
If Aβ = 1 then it becomes infinite and this implies that
amplifier is capable of producing an output even when
no input is applied.
This is called Barkhausen criterion for oscillation.
82. The Darlington pair is mainly used for
(a) Reducing distortion
(b) Power amplification
(c) Wideband voltage amplification
(d) Impedance matching
RRB SSE 02.09.2015, Shift-I
Ans. (d) :
A Darlington pair consists of two npn transistors the
emitter current of Q1 is the base current of Q2 and
collector terminal is common of both transistor.
85. The configuration of the given figure is a

In Darlington pair the output of the first amplifier is

connected to the input of the second amplifier collector
of both transistor is common in this circuit.
The Darlington pair provide high input impedance and
low output impedance so it is used for impedance
matching.
83. Negative voltage feedback in amplifiers (a) Precision integrator
S1: Improves gain stability (b) Hartley oscillator
S2: Reduces non linear distortion (c) Butterworth high pass filter
S3: Improves frequency response (d) Wien bridge oscillator
S4: Increase circuit stability ISRO Scientist- May, 2017
S5: Increase Input Impedance and decrease output Ans. (d) :
impedance
(a) Only S1 and S2 are correct
(b) Only S2 and S4 are correct
(c) Only S3 and S5 are correct
(d) All except S3 are correct
(e) All are correct
BEL-2015
CGPSC SO 14.02.2016
Ans. (e) : Negative voltage feedback in amplifiers
1- Improves gain stability
2- Reduces non linear distortion
3- Improves frequency response Given figure is Wien bridge oscillator, it can generate a
4- Increase circuit stability large range of frequencies.
5- Increase Input Impedance and decrease output 86. Decibel scale is useful while measuring voltage
impedance conversing
84. In darlington pair connection we are (a) Wider frequency ratio
connecting _____. (b) Wide voltage ratio
(a) CB-CC (b) CC-CE (c) Narrow frequency range
(c) CE-CB (d) CC-CC (d) Narrow voltage range
AAI-2015 RRB SSE 01.09.2015 Shit-I
Analog Electronics 391 YCT
Ans. (a) : A decibel scale is used for measuring voltage Ans. (c) : Loop gain |Aβ| = 1
covering the wider frequency ratio, decibel scale widely 2. Total phase shift should be 360º or 0º
used in electronics, communication and signals. 2. What is the value of capacitor of the Wien
87. Half power frequency represent below gain of bridge oscillator operating at resonant
(a) 0dB (b) 3dB frequency of 10 kHz with resistance of 100
(c) 2dB (d) 1dB kΩ ?
BEL-2015 (a) 149 pF (b) 159 pF
Ans. (b) : Gain of half power frequency (c) 169 pF (d) 189 pF
Input power = Pi ESE-2021
Ans.(b) : The frequency of oscillation-
Output power = P0
1
For half power frequency Pi = P0 2 ω0 =
RC
Power gain = 10log ( P0 Pi ) 1
f0 =
2πRC
 P  Given that, R = 100KΩ
= 10log  0 
 P0 2  f 0 = 10KHz
2 f0 =
1
= 10log  
1 2 π RC
= 3.010 1
C=
Power gain = 3dB 2π× 100 × 103 × 10 × 103
C = 159.155 × 10−12
88. The negative feedback in an amplifier leads to C = 159pF
which one of the following?
(a) Increase in current gain 3. What do phase-shift oscillators, twin-T
(b) Increase in voltage gain oscillators, and Wien bridge oscillators have in
(c) Decrease in voltage gain common?
(d) Decrease in bandwidth (i) They use RC frequency control
RRB SSE 01.09.2015, Shift-II (ii) They have a sinusoidal output
Ans. (c) : The feedback amplification factor (iii) They use amplifier gain to overcome
feedback loss
A
Af = (a) (i), (ii) and (iii) (b) (i) and (ii)
1 + Aβ (c) (i) and (iii) (d) (ii) and (iii)
Where A – open-loop gain NLC GET -24.11.2020
Aβ – loop gain Ans. (a) : The common characteristic among phase shift
As feedback increases the gain decreases (voltage gain) oscillators, twin-T oscillators and Wien bridge
thereby bandwidth increases. oscillators have are -
Effect of Negative feedback in amplifiers– They have a Audio frequency oscillator
They use RC frequency control and they use amplifier
1. reduces the gain and increases the stability in gain.
gain to overcome feedback loss.
2. increases the bandwidth to maintain the constant gain Twin-T oscillator (also known as a parallel-T
bandwidth product. oscillator) uses two interconnected resistive capacitive
3. reduces the distortion and noise in the amplifier. (RC) network together in parallel.
4. does not affect the signal to noise ratio. 4. Which of the following statements is not true?
(a) All oscillators satisfy the Barkhausen
(vii) Oscillator criterion
(b) An oscillator is an amplifier that supplies its
own input signal
1. The basic conditions for generating sinusoidal
(c) An oscillator is a circuit that converts dc to ac
voltage in a feedback oscillator is (are)
(d) In-phase feedback is called positive feedback
(a) Total loop gain should be 1
NLC GET -24.11.2020
(b) Total phase shift should be 360º
Ans. (a) : The oscillator is an electronic device that
(c) Both (a) and (b)
produces the output wave form periodically without any
(d) None of these
input. An oscillator is an amplifier that supplies its own
UPRVUNL AE-19.07. 2021, Shift-II input signal and by converting unidirectional current
TNPSE AE-2019 flow into an alternating wave form with a specified
Nagaland PSC-2018, Diploma, Paper-II frequency oscillators convert the DC current flow to an
Nagaland PSC (Degree) 2018, Paper-II alternating current flow.

Analog Electronics 392 YCT

Practically oscillators are amplifier circuit that have Ans. (d) : Wien bridge oscillator –
positive or regenerative feedback where the portion of
the output is feedback to the input side.
In general oscillators follow Barkhausen criteria for
stabilized oscillations but not all oscillators.
5. A Colpitts Oscillator is having tank
capacitances of 1nF and 10 nF, and inductance
of 0.1 µH. The gain required by the circuit to
start oscillating is:
(a) 10 (b) 100
(c) 1 (d) 1000 1
ISRO Scientist Engg.-2014 f=
2πRC
Ans. (a) : Given,
Commonly used as audio frequency oscillator.
C1 = 1nF
Precision measurement of capacitance in terms of
C2 = 10 nF
resistance and frequency.
L = 0.1µH Audio frequency range- 20 Hz to 20 kHz
The gain required by the circuit to start oscillating is:-
This oscillator is free from the circuit fluctuations
C and the ambient temperature.
| Ar | ≥ 2
C1 Provides constant output.
10nF Frequency of oscillations can be changed easily.
| Ar | ≥ Good frequency stability.
1nF
= 10 9. The basic amplifier in Wien bridge oscillator
6. Oscillator requires consists of
(a) No feedback (a) CE stage followed by CC
(b) Negative feedback (b) CC stage followed by CE
(c) Positive feedback (c) CB stage followed by CE
(d) Either positive or negative feedback (d) CE stage followed by CB
Nagaland PSC (CTSE) Diploma-2017, Paper II Nagaland PSC (CTSE) Diploma-2017, Paper II
Mizoram PSC Jr. Grade-2015, Paper-II Ans. (a) : The basic amplifier in Wien bridge oscillator
TNPSC AE-2014 consist of common emitter stage amplifier followed by
Mizoram PSC AE/SDO 2012-Paper-I common collector. A Wien's bridge is a type of
ISRO Scientist Engg.-2006 electronic circuit that generate sine wave.
Ans. (c) : Oscillator requires positive feedback. 10. ……….oscillator uses a tapped coil in the LC
tuned circuit
A
+ve feedback closed loop gain = A CL = (a) Hartley (b) Armstrong
1 − βA (c) Colpitts (d) Pierce
βA = 1 is maintained to satisfy Barkhausen criteria Nagaland PSC (CTSE) Diploma-2017, Paper II
due to which high gain can be obtained which produces- Ans. (a) : Hartley oscillator uses a tapped coil in LC
oscillation in the system. tuned circuit. The Hartley oscillator is after referred to
7. The oscillator with the best frequency stability as a self-inductance oscillator because coil L is centre
and accuracy is tapped.
(a) Hartley oscillator
11. If L1 = 1 mH, L2 = 2 mH and C = 0.1 nF in
(b) Colpitts Oscillator
Hartley oscillator, then f =_____ kHz.
(c) Tickler feedback oscillator
(d) Crystal controlled oscillator (a) 45.88 (b) 290.57
Nagaland PSC (CTSE) Degree -2018, Paper II (c) 145.57 (d) 572.25
Nagaland PSC (CTSE) Diploma-2017, Paper II UPRVUNL AE -19.07.2021, Shift-II
ISRO Scientist Engg.-2007, IES-1998 TSTRANSCO AE- 2018
Ans. (d) : The oscillator with the best frequency Ans. (b) : The frequency of the Hartley oscillator is
stability and accuracy is crystal controlled oscillator. 1
Crystal oscillator parameters doesn't change with given by f = LT = L1 + L2
temperature, the output frequency is highly stable. 2π L T C
8. A Wien bridge oscillator is a 1
(a) Microwave =
2 π 3 × 10 × 0.1 × 10 −9
−3
(b) RF oscillator
(c) VHF oscillator 1
= = 290575.84Hz
(d) Audio frequency oscillator 2π 0.3 × 10 −12
Nagaland PSC (CTSE) Diploma-2017, Paper II = 290.57 kHz.
Analog Electronics 393 YCT
12. If C1 = 200 pF, C2 = 50 pF in Colpitts oscillator 14. Colpitts and Hartley oscillators belong to a
and frequency is 1 MHz, then what is the value general class of oscillation that ______
of inductance required? feedback.
(a) 1.25 mH (b) 0.6332 mH (a) Voltage-series (b) Current-series
(c) 0.782 mH (d) 0.432 mH (c) Voltage-shunt (d) Current-shunt
UPRVUNL AE -19.07.2021, Shift-II TNPSC AE - 2018
Ans. (b) : Frequency in Colpitts oscillator, Ans. (a) : Colpitts and Hartley oscillator belongs to
general class of oscillation that voltage series feedback.
1
f= The main difference between colpitts and Hartley
2π CT L oscillator is former uses tapped capacitance while the
latter uses tapped inductance.
C1C 2
CT = 15. For the oscillator circuit given, expression for
C1 + C 2 the time period oscillator can be given by
200 ×10−12 × 50 ×10−12
CT =
( 200 + 50 )10−12
10,000 ×10−24
CT =
250 ×10−12
CT = 40 × 10−12
1
f=
2 π CT L (a) τln 3 (b) 2τln 3
(c) τln 2 (d) 2τln 2
1
L= TNPSC AE - 2018
( 2πf )
2
CT Ans. (b) :
1
L=
( 2 × 3.14 ×1×10 ) 6 2
× 40 × 10−12

L = 0.6332mH
13. Colpitts oscillator designed with an inductor L
produces frequency f. If it has to produce
frequency 2f, then the new inductance is
________.
(a) L/2 (b) L/4
(c) 2L (d) 4L
UPRVUNL AE -19.07.2021, Shift-II Time period of oscillator
KVS TGT (WE)- 2017  R + R2 + R3 
Ans. (b) : Output frequency of colpitts oscillator, T = ( R 2 + R 3 ) Cln  1 
 R1 
Where, ( R1 = R 2 = R 3 = R )
τ = RC
T = 2RC ln 3
T = 2τln3
16. The phase shift oscillator requires
(a) 180º phase shift from RC network
(b) 360º phase shift from RC network
(c) 0º phase shift from RC network
1 (d) 90º phase shift from RC network
f= KVS TGT (WE)- 2018
2π LCT GPSC Asstt. Prof. 11.04.2017
C1C2 1 KVS TGT (WE)- 2016
CT = , L=
C1 + C2 ( ) CT
2
2 πf Ans. (a) : A phase shift oscillator is a linear electronic
oscillator circuit that produce a sine wave output. A
L phase shift requires 180° phase shift from RC network.
For L' = the frequency become 2f.
4 17. Colpitts oscillator circuit uses
Analog Electronics 394 YCT
 (a) Two capacitors and one inductor C.C0
(b) Two inductors and one capacitor where Ceq =
C + C0
(c) One inductors and one capacitor
(d) Three inductors 1
• Series resonance frequency f(s) =
GPSC Asstt. Prof. 11.04.2017 2π L C
Ans. (a) : A colpitts oscillator is a type of LC oscillator, 19. An oscillator that consists of two
and it generates sinusoidal output signals with very high interdependent circuit such that output of each
frequency. Colpitts oscillator circuit uses two capacitors controls the input of the other is called a
and one inductor.
(a) sine wave oscillator
(b) feedback oscillator
(c) relaxation oscillator
(d) −ve resistance oscillator
Nagaland PSC CTSE- 2015, Paper-II
Mizoram PSC AE/SDO 2012-Paper-I
Ans. (c) : An oscillator that consist of two inter-
dependent circuit such that output of each controls the
input of the other is called a relaxation oscillator.
• A Relaxation oscillator is basically a non-linear
oscillator that has the ability to generate a non-
sinusoidal periodic waveform at output.
20. The Wien bridge oscillator is
(a) a free running oscillator
(b) a square wave generator
(c) a stable sine wave generator
(d) also called cosine oscillator
KVS TGT (WE)- 2018,2017
Mizoram PSC AE/SDO 2012-Paper-I
Ans. (c) : A Wien's bridge oscillator is a type of
electronic oscillator that generates sine wave. It can
18. Frequency stability in an oscillator can be generate a large range of frequencies.
achieved by • Wien bridge oscillator
(a) adjusting the phase shift 1
(b) controlling its gain frequency of oscillation f =
2π C1C 2 R 3 R 4
(c) incorporating a tuned circuit
(d) employing automatic biasing If C1 = C2 = C and R3 = R4 = R
TANGEDCO- 2015 1
Then f =
Mizoram PSC AE/SDO 2012-Paper-I 2π RC
Ans. (c) : Crystal oscillator is a best source to obtain a 21. In VHF oscillator using butterfly capacitor
very high precise and stable frequency of oscillation. It (a) only L (b) only C
has very low frequency drift due to change in
temperature and other parameter. (c) both L and C (d) none of these
Frequency stability can be achieved by incorporating a Mizoram PSC AE/SDO-2012 Paper-III
tuned circuit in an oscillator. Ans. (c) : In very high frequency oscillator using
butterfly capacitor both L and C are used.
22. In an oscillator crystal, the parallel resonant
frequency is .............. series resonant frequency
(a) equal to (b) higher than
(c) lower than (d) none of these
Mizoram PSC AE/SDO-2012 Paper-III
Ans. (b) : In an oscillator crystal, the parallel resonant
frequency is higher than series resonant frequency
23. Reflex klystron oscillator uses
(a) one cavity resonator
(b) two cavity resonators
1
• Parallel resonance frequency f p = (c) three cavity resonators
2π L Ceq (d) both (a) & (b)
Mizoram PSC IOLM-, Paper-III

Analog Electronics 395 YCT

Ans. (a) : A reflex klystron is an absolute oscillator Ans. (a) : Wien bridge oscillator–It is a low-
type in which the electron beam is reflected back along frequency, low distortion, tunable, high-purity sine
its path by a high potential electrode, this oscillator uses wave generator, often used in laboratory work.
one cavity resonator. In Wien bridge oscillator, if the open loop gain of the
24. RC oscillator is basically a- op-amp is greater, then greater is the frequency stability
(a) Square wave generator of the oscillator.
(b) Pulse generator 28. When L is doubled and C is halved, the
(c) Sinusoidal wave generator frequency of oscillation is?
(d) Triangular wave generator (a) Doubled (b) Halved
UPPCL AE-16.11.2013
(c) One quarter (d) Unchanged
Ans. (c) : An RC oscillator is a basically type of TNPSC AE-2014
feedback oscillator which consist of a transistor an
amplifying device, a vacuum tube and an op-amp. An 1
Ans. (d) : f =
RC oscillator is basically a sinusoidal generator. 2π LC
25. In a phase shift oscillator, the minimum When L' = 2L
number of RC circuits required to generate a
C' = C/2
phase shift of 180º between input and output is
(a) 1 (b) 2 1 1
then, f = =
(c) 3 (d) 4 C 2π LC
UJVNL AE-2016 2π 2L ×
2
KVS TGT (WE)- 2014
29. The horizontal sweep oscillator in a TV
Ans. (c) : In a phase shift oscillator, the minimum operates at
number of RC circuits required to generate a phase shift
of 180º between input and output is 3. (a) 625 Hz (b) 1250 Hz
(c) 15625 Hz (d) 50 Hz
TNPSC AE-2014
Ans. (c) : Horizontal sweep,
Sweep rate = 15625 Hz
Sweep time = 64 µs
64 µs = 52 µs + 12 µs
52 µs = Beam travels from left to right
12 µs = Beam travels from right to left, Blanked out,
line blanking period.
30. Crystal oscillator are superior to tuned LC
oscillator because
(a) They have very high level of frequency
stability
26. The oscillator circuit (b) They have moderate level of frequency
(a) Cannot be operated in class A condition stability
(b) Can be operated in class A condition to give (c) They have a high value of Q-factor
sinusoidal waveform (d) Both (They have very high level of frequency
(c) Can be operated in class A condition to give stability) and (They have moderate level of
distorted waveform frequency stability)
(d) Can be operated in class A condition for MPPSC Forest Service Exam.-2014
better wave shape Ans. (a) : A crystal oscillator are superior to tuned LC
TNPSC AE-2014 oscillator because crystal oscillator has high level of
Ans. (b) : The essential condition for maintaining frequency stability. It has wide range of operating
oscillations and for finding the value of frequency is– temperature range.
βA = 1+ j0 or βA ∠φ = 1 ∠0
31. Wien bridge oscillator is used frequently
(i) The feedback factor or loop gain |βA| = 1
(a) When ever high feedback ratio is required
(ii) The net phase shift around the loop is 0º.
(b) When ever square output waves are required
27. In Wien bridge oscillator, if the open loop gain
(c) When ever wide range of high purity sine
of the Op-Amp is greater, then ______is the
frequency stability of the oscillator. waves are required
(a) Greater (b) Lesser (d) When ever extremely high resonant
(c) Zero (d) Constant frequencies are required
TNPSC AE-2014 MPPSC Forest Service Exam.-2014

Analog Electronics 396 YCT

Ans. (c) : A Wien bridge oscillator is a simple circuit 37. A Hartley oscillator uses
that can be set to continuous oscillation which output is (a) A tapped inductor (b) A tapped capacitor
sine wave. Hence Wien bridge is used frequently when (c) Both (a) and (b) (d) Neither (a) nor (b)
ever wide range high sine waves are required. KVS TGT (WE)- 2018
32. Barkhausen criterion is related to Mizoram PSC Jr. Grade-2015, Paper-II
(a) Filter (b) Amplifier KVS TGT (WE)- 2014
(c) Oscillator (d) None of these Mizoram PSC AE/SDO -2012, Paper-II
MPPSC Forest Service Exam.-2014 Ans. (a) : A Hartley oscillator uses a tapped inductor.
Ans. (c) : Barkhausen criterion has two conditions first
the closed-loop gain is equal to 1, second the closed
loop phase angle is equal to 0º, with these condition the
oscillator circuit would generate a sinusoidal oscillator
signal.
33. Positive feedback is utilized in
(a) Power amplifier
(b) Low power amplifier
(c) Oscillator
(d) None of these
MPPSC Forest Service Exam.-2014
Ans. (c) : The condition for positive feedback is that a
partition of the output is combined in phase with the
input.
LT = L1 + L2
The use of positive feedback is useful for producing
oscillators. 1
f=
34. If 8 identical RC sections are used in the 2 π LT C
feedback path of a Phase-shift oscillator (with
non-inverting amplifier) it will oscillate at the 38. Crystals used in oscillator circuits for the
frequency at which each section shifts Phase by purpose of stabilizing frequency are made of
(a) 300 (b) 450 (a) quartz
0
(c) 60 (d) 22.50 (b) silicon
Nagaland PSC CTSE (Degree)-2016, Paper-II (c) germanium
Ans. (d) : In a 8 identical RC section, Provides phase (d) some other semiconductor material
180º Nagaland PSC 2018, Diploma Paper-II
shift in oscillator = = 22.5º
8 UPPCL AE-16.11.2013
35. What is the typical value of Q of a crystal? RPCS Lect.-2011
(a) 100 (b) 1000 Ans. (a) : Piezo-electric quartz crystal behaves like an
(c) 10,000 (d) More than 10,000 RLC circuit, composed of an inductor, capacitor and
Nagaland PSC CTSE (Diploma)-2017, Paper-I resistor, with a precise resonant frequency.
Ans. (d) : Piezoelectric effect quartz crystal has a very
39. What is the frequency of oscillation for an RC
high quality factor.
A typical Q for a quartz oscillator ranges from 104 to phase-shift oscillator with R of 10 kΩ and C of
106. The maximum Q for high stability quartz oscillator 0.001 µF in each of its three RC sections?
can be estimated as Q = 16 million/f, where f is the (a) 5.0 kHz (b) 5.5 kHz
resonance frequency in megahertz. (c) 6.0 kHz (d) 6.5 kHz
36. Quartz crystal is mostly used in crystal IES-2019
oscillator because Ans. (d) : R = 10kΩ
(a) It is easily available
C = 0.001µF
(b) It has superior electrical properties
(c) It is quite inexpensive C = 0.001× 10 −6 F
(d) It is very rugged Frequency oscillation for an RC phase-shift oscillator-
Nagaland PSC CTSE (Diploma)-2017, Paper-I 1
f0 =
Ans. (b) : This is mainly due to its low series resistance, 2πRC 6
Rs. As a result, quartz crystals make an excellent 1
component choice for use in oscillators especially in fo =
2 π × 10 × 10 × 0.001× 10−6 × 6
3
very high frequency oscillators.
1
Quartz crystal is mostly used in crystal oscillator fo =
because it has superior electrical properties. 2 × 3.14 × 0.01×10−6 × 2.45 × 103

Analog Electronics 397 YCT

 100 ×1×106 ×100 ×100 Which of the above statements are correct?
fo = (a) 1 and 3 only (b) 2 and 4 only
628 × 245 × 103
(c) 1 and 4 only (d) 2 and 3 only
1×106 ×106
fo = IES-2016
153860 ×103
Ans. (a) : Wien bridge has a larger bandwidth than the
f o = 6.499 kHz
phase shift oscillator.
fo 6.5 kHz Wien bridge has two capacitor while the phase shift
oscillator has 3 capacitor.
40. In the Wien bridge oscillator, the 0o phase-shift
is met by using lead-lag network and by using. Advantages of Wien bridge oscillator -
(a) Inverting op-amp i) It gives constant output.
(b) Non-inverting op-amp ii) The circuit works quite easily.
(c) Feedback op-amp iii) The overall gain is high.
(d) High-gain op-amp 43. Consider the following statements related to
IES-2019 oscillator circuits:
Ans. (b) : In the Wien bridge oscillator, the 0º phase 1. The tank circuit of a Hartley oscillator is
shift is met by using lead-lag network and by using non- made up of a tapped capacitor and a
inverting op-amp. common inductor.
2. The tank circuit of a Colpitts oscillator is
made up of a tapped capacitor and a
common inductor.
3. The Wien bridge oscillator is essentially a
two-stage amplifier with an RC bridge in
the first stage, and the second stage serving
as an inverter.
OP- Amp non-inverting Amplifier 4. Crystal oscillators are fixed frequency
The wien bridge has RC circuit in the two adjacent oscillators with a high Q-factor.
branches and determines the frequency of oscillations as Which of the above statements are correct?
well as acts as a feedback circuit. At one particular (a) 1,2 and 3 only (b) 2,3, and 4 only
frequency, the wien bridge is balanced and produces 0º (c) 1,2 and 4 only (d) 1,3 and 4 only
phase shift.
KVS TGT (WE)- 2017
41. In a sinusoidal oscillator, sustained oscillations
will be produced only if the loop gain (at the IES-2016
oscillation frequency) is Ans. (b) : The tank circuit of a colpitts oscillator is
(a) Less than unity but not zero made up of a tapped capacitor and a common inductor.
(b) Zero The Wien bridge oscillator is essentially a two-stage
(c) Unity amplifier with an RC bridge in the first-stage and the
(d) Greater than unity second stage serving as an inverter.
IES-2016 Crystal oscillators are fixed frequency oscillators
KVS TGT (WE)- 2014 with a high Q-factor.
DRDO -2008 44. For an Op-Amp phase shift oscillation, the
Ans. (c) : In a sinusoidal oscillator, sustained frequency of oscillations is
oscillations will be produced only if the loop gain (at 1 1
the oscillation frequency) is unity. (a) (b)
Barkhausen criteria for oscillation 2πRC 2πR 2C 2
i) Aβ = 1 1 1
(c) (d)
ii) ∠Aβ = 0º or 360º 2πRC 6 2πRC 3
KVS TGT (WE)- 2017
42. Consider the following statements regarding
Wien bridge oscillator: IES-2015
1. It has a larger bandwidth than the phase shift Ans. (c) : In a phase shift oscillator, a phase shift of
oscillator 180º is obtained with a phase shift circuit instead of
2. It has a smaller bandwidth than the phase inductive or capacitive coupling.
shift oscillator For an Op-Amp phase shift oscillation the frequency of
3. It has 2 capacitors while the phase shift oscillation is-
oscillator has 3 capacitors.
1
4. It has 3 capacitors while the phase shift fo = Hz
oscillator has 2 capacitors. 2πRC 6

Analog Electronics 398 YCT

45. For various types of oscillators, the correct 47. Which one of the following oscillators is well
statement is : suited for the generation of wide range audio
(a) LC oscillators are more stable than crystal frequency sine waves?
oscillators (a) RC phase-shift oscillator
(b) Crystal oscillators have highest Q (b) Wien-bridge oscillator
(c) Phase-shift oscillators have the widest range (c) Colpitts oscillator
of frequency (d) Hartley oscillator
(d) Wien bridge oscillator is used where a single
IES-2009
frequency oscillator is required
ISRO Scientist Engg.-2012 Ans. (b) : Wien-bridge oscillator is well suited for the
generation of wide range audio frequency sine waves.
Ans. (b) : Various oscillator
Wien-bridge oscillator has wide range (5Hz to 1MHz)
Parameter LC Crystal RC phase audio frequency.
shift
Frequency It is a radio Fixed Audio
frequency frequency range
oscillator oscillator frequency
Stability Less stable More stable Stable
Quality Less Higher Less
factor
46. Which oscillator is characterized by a split
capacitor in its tank circuit?
(a) RC phase shift oscillator
(b) Colpitts oscillator 48. In a practical oscillator circuit, which one of
(c) Wien bridge oscillator the following limits the amplitude of the
(d) None of the above oscillations?
IES-2014 (a) Onset of non-linearity
Ans. (b) : Colpitts oscillator is characterized by a split (b) Power supply voltage
capacitor in its tank circuit. Colpitt’s oscillator uses two (c) Oscillation frequencies
capacitors and placed across a common inductor L and (d) Temperature of the active device
the centre of the two capacitors is tapped. The tank IES-2008
circuit is made up of C1, C2 and L.
Ans. (a) : In a practical oscillator circuit, onset of non-
The frequency of oscillation
linearity limits the amplitude of the oscillations. The
1
f= amplitude limit of sinusoidal oscillator is caused by
2 π LC T non-linearity. As the circuit element cannot have perfect
C1C 2 linear characteristics. The amplitude distortion of a
Where CT = sinusoidal oscillator is controlled by the onset of non-
C1 + C 2
linearity of the amplifying device.
49. Match List-I (Name of the oscillator) with List-
II (Characteristics) and select the correct
answer using the code given below the lists
List-I List-II
A. Colpitts Oscillator 1. RC Oscillator
B. Phase Shift Oscillator 2. LC Oscillator
C. Tunnel diode 3. Negative
Oscillator resistance
Oscillator
D. Relaxation Oscillator 4. Sweep circuits
A B C D
(a) 1 2 3 4
(b) 2 1 3 4
(c) 1 2 4 3
(d) 2 1 4 3
IES-2005
Analog Electronics 399 YCT
Ans. (b) : Colpitts oscillator- LC oscillator colpitt’s Ans. (a) :
oscillator uses two capacitors C1 and C2 placed across a
common inductor L and the centre of the two capacitors
is tapped.
Phase shift oscillator- RC oscillator a RC phase shift
oscillator gives 180º phase shift at output.
Tunnel diode oscillator-Negative resistance
oscillator.
Relaxation oscillator - sweep circuits.
50. Consider the following statements regarding a
common emitter amplifier it can be converted
into an oscillator by:
1. Providing adequate positive feedback An amplifier will generate stable sinusoidal oscillation
2. Phase shifting the output by 180º and if we provide feedback such that its poles lies close to
feeding this phase-shifted output to the jω -axis in the right half of s-plane.
input 52. Which one of the following circuits is most
3. Using only a series tuned circuit as a load suitable as an oscillator at a frequency of 100
on the amplifier. Hz.
4. Using a negative resistance device it’s a (a) Hartley oscillator (b) Colpitts oscillator
load on the amplifier. (c) Crystal oscillator (d) Twin-T oscillator
Which of the above statements are correct? IES-2001
(a) 1, 2, 3 and 4 (b) 1 and 2 RPSC Vice Principal ITI-2016
(c) 1, 3 and 4 (d) 3 and 4 Ans. (d) : Twin-T oscillator circuit is most suitable as
IES-2015, 2002 an oscillator at a frequency of 100Hz. Twin-T is
Ans. (b) : basically a frequency selective network. The Twin-T
network acts as the phase lead-lag network.
53. A relaxation oscillator is one which
(a) Has two stable states
(b) Oscillates continuously
(c) Relaxes indefinitely
(d) produces non-sinusoidal output.
Mizoram PSC IOLM-2018, Paper-II
Nagaland PSC (Degree) 2018, Paper-II
IES-2001
Ans. (d) : A relaxation oscillator is one which produces
non-sinusoidal output.

Common Emitter Amplifier

Common emitter amplifier provides adequate positive
feedback.
Common emitter amplifier has 180º phase shift at  1+ β 
Time period of output signal, T = 2RC log  
output and feed this phase-shifted output to the input.  j−β 
51. An amplifier will generate stable sinusoidal Where,
oscillations if we provide feedback such that
R → feedback resistance
(a) Its poles lie close to jω-axis in the right half
of s-plane. β → feedback fraction
(b) Its poles lie close to jω-axis in the left half of Relaxation oscillator and UJT oscillator are non-linear
s-plane. oscillator. Non-linear oscillators or function generators
generate square-wave triangular wave, pulses etc.
(c) Its poles lie on the +ve real axis in s-plane
(d) Its poles lie anywhere in s-plane. 54. In every practical oscillator, the loop gain is
slightly larger than unity and the amplitude of
IES-2002 the oscillations is limited by the-
Analog Electronics 400 YCT
 (a) Magnitude of the loop Ans. (c) :
(b) Onset of non-linearity Oscillator Characteristics features
(c) Magnitude of the gain of the amplifier (A) Wien Bridge RC oscillator for audio
(d) Feedback transmission factor frequency applications.
IES-2000 (B) Colpitts RF oscillator two capacitances
Ans. (b) : In every practical oscillator, the loop gain is and one inductance as the
slightly larger than unity and the amplitude of the reactance network.
oscillations is limited by the onset of non-linearity. The (C) Hartley RF oscillator two inductance and
amplitude limit of sinusoidal oscillator is caused by one capacitance on the reactance
non-linearity. As the circuit element can not have network
perfect linear characteristics. (D) Clapp LC oscillator for radio frequency
55. A Hartley oscillator is used for generating : three capacitances & one
(a) Very low frequency oscillation inductance in the reactance
(b) Radio-frequency oscillation network.
(c) Microwave oscillation 57. By proper selection of Rf and R1, the circuit
(d) Audio-frequency oscillation shown in the given figure can be used as a
IES-1999
MPPSC Forest Service Exam.-2014
Ans. (b) : A Hartley oscillator is used for generating
radio-frequency oscillation.

(a) Ramp generator

(b) Square wave generator
(c) Sawtooth generator
(d) Sine wave generator
IES-1996
Ans. (d) : By proper selection of Rf and R1, the circuit
shown in the given figure can be used as a sine wave
Frequency of oscillation for Hartley oscillator generator
1
f0 =
2 π C ( L1 + L 2 )
56. Match List-I with List-II and select the correct
answer using the codes given below the lists :
List-I List-II
(Oscillator) (Characteristics Features)
A. Wien Bridge 1. RF oscillator two
inductance and one
capacitance on the
The sine wave generator is an excellent tool for
reactance network.
generating waves with speakers or wave drivers. Sine
B. Colpitts 2. LC oscillator for radio wave generator is a pure sine wave output variable from
frequency : three
1Hz to 1 MHz.
capacitances and one
inductance in the reactance 58. Match List-I with List-II and select the correct
network. answer using the code given below the lists :
C. Hartley 3. RC oscillator for audio List-I List-II
frequency applications (Name of the circuit) (Characteristics)
D. Clapp 4. RF oscillator : two A. Tunnel diode 1. Produces high
capacitances and one oscillators current pulses of
inductance as the reactance short duration.
network.
B. UJT oscillators 2. An LC oscillator
A B C D
used for generation
(a) 2 1 4 3
of sine wave at RF
(b) 2 4 1 3
(c) 3 4 1 2 C. Hartley oscillators 3. A negative resistance
(d) 3 1 4 2 oscillator for
IES-1996 microwave frequency

Analog Electronics 401 YCT

 D. Blocking oscillators 4. Uses negative Differential eqn (ii) w.r.t. K
resistance property d 2 h f e 58
for the generation of = >0
saw tooth wave-form dK 2 K 3
Codes : 29
Put the value of k = in equation (i)
A B C D 2
(a) 3 2 1 4 29 29
(b) 1 2 4 3 h fe / min = 23 + + 4×
29 / 2 2
(c) 3 4 2 1 58
(d) 4 3 1 2 = 23 + + 2 29
29
IES-1995
58
Ans. (c) : = 23 + + 2 × 5.385
5.385
Sr. Oscillators Characteristics = 23 + 10.77 + 10.77
No.
h fe / min = 44.54
(A) Tunnel diode A negative resistance
oscillators oscillator for 60. Match the following
microwave frequency. List-I List-II
(p) Hartley (1) Low frequency oscillator
(B) UJT oscillators Uses negative (q) Wien-bridge (2) High frequency oscillator
resistance property for (r) Crystal (3) Stable frequency oscillator
the generation of saw (4) Relaxation oscillator
tooth wave-form. (5) Negative resistance
(C) Hartley oscillators An LC oscillator used oscillator
for generation of sine p q r
wave at RF. (a) 2 1 3
(D) Blocking oscillators Produces high current (b) 1 2 3
pulses of short (c) 2 3 1
duration. (d) 3 1 2
59. The minimum value of hfe of a transistor to be Punjab PSC Poly. Lect. 20.08.2017
used in three-section RC phase shift oscillator GATE-1994
is Ans. (a) :
(a) 54.4 (b) 45.4 (p) Hartley High frequency oscillator (10
(c) 44.5 (d) 29 kHz to 100 MHz)
UPRVUNL AE -19.07.2021, Shift-II (q) Wien-bridge Low frequency oscillator
IES-1995 oscillator (1Hz to 1 MHz)
(r) Crystal oscillator Stable frequency oscillator
Ans. (c) : The minimum value of hfe of a transistor to be
(For fixed frequency)
used in three-section RC
29 61. Value of R the oscillator shown in the given
h fe = 23 + + 4K .............(i) figure. So chosen that it just oscillates at an
K
angular frequencies of ' ω'. The value of 'ω' and
Where; the required value of R will respectively be
R
K= C
R
R C = Collector Resistance
R = Resistance of an RC section
Differential eqn (i) w.r.t. K
d h fe 29
=0− 2 +4
dK K
d hf e 29
= 4 − 2 = 0 .......(ii)
dK K (a) 105 rad/sec, 2 × 104 Ω
4K 2 − 29 = 0 (b) 2 × 104 rad/sec, 2 × 104 Ω
(c) 2 × 104 rad/sec, 105 Ω
29 105 rad/sec, 105 Ω
K= (d)
2 GATE-1996

Analog Electronics 402 YCT

Ans. (a) : Given, R + 1k = 21×1k
C = 0.01µF R f = 100kΩ , Rin = 5kΩ R = 21k − 1k
L = 10mH R1 = 1kΩ R = 20kΩ or R = 2 ×104 Ω
1 62. The configuration of the figure is a
Angular frequencies, ω =
LC
1
ω=
10 ×10 × 0.01×10−6
−3

ω = 105 rad/sec

(a) Precision integrator

(b) Hartley oscillator
(c) Butterworth high pass filter
According Nodal analysis–
(d) Wien-bridge oscillator
Vf − Vo Vf Vf GATE-2000
+ + + Vf X C = 0
R 1k X L Ans. (d) : Wien-bridge oscillator
Vf Vo Vf   1 
− + + Vf  j  − ωc   = 0
R R 1k   ωL 
1 1   1   Vo
Vf  +  + Vf  j  ωL − ωc   = R ......... (i)
 R 1k    
1
From equation (i) for oscillation, ωc =
ωL
1
ωc − =0
ωL
1
ωc = 1
ωL Resonant frequency, f o =
2πRC
1 1 V
Vf  +  = o Used for low frequency oscillator (1Hz to 1 MHz)
 R 1k  R 63. The oscillator circuit shown in the figure is
1
Vf 1k
β= = R = ............(2)
Vo 1
+
1 R + 1k
R 1k
Rf
A = 1+
R in
100
= 1+
5
(a)
Hartley oscillator with foscillation = 79.6 MHz
A = 21
(b)
Colpitts oscillator with foscillation = 50.3 MHz
1 1 (c)
Hartley oscillator with foscillation = 159.2 MHz
β= = (d)
Colpitts oscillator with foscillation = 159.2 MHz
A 21
From equation (2) GATE-2001
Ans. (b) : Given circuit is a colpitts oscillator
1k
β= Given, L = 10µH
1k + R
C1 = 2pF
1 1k
= C2 = 2pF
A R + 1k
1 1k C1C2 2× 2
= Ceq = =
21 R + 1k C1 + C2 2 + 2

Analog Electronics 403 YCT

 4 βVo R 2 + βVo R1 = Vo R1
= =1
4  1
βR 2 + βR1 = R1 β = 6 
Ceq = 1pF
1 1
1 × R 2 + R 1 = R1
f= 6 6
2 π LCeq
R 2 + R1 = 6R1
1
= R 2 = 5R1
2π 10 × 10−6 × 10−12
65. The oscillator circuit shown in the figure has
1 an ideal inverting amplifier. Its frequency of
=
2 × 3.14 × 10−9 × 3.16 oscillation (in Hz) is
1
=
19.8448 ×10−9
f = 50.5MHz or f 50.3 MHz
64. The circuit in the figure employs positive
feedback and is intended to generate sinusoidal
oscillation.
V (f) 1
If at a frequency f0' B(f) = f = ∠0° then to 1 1
V0 (f) 6 (a) (b)
(2π 6RC) (2πRC)
sustain oscillation at this frequency
1 1
(c) (d)
( 6RC) 6(2πRC)
GATE-2003
Ans. (a) : Inverting Amplifier-

(a) R2 = 5R1 (b) R2 = 6R1

R R
(c) R 2 = 1 (d) R 2 = 1
6 5
GATE-2002
Ans. (a) :
The oscillator circuit shown in the above figure has an
ideal inverting amplifier. Its frequency of oscillation (in
Hz) is
1
fo = Hz
2π 6RC
In RC phase shift oscillator, the RC network consisting
of three identical RC sections determines the frequency
of oscillations as well as produces 180º phase shift.
66. The value of C required for sinusoidal
oscillations of frequency 1 kHz in the circuit of
Given, the figure is
1
β=
6
KCL at input -
βV0 − 0 βV0 − V0
+ =0
R1 R2
βVo R 2 + βVo R1 − Vo R1
=0
R 1R 2

Analog Electronics 404 YCT

 1 67. The circuit shown in the figure has an ideal op-
(a) µF (b) 2 πµF
2π amp. The oscillation frequency and the
1 condition to sustain the oscillations,
(c) µF (d) 2π 6µF respectively, are
2π 6
GATE-2004
Ans. (a) :

1
(a) and R1 = R2
CR
1
(b) and R1 = 4R2
CR
1
Given, (c) and R1 = R2
2CR
R f = 2.1kΩ
1
R = R1 = 1kΩ (d) and R1 = 4R2
2CR
KCL at output Node
GATE-2015, Set-I
VO − V1 V1 V1
− − =0 Ans. (d) :
XC + R XC R
VO − V1  1 1
= V1  + 
XC + R  XC R 
VO − V1 (X + R )
= V1 C
XC + R XC R
VO V1 ( X C + R )
2

− =
V1 V1 XCR
1
Frequency of Wien bridge oscillator, f o =
VO ( X C + R )
2
1 2πRC
= +1 XC = −
V1 XCR ωC 1 1
Oscillation frequency, ωo = ⇒R=
VO jωC  1 2 jR  RC ω0 C
= − 2 2 + R −
2
 +1
V1 R  ωC ωC  When time constant is doubled then frequency becomes
Imaginary part is zero for oscillation. half.
−1 1
+ ωCR = 0 So, ωo =
ωCR 2RC
ω2C2 R 2 − 1 = 0 1
Z1 = 2R + = 2 ( R − jR )
1 jωC
ω2 = 2 2
CR 1 R
1 R×
ω= 2 jωC 2 jωC
Z2 = =
CR 1 2 jωCR + 1
1 R+
C= 2 jωC 2 jωC
ωR
R
1 Z2 =
= 2 jωCR + 1
2πf R
1 R2 j
= Z2 =
2π × 103 × 103 R − jR
1 R2
C= µF Z2 =
2π R + jR

Analog Electronics 405 YCT

 R2 Ans. (a) :
Z2 R + jR
β= =
Z1 + Z2 R2
2 ( R − jR ) +
R + jR
R2 R + jR
β= ×
R + jR 2 ( R − j2 R 2 ) + R 2
2

R2
=
5R 2
1
β=
5
R1 1
1+ = Introduce amplitude stabilization by preventing the
R2 β OP-Amp from saturating and thus producing sinusoidal
R1 oscillations of fixed amplitude.
1+ =5
R2 69. In an RC phase shift oscillator using FET, for
R1 sustained oscillations, the minimum voltage
=4 gain of the FET should be
R2
(a) 29
R 1 = 4R 2 (b) 64
(c) 51
68. Consider the oscillator circuit shown in the
figure. The function of the network (shown in (d) 56
dotted lines) consisting of the 100 kΩ resistor in APPSC POLY. LECT. 14.03.2020
series with the two diodes connected back-to- Nagaland PSC CTSC (Degree)-2017, Paper-II
back is to: Ans. (a) : In an RC phase shift oscillator using FET, for
sustained oscillations, the minimum voltage gain of the
FET should be 29.
70.

(a) Introduce amplitude stabilization by

preventing the op-amp from saturating and
thus producing sinusoidal oscillations of fixed
amplitude
(b) Introduce amplitude stabilization by forcing For a Hartley Oscillator X1, X2 and X3
the op-amp to swing between positive and respectively are :
negative saturation and thus producing square (a) L.L.C.
wave oscillations of fixed amplitude (b) C.C.L
(c) Introduce frequency stabilization by forcing (c) L.C.L.
the circuit to oscillate at a single frequency (d) LC.L.C
(d) Enable the loop gain to take on a value that APPSC Poly. Lect. 15.03.2020
produces square wave oscillations Ans. (a) : X 1 = X 2 = L
GATE-2016, Set-I X 3 = C

Analog Electronics 406 YCT

 • β = 1/ 3 for oscillation
Where β = Feedback factor
• R 2 ≥ 2R1 for oscillator
73. A beat frequency oscillator uses
(a) Two RF oscillators (b) Two AF oscillators
(c) One RF oscillator (d) One AF oscillator
Nagaland PSC (Degree) 2018, Paper-II
Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (a) : Two RF oscillators.
1
f0 =
2π L T ⋅ C
LT = L1 + L 2
71. FET phase shift oscillator uses
(a) Voltage series feedback
It uses two radio frequency (RF) oscillators. One is
(b) Voltage shunt feedback
fixed frequency oscillator and other is variable
(c) Current series feedback frequency oscillator. The output of both oscillators are
(d) Current shunt feedback fed as a input to the mixer. The mixer output is the
Nagaland PSC (Degree) 2018, Paper-II signal with a frequency given by difference of two input
TSGENCO AE-2015 frequency.
Ans. (a) : Voltage series feedback- In a FET phase 74. A blocking oscillator
shift oscillator voltage series feedback is used that is (a) Is a triggered oscillator
feedback voltage proportional to the output voltage (b) Generates sinusoidal waves
(Vout) and supplied in series with the input signal at the
(c) Is an amplifier with a negative feedback
gate is used.
(d) Produces very sharp and narrow pulses
Nagaland PSC (Degree) 2018, Paper-II
Ans. (d) : A blocking oscillators is a waveform
generator that is used to produce very sharp and narrow
pulses and are used as high impedance switches and
frequency dividers. It is simple configuration of discrete
electronic component which can produces a free
running signal.
75. Which sinusoidal oscillator is preferred
(a) Resonant circuit (b) RC phase shift
(c) Negative resistance (d) None of these
Nagaland PSC- 2018, Diploma Paper-II
Ans. (b) : RC phase shift oscillator is preferred because
capacitor passes ac signal through it.

Application of FET phase shift oscillator :-

FET phase shift oscillator is used for generating signals
over a wide frequency range.
72. In a Wien bridge oscillator, the positive
feedback attenuation is
(a) 1/3 (b) 1/29
(c) –29 (d) 3
Nagaland PSC (Degree) 2018, Paper-II
Ans. (a) : Wien bridge oscillator
1
• Frequency oscillator ( f ) =
2π R 3 R 4 C 2 C1

Analog Electronics 407 YCT

R.C shift oscillator is used to generate the signals over Ans. (a) : When a transfer function has one pair of pole
an extensive range of frequency. They are used in at imaginary axis. The system will produce oscillatory
musical instruments, GPS units & voice synthesis. output. Hence on oscillator has its pole on imaginary
76. Blocking oscillators are used as axis.
(a) Abrut pulse generator 80. The range of frequency generated by VHF
(b) Low impedance switches oscillator is-
(c) High impedance switches and frequency (a) 300 MHz - 3 GHz (b) Above 3 GHz
dividers (c) 30 MHz - 300 MHz (d) 20 kHz - 30 MHz
(d) None of the above RRB JE- 31.08.2019, 10 AM-12 PM
Nagaland PSC CTSE- 2015, Paper-II Ans. (c) : VHF (Very High Frequency) (30 MHz –
Ans. (c) : Blocking oscillators are used as high 300 MHz)
impedance switches and frequency dividers. In FM radio broadcasts, very high frequency are
Note– It is simple configuration of discrete electronic typically used for two way land mobile radio systems,
components which can produce a free running signal. long-distance data communications and maritime
communications. VHF includes radio waves ranging
77. Conditions for oscillations in oscillator circuits
from 30MHz to 300 MHz.
are:
C1: a phase shift of 0º around the feedback loop Type of Frequency Application
frequency Range
C2: a phase shift around the feedback loop of 180º
C3: a gain of 1 around the feedback loop Low frequency 30 to 300 kHz Navigation
C4: the attenuation of the feedback circuit must be Medium 300 kHz to 3 Marine/Aircraft
one-third frequency MHz navigation, AM
(a) Conditions C1 and C3 are correct broadcast
(b) Conditions C1 and C4 are correct High frequency 3 MHz to 30 Broad coasting,
(c) Conditions C2 and C4 are correct MHz Mobile radio
(d) Conditions C2 and C3 are correct Very high 30 MHz to 300 FM broad
(e) Conditions C1 alone is correct frequency MHz coasting
CGPSC SO 14.02.2016 Ultra high 300 MHz to 3 Cell phone,
Ans. (a) : An oscillation can designed so that the frequency GHz mobile radio,
oscillation frequency can be varied over some range by WLAN
an input voltage or current. Super high 3 GHz to 30 Radar TV
Conditions : 1. gain of 1 around the feedbacks loop. frequency GHz
(2) A phase shift of 0º around the feedbacks loop. 81. A high Q-quartz crystal exhibits series
78. For MHz frequency operation which type of resonance at the frequency ωs and parallel
oscillator is suitable. resonance at ωp, then-
(a) RC phase shift (b) Wien bridge (a) ωs is very close but less than ωp
(c) Hartley (d) All (b) ωs is very close, but greater than ωp
NPCIL-2015 (c) ωs >> ωp
(d) ωs << ωp
Ans. (c) : For MHz frequency operation Hartley
oscillator is more suitable. Hartley oscillator is a type of RRB JE- 31.08.2019, 10 AM-12 PM
LC oscillator that generates undamped sinusoidal BPSC Polytechnic Lecturer-2014
oscillations whose tank circuit consists of two inductors Ans. (a) :
and a capacitor.
In this oscillator
where ( L eq = L1 + L 2 )
1
fo =
2π Leq C
79. The poles of an oscillator are:
(a) lie on the imaginary axis.
(b) lie on unit circle centered at origin in s-plane
(c) lie on the left half of s-plane.
(d) lie on the right half of s-plane.
1
Mizoram PSC IOLM-2010, Paper-II fS =
UPPCL AE-05.11.2019 2π LCS

Analog Electronics 408 YCT

 1 Ans. (c) : In a radio transmitter, the frequency of the
fS =
C C crystal oscillator will be stable for a long time if the
2π L P S
C P + CS quality factor of the crystal resonator is. > 1000

fP > fs or ωp>ωs 84. In phase-shift oscillator, a single RC network

introduces a phase change of
ωs is very close but less than ωp
(a) 360º
82. A Hartley oscillator uses L1 =2 mH and L2 = 1.5
(b) 180º
mH. The range of capacitance so that the
(c) 90º
frequency of oscillation can be varied between
1000 kHz to 2000 kHz are (d) 60º
(a) C max = 7.2pF and C min = 1.8pF UKPSC Assistant Radio Officer Screening Exam.-2011

(b) C max = 9.2pF and C min = 0.8pF SRC

Ans. (d) : Consider a RC Network H(s) =
1 + SCR
(c) C max = 7.2pF and C min = 0.8pF
π
(d) C max = 9.2pF and C min = 1.8pF ∠H(jω) = − tan −1 ( ωRC )
2
ESE-2021
π
Ans.(a) : Given that Maximum phase shift will be . If RC = 0.
2
L1 = 2mH
But this is not possible because in circuit component
L2 = 1.5mH
will take finite value, that's why phase shift by 1 section
LT = L1 + L2
π
= 2 + 1.5 less than for typically 60º.
2
LT = 3.5 mH
85. Which of the following oscillators uses a
fmin = 1000 kHz capacitive voltage divider to provide feedback?
fmax = 2000 kHz (a) Colpitts
A Hartley oscillator (b) Multivibrator
1 (c) Hartley
f=
2 π LT C (d) RC phase shift
1 RRB JE-01.09.2019, 3:00 PM – 5:00 PM
C=
( 2 πf )
2
LT Ans. (a) : Colpitts uses two capacitors and placed
1 across a common inductor L and the center of the two
C max = capacitors is tapped. The tank circuit is made up of C1,
( 2 × 3.14 ×1000 ×10 ) 3 2
× 3.5 × 10−3 C2, and L. The frequency of oscillations is determined
1 by the values of C1, C2 and L and given by-
C max =
39.4384 × 1012 × 3.5 × 10−3
Cmax = 0.0072×10-9
Cmax = 7.2 pF
1
C min =
( 2 × 3.14 × 2000 × 103 ) × 3.5 × 10−3
2

1
C min =
157.75 × 1012 × 3.5 × 10−3
= 0.0018×10-9
Cmin = 1.8 pF.
83. In a radio transmitter, the frequency of the
crystal oscillator will be stable for a long time if
the quality factor of the crystal resonator is
(a) >100 (b) >500
• The colpitts oscillator uses a capacitive voltage
(c) > 1000 (d) > 20000
divider network as its feedback source.
BSNL (JTO)-2006
Analog Electronics 409 YCT
 Ans. (b) :
(viii) Operational Amplifiers and
Their Applications
1. In sample and hold circuit, op-amp is
connected as :
(a) Unity gain inverting voltage amplifier V0 ( s ) − Zf − ( R 2 || X C )
= =
(b) Unity gain non inverting voltage amplifier Vi ( s ) Z1 R1 + X L
(c) Unity gain inverting current amplifier
1
(d) Unity gain non inverting current amplifier (a) at f = 0, X C = = ∞ → C is open circuit
2πf C
BPSC Asstt. Prof.-12.04.2022
X L = 2πf C = 0 → L is short circuit
APPSC Poly. Lect. 15.03.2020
Nagaland PSC (Degree) 2018, Paper-II V0 ( s ) = −R 2
Nagaland PSC CTSE (Degree) 2017, Paper-II Vi ( s ) R1
GATE-2000 For small f, X C → very large, X L → very small
Ans. (b) : In sample and hold circuit, op-amp is V0 ( s ) ( R 2 || very large ) −R 2
= ≅
connected as unity gain non-inverting voltage amplifier. Vi ( s ) ( R 1 + very small ) R1
2. A circuit using an operational Amplifier shown This circuit is going to be passing zero freq. as well as
below has low freq.
(b) as frequency increases–
f ↑ ( high frequency ) : X C ↓ ( X C < R 2 ) X L ↑ ( X L > R1 )
V0 ( s ) − ( R 2 || very small ) very small X C
= =
Vi ( s ) R 1 + very large very large X L
= very small ≅ 0
(a) Voltage series feedback • For High frequency gain is zero.
(b) Voltage shunt feedback −R 2
• For the Low frequency zero frequency gain is
(c) Current shunt feedback R1
(d) Current series feedback • This circuit is going to be acting as low pass filter.
BPSC Asst. Prof. - 12.04.2022 4. Which one of the following statements
TNPSC AE- 2019 regarding slew rate is correct?
(a) It signifies how rapidly the output of an op-
IES - 2004 amp can change in response to changes in the
Ans. (b) : Voltage shunt feedback- It is also known as frequency of the input signal
shunt-driven shunt-fed feedback i.e. it is parallel- (b) It does not change with change in voltage
parallel prototype. Here, a small portion of the output gain
voltage is coupled back to the input voltage parallel (c) It should be smaller for high speed op-amp
applications
(shunt).
(d) It is not fixed for an op-amp
A shunt feedback always decreases input and output UPRVUNL AE -19.07.2021, Shift-II
impedance. IES-2020, 2016
3. The op-amp circuit shown below represents a Ans. (a) : Op-amp slew rate - The slew rate of an op-
amp or any amplifier circuit is the rate of change in the
output voltage caused by a step change on the input.
Unit of slew rate = V/µs or V/ms

(a) High pass filter (b) Low pass filter

(c) Band pass filter (d) Band reject filter Note - Generally slew rate have 10 V/µs
BPSC Asst. Prof. - 12.04.2022 dV
Slew rate = o V/µsec
GATE-2008 dt

Analog Electronics 410 YCT

5. An op-amplifier based zero crossing detector Ans. (a) : For general inverting summing amplifier,
converts sinusoidal waveform into a, R
(a) Triangular waveform (b) Impulse train VO = − f ( V1 + V2 + V3 ) …(i)
R
(c) Square waveform (d) Cosine waveform
Given,
RPSC ACF & FRO 23.02.2021
Ans. (c) : If reference voltage VR is set equal to zero the ( V + V2 + V3 )
VO = − 1 …(ii)
output will respond almost discontinuously every time 3
the input passing through zero Such an arrangement is Comparing equation (i) & (ii)
called a zero-crossing detector and it convert sinusoidal Rf 1
waveform into a square waveform. =
R 3
6. The circuit shown below acts as a
⇒ R = 3R f
9.
If an averaging amplifier has five inputs; the
ratio Rf/Ri must be:
(a) 0.2 (b) 5
(c) 2 (d) 0.1
UPRVUNL AE -19.07.2021, Shift-II
(a) Summing Integrator Ans. (a) : Average amplifier is also known as summing
amplifier.
(b) Summing Differentiator
(c) Antilogarithmic Amplifier V + V2 + V3 + V4 + V5
V0 = 1 .............(i)
(d) Logarithmic Amplifier 5
RPSC ACF & FRO 23.02.2021 R
VO = − f ( V1 + V2 + V3 + V4 + V5 ) ..............(ii)
Ans. (a) : Summing Integrator R
Comparison equation (i) and (ii)
1 Rf
= = 0.2 (consider only magnitude)
5 Ri
10. What is CMRR, if Ad = 30 dB and Ac = 2 dB?
(a) 26 dB (b) 28 dB
(c) 32 dB (d) 20 dB
1  V1 V2 V3  UPRVUNL AE -19.07.2021, Shift-II
V0 = − ∫ + +  dt
C  R1 R 2 R 3  Ans. (b) :Given,
R 1 = R2 = R3 = R Ad = 30dB, Ac =2dB
1 A 
V0 = − ∫ ( V1 + V2 + V3 ) dt CMRR = 20 log  d 
RC  Ac 
7.
( )
If we apply square wave to input to an ideal CMRR dB = 30 − 2 = 28dB
integrator, then the output is:
(a) square wave (b) triangular wave 11. The following figure is a circuit diagram
(c) cosine wave (d) sine wave of .
UPRVUNL AE -19.07.2021, Shift-II
IES-2003
Ans. (b) : Output of Ideal integrator is
1
Vi ( t ) dt
RC ∫
V0 = −
∴ Output = Integration of input (a) comparator
Given input = Square wave (b) difference amplifier
Output = Integration of square wave (c) voltage follower
= Triangular wave (d) inverting amplifier
UPRVUNL AE -19.07.2021, Shift-II
8. For a three-input inverting summing amplifier,
(V + V2 + V3 ) Ans. (c)
Vout = − 1 , what is the relation
3
between Rf and R?
(a) R = 3Rf (b) Rf = 0.3R
(c) R = 0.3Rf (d) Rf = 3R
UPRVUNL AE -19.07.2021, Shift-II
Analog Electronics 411 YCT
 V+ = Vin V– = Vout 16. If an op-amp comparator has a gain of 100,
Due to virtual short, 000, an input difference of 0.2 m V above
V+ = V– reference, and a supply of ±12 V. the output
∴ Vin = Vout will be:
Output voltage follows the input voltage (a) 15 V (b) 12 V
∴ voltage follower (c) 20 V (d) 10 V
12. Decreasing the gain in the op-amp non- UPRVUNL AE -19.07.2021, Shift-II
inverting amplifier circuit could be achieved Ans. (b) : In an op-amp comparator.
by: It i/p difference voltage is +ve and above reference then
(a) increasing the value of the feedback resistor o/p voltage is +ve supply i.e 12 V.
(b) removing the feedback resistor It i/p difference voltage is –ve and above reference then
(c) increasing the value of the input resistor o/p voltage is –ve supply i.e –12V.
(d) reducing the amplitude of the input voltage
UPRVUNL AE -19.07.2021, Shift-II 17. An operational amplifier possesses
(a) Very large input resistance and very large
Ans. (c) : Gain of non- inverting op-amp can be
decreased by the increasing the input resistance. output resistance
(b) Very large input resistance and very small
 R  output resistance
Gain = 1 + f 
 Ri  (c) Very small input resistance and very small
13. For the given circuit, if R1 = R2, then voltage output resistance
gain will be . (d) Very small input resistance and very large
output resistance
APPSC Poly. Lect. 14.03.2020
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
IES-2020, 2019, 2015, 2002, 1992
(a) very small (b) – 1 OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
(c) 10 (d) 1 Mizoram PSC IOLM -2018, Paper II
UPRVUNL AE -19.07.2021, Shift-II GPSC Asstt. Prof. 11.04.2017
Ans. (b) : Given circuit is a inverting amplifier Nagaland PSC CTSE (Diploma)-2017, Paper-I
V R CGPSC SO 14.02.2016
gain = 0 = − 2
Vin R1 BEL-2015
R2 = R1 TSPSC Manager (Engg.) - 2015
Gain = –1 TNPSC AE-2014
14. If we apply square wave to an ideal MPPSC Forest Service Exam.-2014
differentiator, then we get _______ as its SAIL-2014
output. ISRO Scientist Engg.2009, 2007
(a) train of impulses (b) cosine GATE-2001
(c) ramp (d) negative cosine
Ans. (b) : Op-Amp characteristics -
UPRVUNL AE -19.07.2021, Shift-II
• Open loop gain (ACL) = ∞ → very high
Ans. (a) : If we apply square wave to an ideal
differentiator we get train of impulses as its output. • Input resistance (Ri) = ∞ → very high
differentiation • Output resistance (R0) = 0 → very small
step function  → impulse .
• Bandwidth (BW) = ∞ → very high
15. If the gain Acl of an inverting amplifier is 4.9, • CMRR = ∞ → very high
with an input resistor value of 2.2 kΩ, what • Slew rate = ∞ → very high
value of feedback resistor is necessary?
• Offset voltage = 0 → very low.
(a) 2.4 kΩ (b) 10.78 Ω
(c) 107.8 kΩ (d) 10.78 kΩ
UPRVUNL AE -19.07.2021, Shift-II
−R f
Ans. (d) : Gain in inverting amplifier, A CL =
Ri
Rf = –ACL Ri
Rf = 4.9×2.2k
R f = 10.78 kΩ

Analog Electronics 412 YCT

Function diagram of op-amp - Nagaland PSC CTSE (Degree)-2017, Paper-II
GPSC Asstt. Prof. 11.04.2017
GATE-2004
Ans. (b) : For an ideal op-amp.
Vout = A × Vi
So it is a voltage controlled voltage source.
The ideal op-Amp has following characteristics
• Input impedance = infinity
• Output impedance (open loop) = 0
18. In the differential amplifier shown in the • Common-mode voltage gain = 0
figure, the magnitudes of the common-mode
• Vout = 0 when both inputs are at the same voltage
and differential-mode gains are Acm and Ad'
respectively. If the resistance RE increased, (zero "offset voltage")
then • Output can change instantaneously (infinite slew
rate)
• The purpose of bias current is to achieve the ideal
behavior in Op-Amp which has high CMRR, high
differential gain and high input impedance.
20. The inverting op-amp shown in the figure has
an open-loop gain of 100. The closed-loop gain
V0/Vs is

(a) Acm increase

(b) Common-mode rejection ratio increases
(c) Ad increase (a) –8 (b) –9
(d) Common-mode rejection ratio decreases (c) –10 (d) –11
Nagaland PSC CTSE (Degree)-2018, Paper-II APPSC Poly. Lect. 14.03.2020
GPSC Asstt. Prof. 11.04.2017 CGPSC SO 14.02.2016
Nagaland PSC CTSE (Degree)-2017, Paper-II BPSC Poly. Lect.2014, GATE-2001
Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (b) : Given open loop gain = 100
Nagaland PSC CTSE (Degree)-2015, Paper-II
GATE-2014, 2005 Then, V0 = A oL ( V+ − V− )
TNPSC AE-2013 V0 = 100 ( 0 − V− ) = −100V− ………….(i)
IES-2012 Apply super position at inverting terminal-
TRB Poly. Lect. -2012
V− = (Due to Vs only) V o =0 + (Due to Vo only) V s =0
Ans. (b) :
 –g R   10   1 
V− =   Vs + Vo  
Ad  m c
  10 + 1   10 + 1 
CMRR = =  –R c  = 2g R
A cm  2R 
m E From equation (i)

E
 −Vo 10Vs Vo
= +
100 11 11
−R C
A cm =  111 
2R E − Vo   = 10Vs
 100 
As R E ↑→ A d ↑→ A c ↓→ CMRR ↑
V −1000
When RE is increased then Acm is decreased and CMRR A CL = o = −9
increases. Vs 111
19. The ideal op-amp is an ideal Hence, closed loop gain = –9
(a) Voltage controlled current source 21. If the input to the circuit of figure is a sine
(b) Voltage controlled voltage source wave the output will be
(c) Current controlled current source
(d) Current controlled
Nagaland PSC CTSE (Diploma)-2018, Paper-I
Mizoram PSC IOLM -2018, Paper II
Analog Electronics 413 YCT
 (a) A half-wave rectified sine wave
A 
(b) A full-wave rectified sine wave CMRR = 20log  d 
(c) A triangular wave  Ac 
(d) A square wave CMRR = 20log A d − 20log A c
RPSC VP/Suptd. ITI-05.11.2019 = 48 − 2
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I CMRR = 46 dB
BPSC Polytechnic Lecturer-2014 23. If a differential amplifier has a gain of 20,000
ISRO Scientist Engg.2010 and CMRR = 80 dB, its common mode gain is:
Ans. (d) : (a) 2 (b) 1
(c) 1/2 (d) 0
TNPSC AE - 2018
Mizoram PSC Jr. Grade-2015, Paper-II
IES-2013, 1992, ISRO Scientist Engg.-2007
Ans. (a) :
Q Op-amp open loop without feedback, it work as Solution –
comparator.
A 
Q CMRR = 20log  d 
 Ac 
Given value - A d = 20000
CMRR = 80dB
A 
CMRR = 20 log  d 
Ideal case,  Ac 
A OL = ∞, R i = ∞, R o = 0 20000
80 = 20log
Ac
Vo = ± VSat
20000
Vo = A OL ( Vid ) 4 = log
Ac
Vo = A OL ( V+ − V− ) = A OL ( V2 − V1 ) 20000
104 =
If V2 > V1 then, Vo = + Vsat. Ac
And V2 < V1 then, Vo = −Vsat . 20000
Ac =
Represented graph, square wave, 10000
Ac = 2
24. The large signal bandwidth of an op-amp is
limited by
(a) Its slew rate specification
(b) Its Gain-bandwidth product
(c) CMRR
(d) None of these
Nagaland PSC 2018 Diploma paper -II
22. If the differential voltage gain and the common Nagaland PSC CTSE (Diploma)-2018, Paper-I
mode voltage gain of a differential amplifier Punjab PSC Poly. Lect. 20.08.2017
are 48 dB and 2 dB respectively, then its
IES-2015
common mode rejection ratio is
(a) 23 dB (b) 25 dB Ans. (a) : The large signal bandwidth of op-amp is
limited by slew rate because
(c) 46 dB (d) 50 dB
GPSC Asstt. Prof. 11.04.2017  dV 
slew rate =   = 2πVm f V/µsec
Mizoram PSC IOLM -2018, Paper II  dt  m
Punjab PSC Poly. Lect. 20.08.2017 25. An OP-AMP has a slew rate of 5V/µs. The
GATE-2003 largest sine wave O/P voltage possible at a
Ans. (c) : Given value– frequency of 1MHz is
Differential voltage gain Ad = 48 dB. (a) 10π volts (b) 5 volts
Common mode voltage gain Ac = 2dB 5
(c) volts (d) 5/2π volts
Find out value-CMRR = ? π
A TNPSC AE-2019
CMRR = d Kerala PSC Lecturer (NCA) 04.07.2017
Ac Mizoram PSC Jr. Grade-2015, Paper-II
Analog Electronics 414 YCT
Ans. (d) : Slew rate = 2πf m Vm = 0.04 sec.
1
5 × 10 = 2π × 10 Vm
6 6
Q Feedback frequency f =
τ
5
Vm = f=
1
= 25Hz .....(ii)
2π 0.04
26. Compare to equation (i) and (ii),
Source frequency > feedback frequency
Since capacitor becomes short circuit. So, output
voltage is equal to voltage at inverting and non-
inverting terminal of op-amp.
Therefore, Output signal V0 = 1 Vrms
28. A high gain OpAmp has Rf = 105 Ω & Ri =103
Ω. The correct statements is :
(a) The non-inverting gain & inverting gain are
nearly same.
(b) The inverting gain is very much higher than
In the circuit shown in the above figure, the non-inverting gain
value of output V0 is (c) The non-inverting gain is very much higher
(a) +6V (b) –9V than inverting gain
(c) –6V (d) +9V (d) The inverting & non-inverting gains are
ISRO Scientist Engg. 2009 unrelated
Ans. (b) : According to circuit diagram ISRO Scientist Engg.-2012
Q op-amp as an adder Ans. (a) : Given, Rf = 105Ω, Ri = 103Ω
R R R  Q for inverting terminal
V0 = − IR f = −  f × V1 + f × V2 + f × V3  −R f −105
 R1 R2 R3  ∴ V0 = = = −100 …………….(i)
Q Given value, Ri 103
V1 = 1, V2 = 2, V3 = 3
R 1 = 40kΩ, R 2 = 80kΩ, R 3 = 120kΩ
R f = 120kΩ
120 120 120 
V0 = −  ×1 + ×2+ ×3
 40 80 120 
V0 = –[3+3+3]
V0 = −9V
27. What is the output signal level of following
circuit? And non inverting terminal,
 R  105
V0 = 1 + f  = 1 + 3
 Ri  10
= 1 + 100 = 101 …………………………..(ii)
So, from equation (i) and (ii), magnitude are nearly
same.
29. Determine output voltage 'V0' for below circuit
where Vin=Sin(100πt)

(a) ∼5 Vrms (b) ∼1 Vrms

(c) ∼4 Vrms (d) ∼0.1 Vrms
ISRO Scientist Engg.-2014
Ans. (b) : Given,
Source frequency (fs) = 200kHz...(i)
Feedback capacitor Cf = 1µF=10–6 farad,
Feedback resistance Rf = 40kΩ = 40 ×103Ω (a) 2 sin (100πt) (b) sin (100 πt)
Time constant τ = RC (c) sin (200πt) (d) 0.5 sin (100πt)
= 10–6×40×103 ISRO Scientist Engg.-2018

Analog Electronics 415 YCT

Ans.(a) Ans. (c) : Q Maximum rate of change in output with
respect to time,
dV0
Slew rate = = 5V / µs
dt max
Q Given output = 1V peak = Vp

So, Slew rate = ( Vp ) × 2πf m =

dV0
dt
5 × 10 +6 = 1 × 2 × 3.14 × f m
Q op-amp output voltage
−1 5 × 106
RC ∫
V0A = Vi dt fm = = 0.79617 ×106
6.28
−1 f m = 796.18kHz
sin (100πt )
100 × 10−12 ∫
=
32. For the circuit given below, the voltage V0
1  −1 
=− −12 
× cos (100π ) t  across the op-amp output is :
100 × 10 100π 
1
V0A = cos (100π ) t
100 × 10−12 × 100π
d
V0 = − RC ( V0A )
dt
d 1 
= −200 × 10−12  −12
cos (100π ) t 
dt 100 × 10 × 100π 
(a) –9Vi (b) –3Vi
−200 × 10−12
=  − sin (100π ) t.100π  (c) –11Vi (d) 9Vi
100 × 10−12 × 100π  ISRO Scientist Engg.-2013
= −2  − sin (100π ) t  Ans. (c) :
V0 = 2sin (100π ) t
30. The circuit is with an ideal operational
amplifier with ±10 V supply. The output
voltage is:

Q ( − ve ) negative feedback, VA = 0
(a) –200 mV (b) –400 mV So, nodal analysis at point A,
(c) –600 mV (d) –300 mV VA − Vi VA − VB
+ =0
ISRO Scientist Engg. -2015 10 50
Ans. (b) : Given, Ideal op-amp, AOL= ∞, Vid = 0 , V = −5V …………………………..(i)
B i
V− = V+ virtual ground And nodal analysis at point B,
Applying KCL at inverting terminal of op-amp, VB − V0 VB VB − VA
+ + =0
20 − 0 40 − 0 0 − Vo 10 10 50
+ =
1 2 10 5 ( VB − V0 ) + 5VB + VB − VA = 0
−Vo
20 + 20 = 11VB = 5V0
10
Vo = –400 mV 5
VB = V0 …………………..(ii)
31. Output of an Op-amp is 1V peak, and slew rate 11
is 5V/µs. The maximum frequency of input From equation (i) and (ii)
sinusoidal signal that can be reproduced is : 5
(a) 398 Hz (b) 796 Hz V0 = −5Vi
11
(c) 796 kHz (d) 398 kHz
V0 = −11Vi
ISRO Scientist Engg.-2013
Analog Electronics 416 YCT
33. Given the output for the following non- (a) 2 VS (b) –2VS
inverting summing amplifier, the relation (c) 3VS (d) –3VS
between Rf and R in the circuit is : Nagaland PSC CTSE (Degree)-2016, Paper-II
ISRO Scientist Engg.-2007
Ans. (c) :

By virtual concept:- V+ = V−
(a) Rf = R (b) Rf = 4R
(c) Rf = 2R (d) Rf = R/2 Apply KCL at virtual node:-
ISRO Scientist Engg.-2013 VS VS − V0
+ =0
Ans. (a) : R 2R
2VS + VS – V0 = 0
3Vs − V0 = 0
V0 = 3Vs
35. The value of C required for sinusoidal
oscillation of frequency = 2 kHz in the given
circuit is

Q Nodal analysis at node A,

VA − V1 VA − V2 VA − V3 VA − V4
+ + + =0
R R R R
V1 + V2 + V3 + V4 4VA
=
R R (a) 1/(2π) µF (b) 1/ (4π) µF
And nodal analysis at node B, (c) 1/π µF (d) None of these
VR ISRO Scientist Engg. -2020
VB = 0
R + Rf Ans. (d) :
Q Ideal op-amp
VA = VB Virtual ground
V1 + V2 + V3 + V4 4V0
So, =
R R + Rf
 V1 + V2 + V3 + V4 
Q Given V0 = 
 2 
2V0 4V0 Given, Rf = 1.9 kΩ, Ri = 1 kΩ
= Condition – Wein bridge circuit must be equal to or
R R + Rf
greater than 3, for sinusoidal oscillation.
1 2 Av ≥ 3
=
R R + Rf
V0 R 1.9
R + R f = 2R ∴ = 1+ f = 1+ (non-inverting terminal)
Vin Ri 1
Rf = R
Vout
34. In the ideal Op-amp circuit shown, V0 is = 2.9
Vin
Therefore, voltage gain less than 3. So, it does not
satisfy the above condition
36. In order to ensure that the output voltage of an
op-amp is zero, when both its inputs are
grounded
Analog Electronics 417 YCT
 (a) Internal negative feedback is used In negative half cycle Z1 will be open and Z2 will be
(b) An external offset balancing circuit is used at short.
the input terminals Therefore, the output of the circuit is same as input and
(c) The currents incident at the output node are inverted.
carefully designed 38. Assume that Vi = 2V; R3 = 10Ω; β of Q1 = 50;
(d) The totem-pole output transistors are VCC = 15V. Find Iout
designed to have exactly equal cut in voltages
ISRO Scientist Engg. -2020
Ans. (b) : Given,
Q Output voltage of an op-amp V0 = 0
And both inputs are grounded,

(a) 3.92 mA (b) 4mA

(c) 6.84 mA (d) 2.8 mA
ISRO Scientist Engg.-2010
In case of when op-amp both inputs voltage, V1 and Ans. (a) : Given,
V2 equal then the voltage V0 = 0. VCC = 15 V
An external offset balancing circuit is used at the Vi = 2V
input terminals. R3 = 10Ω
37. What is the output waveform V0 for a β = 50
sinusoidal input of peak-peak amplitude of 4V.
Assume that Z1 and Z2 are two identical Zener
diodes of 4.7V, and R1=10 kΩ and R2= 20kΩ c

(a) Same as input

(b) Sinusoidal waveform with 5.4V peak
(c) Sinusoidal waveform clamped to +/-4.7V
(d) Sinusoidal waveform clamped to +/-5.4V Vi
IE =
ISRO Scientist Engg.-2010 R3
Ans. (a) : 2
IE = = 0.2A
10
I E = I B (1 + β)
0.2
IB =
51
I B = 3.921mA (Q I B = Iout )
39. In an inverting OP-AMP, the input bias
current is -1µA, and the input and the feedback
resistances are both 1 MΩ. What will be the
Given, output voltage for an input voltage of 2.5V?
V0 for a sinusoidal input of peak –peak amplitude = 4V (a) –2.5 V (b) –3.0V
R1 = 10kΩ (c) –3.5V (d) 4.0V
R2 = 20 kΩ ISRO Scientist Engg.-2010
And Z1 and Z2 are two identical zener diode voltage Ans. (c) : Given, Vi = 2.5V
= 4.7V
−R f
In positive half cycle one zener diode Z1 will be forward V0 = Vin + Ib R f
bias that is short and Z2 will be open and, Ri

Analog Electronics 418 YCT

 −1 ×106 42.
If d.c. supply of 10V is fed to a differentiating
V0 = × 2.5 + (−1× 10−6 × 106 × 1) circuit, then output will be______
106 (a) 20V (b) 10V
V0 = −2.5 − 1 (c) 0V (d) None of the above
V0 = −3.5V Nagaland PSC (CTSE) Diploma-2017, Paper II
40. What would be the output of the following Ans. (c) :
circuit, if a positive going unipolar pulse with
an amplitude greater than Vref, is applied at the
input?

dVi
V0 ( t ) = −RC
(a) Vo will go high momentarily and return to dt
low if d.c. supply of 10V.
(b) Vo will go low momentarily and return to d
Then V0 (t) = − RC (10 )
high dt
(c) Vo will go high and remain high = 0V
(d) Vo will not change its previous state 43. What is PSRR value of an ideal op-amp?
ISRO Scientist Engg.-2010 (a) Zero (b) Unity
Ans. (c) : (c) Infinite (d) Unpredictable
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (a) : If the supply of an op-amp changes, its output
should not, but it typically does. If supply voltage
change X volt and output change Y volt then
X
PSRR =
Y
The dimensionless ratio is generally called the power
When Vin is applied at positive terminal diode will be supply rejection ratio (PSRR). An ideal value of PSRR
forward bias and Vin > Vref (D1 as a shorted) in op-amp is zero.
Then, Vo will go high and remain high. 44. In differential-mode,………….
(a) Opposite polarity signals are applied to the
41. If the input to a differentiating circuit is a saw-
inputs
tooth wave, then output will be______
(b) The gain is one
(a) Square (b) Triangular
(c) The outputs are of different amplitudes
(c) Sine (d) Rectangular
(d) Only one supply voltage is used
Nagaland PSC (CTSE) Diploma-2017, Paper II
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (d) : Ans. (a) : In differential mode opposite polarity signals
are applied to the inputs.
45. The output of a particular Op-amp increases 8
V in 12 µs. The slew rate is……….
(a) 90 V/µs (b) 0.67 V/µs
(c) 1.5 V/µs (d) None of these
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (b) : Given,
dV ( t ) V = 8volt, t = 12µsec
V0 ( t ) = −RC  dV 
dt Slew Rate =  
The output of the circuit depends on the differentiation  dt  m
of the input voltage. 8 2
If we give a sawtooth wave as input (Vi) to this circuit it SR = = V / µs
12 3
will give a rectangular wave as output after
differentiating the input. SR = 0.67 V / µs

Analog Electronics 419 YCT

46. The input impedance of a differential amplifier Ans. (d) : The output of an ideal differential amplifier,
equals re' times……… when same input signals are applied at input will be
zero, because difference of input will zero.
(a) β (b) RE
(c) RC (d) 2β 51. What is the feedback factor of the circuit
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (d) : Differential input resistance is define as the
equivalent resistance that would to measured at either
terminal with the other terminal grounded.
Ri = 2β
47. A common-mode signal is applied to………
(a) the non inverting input
(b) the inverting input
(c) both inputs 9 9
(a) (b)
(d) top of the tail resistor 100 10
Nagaland PSC (CTSE) Diploma-2017, Paper II 1 1
(c) (d)
Mizoram PSC AE/SDO-2012, Paper-I 9 100
Ans. (c) : As the common mode is known when both TNPSC AE - 2018
signals are same and it is applied to both input 1
terminals. If the transistor are perfectly matched the Ans. (d) : Feedback factor β =
output will be zero otherwise there exists some output R1 + R 2
voltage. In an ideal op-amp the voltage gain for the R 1 & R 2 = Feedback resistor.
common mode signal is zero. 1
β=
48. The common-mode voltage gain is…….. 10 + 90
(a) smaller than differential voltage gain
1
(b) equal to differential voltage gain β=
(c) greater than differential voltage gain 100
(d) none of the above 52. The low frequency gain of LPF shown is
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (a) : We know that-
DifferentialGain
CMRR =
Common modeGain
CMRR > 1
Ad
>1 (a) 10 dB (b) 20 dB
Ac
(c) 30 dB (d) 40 dB
Ad > A c TNPSC AE - 2018
49. The input stage of an Op-amp is usually a…….. Ans. (d) : At low frequency f = 0 and Xc = ∞
(a) differential amplifier V
Gain = o = 100
(b) class B push-pull amplifier Vi
(c) CE amplifier
(d) swamped amplifier V
For Low frequency ⇒ Gain = 20log o = 20log100
Nagaland PSC (CTSE) Diploma-2017, Paper II Vi
Ans. (a) : The op-amp has two input terminals. The = 20 × 2
input voltage given to both the input terminals. The
Gain = 40 dB
differences of the input voltage will be amplified.
Therefore the input stage of an op-amp is usually a 53. The circuit shown in figure is a
differential amplifier.
50. The output of an ideal differential amplifier,
when same input signals are applied at the
inputs is
(a) Dependent on its CMRR
(b) Dependent on its voltage gain (a) Low-pass filter (b) High-pass filter
(c) Determined by its symmetry (c) Band-pass filter (d) Band-reject filter
(d) Zero RPSC ACF & FRO-23.02.2021
TNPSC AE - 2018 ISRO Scientist Engg.-2008
Analog Electronics 420 YCT
Ans. (a) : The circuit shown in figure is a second order Ans. (c) :
low pass filter.
• At low frequencies (s → 0) capacitor act as open
circuit.
1 1
Q XC = =
jωC sC
1
XC =
sC When Vs is -1 volt then diode will be off
XC = ∞
Apply KCL at node A,
• At high frequencies capacitor act as short circuit
VS − 0 0 − V01
1 =
Q XC = 1 1
jωC
−1 = −V01
1
XC = =0
∞×C V01 = 1 V
The circuit represent → Low pass filter. When VS = + 1 volt then diode will on
54. The OP-AMP integrator circuit contains
(a) Resistor in the feedback path
(b) Capacitor in the feedback path
(c) Inductor in the feedback path
(d) Short circuit in the feedback path
GPSC Asstt. Prof. 11.04.2017
Ans. (b) : The OP-AMP integrator circuit contains Apply KCL at node A,
capacitor in the feedback path.
1 − 0 0 − V02
= ⇒ V02 = −0.5V
1 0.5
V01 + V02 = 1 − 0.5 = 0.5V
57. In the circuit shown below the op-amp is ideal.
Ideal integrator act as a low pass filter. The voltage gain V0/Vi is
55. Which converters uses integrating Op-amp
(a) Dual slope A/D converter
(b) Parallel A/D converter
(c) Single slope A/D converter
(d) None of these
Mizoram PSC IOLM -2018, Paper II
(a) –2 (b) 2
Ans. (a) : A dual slope A/D converter produce an
equivalent digital output for a corresponding analog (c) –1 (d) 1
input. It uses a integrator clock generator, control logic UPPCL AE- 31.12.2018
and a counter. Ans. (a) : From Virtual ground concept – at terminal of
56. In the circuit shown below assume that diodes op-amp voltage will be zero.
and op-amp are ideal. Suppose that V01 is the
output voltage when input voltage is Vs = –1.0
V and V02 is the output voltage when input
voltage is Vs = +1.0 V, then the value of V01 +
V02 is

Apply virtual ground equation

Vi − 0 0 − Vo
=
1 2
Vo
= −2
Vi
(a) 2.0 V (b) –0.5 V 58. Assume that op-amp in the circuit shown below
(c) 0.5 V (d) 0.0 V is ideal. Value of the transfer function
UPPCL AE- 31.12.2018 V2(s)/V1(s) evaluated at s = j is
Analog Electronics 421 YCT
 On putting s = j
( )
2V1 ( s ) = V2 ( s )  2 −1 + 2 2 j + 2 − 2 2j − 2 
 
= V2 ( s )  −2 + 4 2 j + 4 − 2 2 j − 2 

2V1 ( s ) = V2 ( s )  −4 + 4 + 2 2 j

2V1 ( s ) = 2 2 jV2 ( s )

(a) −1 (b) − j V2 ( s ) 1 j −j
= × =
2 2 V1 ( s ) 2j j 2
(c) j (d) 1
2 2 V2 ( s )
= − j/ 2
UPPCL AE- 31.12.2018 V1 ( s )
Ans. (b) : Draw circuit in s-domain– 59. The input impedance and voltage gain of the
given circuit in figure below is-

KCL apply at node (3), (a) 2 kΩ, 2 (b) 2 kΩ, 1

V1 ( s ) − V3 V3 − V2 ( s ) V3 − V2 ( s ) (c) 1/2kΩ, 2 (d) 1kΩ, 1
= + UPPCL AE-16.11.2013
1/ 2 1/ C1s 1/ 2
Ans. (d) :
2 ( V1 ( s ) ) − 2V3 = C1sV3 − C1sV2 ( s ) + 2V3 − 2V2 ( s )
–––––(1)
KCL apply at node (2),
V3 − V2 ( s ) V2 ( s )
=
1/ 2 1/ C 2s
2V3 − 2V2 ( s ) = C 2sV2 ( s )
2V3 = 2V2 ( s ) + C 2sV2 ( s )
In ideal open Av = ∞ ,
sV2 ( s ) + 2V2 ( s )
V3 = ( C2 = 1F ) V+ = V– (virtual ground condition)
2 Apply virtual concept at inverting terminal
From eq. (1) Vin − 0 0 − Vout
=
2V1 ( s ) = 2V3 + C1sV3 − C1sV2 ( s ) + 2V3 − 2V2 ( s ) 1 1
2V1 ( s ) = V3  2 + 2 + C1s  − C1sV2 − 2V2 ( s ) Vout
Vin = −Vout ⇒ = −1
On putting the value of V3 and C1 = 2F Vin
sV2 ( s ) + 2V2 ( s ) and input resistance Ri = 1kΩ
2V1 ( s ) =
2
(2 2 + 2s ) 60. Find output voltage Vo in the circuit below:

−2sV2 ( s ) − 2V2 ( s )
 s + 2  
2V1 ( s ) = V2 ( s ) 
 2 
(
 2 2 + 2s − 2s − 2 )


( )( )
 s + 2 2 2 + s − 2 2s − 2 
= V2 ( s )  
 2  (a) –1.1 V (b) +1.1 V
  (c) 1.0 V (d) 10 V

 (2
)
2V1 ( s ) = V2 ( s )  2 s + 2 2s + 2 − 2 2s − 2 

UKPSC Assistant Radio Officer Screening Exam.-2011
IES-2007
Analog Electronics 422 YCT
Ans. (b) : (a) 0V (b) ∞
(c) 400V (d) ± 400V
TNPSC AE-2008
Ans. (a) : Input offset voltage is the difference in input
voltage that exist between input terminal of an op-amp
without any external input & force the output voltage to
zero.
65. An OP-AMP has a common made gain of 0.01
Applying voltage division rule at point A: and a differential made gain of 105. The value
 100  of the CMRR will be
V1 = 1 mV × 1 +  =11mV (a) 105 (b) 107
 10  –3
(c) 10 (d) 103
Applying voltage division rule at point B:
Mizoram PSC Jr. Grade-2015, Paper-II
 470  MPPSC Forest Service Exam.-2014
V2 = 11 mV ×  −  = −110 mV
 47  Ans. (b) : Given, Ad = 105 , Ac = 0.01
Applying voltage division rule at point C: A
 22  CMRR = d
V0 = −110mV  −  = +1.1V
Ac
 2.2 
105
61. The voltage that is to be applied between the CMRR =
two input terminals for making zero output 0.01
voltage is CMRR = 107
(a) Output offset voltage (b) Threshold voltage 66. An inverting amplifier is made using ideal OP-
(c) Input offset voltage (d) None of the above AMP. Why are the two input terminals of the
TNPSC AE-2014 OP-AMP at the same potential?
Ans. (c) : Input offset voltage is the voltage which must (a) CMRR is infinity
be applied between input terminals to make amplifier (b) The input impedance is infinity
output voltage (V0 = 0). (c) The open loop gain of the OP-AMP is infinity
62. An operation amplifier having a slew rate of (d) Both (CMRR is infinity) and (The input
62.8 v/µsec, is connected in a voltage follower impedance is infinity)
configuration. If the maximum amplitude of Mizoram PSC Jr. Grade-2018, Paper-II
the input sinusoid is 10 V, then the maximum MPPSC Forest Service Exam.-2014
frequency at which the output is undistorted.
(a) 1 MHz (b) 6.28 MHz Ans. (d) : For ideal operational amplifier– R in = ∞
(c) 10 MHz (d) 62.8 MHz and CMRR= ∞ Hence virtual ground concept is
TNPSC AE-2013 applicable which states that same voltage at both
Ans. (a) :Given value, Slew rate = 62.8 V/µsec , terminal of amplifier.
Vm = 10V 67. The slew rate of an operational amplifier is 0.8
∂V0 volts per micro second. What will be the
Slew rate = = 2πfmVm maximum amplitude of undistracted output
∂Vt
sine wave that the OP-AMP can produce at 40
62.8 × 106 = 6.28 × 10 × fm kHz?
f m = 1MHz (a) 3.18 volts (b) 4 volts
63. Op-Amp circuit consists of first two stages, (c) 20 volts (d) 2.54 volts
which are MPPSC Forest Service Exam.-2014
(a) Cascade differential amplifier Ans. (a) : Given value,
(b) Buffer amplifier S.R. = 0.8 V/µ sec f = 40 kHz
(c) Driver S.R. = 2π × f × Vm
(d) Emitter follower
0.8
TNPSC AE-2013 Vm =
Ans. (a) : The Op-Amp circuit consists of two stages 2π × 40kHz ×10−6
which are cascaded differential amplifier. The first stage Vm = 3.18 V
providing high gain and the second stage providing 68. In a log amplifier the input is 'a'. The output
additional voltage gain and large output signal swing. will be proportional to
64. A 741 OP-AMP has an open loop gain 200,000. (a) log a (b) 2.3 log a
The output offset voltage is 2 mV. If the input (c) log 20 a (d) None of these
terminals are shorted, the output voltage is MPPSC Forest Service Exam.-2014

Analog Electronics 423 YCT

Ans. (a) : The logarithm amplifier gives an output Ans. (a) : For Integrated circuit →
voltage which is proportional to the log of applied input −1
voltage,
Vout = log (Vin)
V0 =
RC ∫Vi dt

Vin = a
Vout = log a
69. An inverting operational amplifier has
Rf = 2MΩ and R1 = 2kΩ. Its scale factor is
(symbols/notations carry their usual meaning) If the capacitor in an RC integrator shorts, the output is
(a) 1000 (b) 100 at ground.
(c) -100 (d) -1000 75. The frequency compensation is used in op-amp
RPSC LECTURER-10.01.2016 to increase its
Ans. (d) : Given , Rf = 2MΩ, R1 = 2kΩ (a) Input impedance (b) Output impedance
V0 −2 × 106 (c) Gain (d) Bandwidth
= = −1000 Nagaland PSC CTSE (Diploma)-2018, Paper-I
Vi 2 × 103
GATE-1994
–ve sign indicates polarity of output signal is reversed Ans. (c) : The frequency compensation is used in op-
to that of input signal. amp to increase its gain.
70. Logarithmic amplifiers are used in 76. An op-amp is used as a zero-crossing detector.
(a) Adders (b) Dividers If the maximum output voltage is ± 15 Volt p-p
(c) Multipliers (d) All of the above and the slew rate is 10 V/µsec, then the
Nagaland PSC CTSE (Degree)-2016, Paper-II maximum frequency will be
Ans. (d) : Logarithmic amplifiers are used in adders, (a) 106 Hz (b) 10.6 Hz
multipliers, subtractions. (c) 106 kHz (d) 10.6 kHz
71. The number of operational amplifiers required Nagaland PSC CTSE (Diploma)-2018, Paper-I
to design an electronic PID controller is : Ans. (c) : Given, V0 = 15V,
(a) 1 (b) 2
S.R = 10 V/µsec.
(c) 3 (d) 4
dV0
Nagaland PSC CTSE (Degree)-2016, Paper-II slew rate = = 2πVf V/µsec
dt
Ans. (a) : The no. of op-amp in a PID controller = 1
dV
72. How many stages are involved in bipolar op- = 10V / µ sec
amp? dt
(a) 2 (b) 3 2π f V0 = 10V/µsec
(c) 4 (d) 6 10 × 106
f=
Nagaland PSC CTSE (Diploma)-2017, Paper-I 2π ×15
Ans. (b) : The bipolar op-amp consists of three stages- f = 106 kHz
Input differential amplifier 77. A differentiator circuit is also a
Gain stage (a) High pass circuit (b) Low pass circuit
Output stage (c) Band pass circuit (d) Band reject circuit
73. In op-amps, which type of noise occurs due to Nagaland PSC CTSE (Diploma)-2018, Paper-I
discrete flow of current in the device? Ans. (a) : In electronics, a differentiator is a circuit that
(a) Shot noise (b) Burst noise is designed such that the output of the circuit is
(c) Thermal noise (d) Flicker noise approximately directly proportional to the rate of
Nagaland PSC CTSE (Diploma)-2017, Paper-I change of the input. The differentiator circuit is a high
Ans. (a) : In op-amp, shot noise occurs due to discrete pass filter.
flow of current in the device. 78. An op-amp having a slew-rate specification of 1
74. If the capacitor in an RC integrator shorts, the V/µs has been connected in the voltage follower
output configuration. The input is a unit step of
(a) is at ground voltage applied at instant t = 0. What is the
(b) would measure the same as the input output magnitude at t = 500 ns?
(c) would measure zero volts (a) 1 V (b) 0 V
(d) none of the above (c) 0.5 V (d) 2.5 V
Nagaland PSC CTSE (Diploma)-2018, Paper-I Mizoram PSC Jr. Grade -2018, Paper-II
Analog Electronics 424 YCT
Ans. (c) : Given, Slew rate = 1V/µsec, t= 500ns Ans. (c) : Given data -
 dV  Bandwidth = 1 MHz
S.R. =  o  Closed loop gain ACL = 200 V/mV
 dt  max
BW
1×106 =
dVo ∵ fC =
500 × 10−9 A CL
( Vo )m = 1× 500 × 10−3 ∴ Put the value, the cut off frequency
( Vo )m = 0.5Volt 1×106
fC =
200 × 103
79. In an op-amp, when the input signal drives the
= 5 Hz
output at a rate of voltage change greater than
the slew rate, then the resulting signal 84. If the bias current in the IC-741 op-amp is IQ =
(a) is enhanced 19 µA and the internal frequency compensation
(b) is clipped capacitor C1 = 30pF, the slew rate of the op-
(c) is unaffected amp will be nearly
(d) remains the same, but with 900 phase (a) 1.58 V/µs (b) 1.26 V/µs
difference (c) 0.93 V/µs (d) 0.63 V/µs
Mizoram PSC IOLM-2010, Paper-I IES-2020
Ans. (a) : In an op-amp, when the input signal drives Ans. (d) :
the output at the rate of voltage change greater than dV I
slew rate, the resulting output signal will increase it Slew rate S = 0 = 2πf m Vm =
width. Hence signal is enhanced. dt C
I
80. In ideal op-amp the current through the virtual S=
ground is C
(a) 1 A (b) 10 A ∵ Given value -
(c) Zero (d) infinity IC - 741 op-amp is IQ = 19µA
RPCS Lect.-2011 Internal frequency compensation capacitor C1 = 30 pF
Ans. (c) : In op-amps the term virtual ground means 19 ×10−6
that the voltage at that particular node is almost equal to ∴ S=
ground voltage zero. 30 ×10−12
It is not physically connected to ground. So, in ideal op- = 0.633 × 106 V / s
amp the current through the virtual ground is zero. = 0.63 V/µs
81. An operational amplifier is a 85. In a differential amplifier, there are two sets of
(a) high gain CE amplifier input signals. In first set, V1 = +50 µV and V2 =
(b) cascaded CE amplifier –50µV. and in second set V1 = 1050 µV and V2
(c) high gain direct coupled amplifier = 950 µV. If the common mode rejection ratio
(d) high gain CB amplifier is 100, the percentage difference in the output
RPSC Vice Principal ITI-2016 voltage for the two sets of input signals will be
Ans. (c) : An operation amplifier op-amp is a high gain (a) 10% (b) 15%
direct coupled amplifier with high input resistance and (c) 20% (d) 25%
zero output resistance. IES-2020
82. Gain of an Op-Amp inverting amplifier with an Ans. (a) : Differential amplifier - A differential
input of 0.25 V and output of 17.5 V is amplifier is a type of electronic amplifier the difference
(a) 4.375 (b) 17.75 between two input voltage but suppresses any voltage
(c) 17.25 (d) 70 common to the two input.
RPSC Vice Principal ITI-2016
Ans. (d) :
V
Gain of an operational amplifier is given by out
Vin
17.5
A0 = = 70
0.25
83. If an op-amp having specified signal bandwidth
(BW) of 1 MHz and closed loop gain ACL = 200 Vout = A V ( V1 − V2 )
V/mV, the cut-off frequency Fc will be where AV = op-amp gain.
(a) 25 Hz (b) 15 Hz
A
(c) 5 Hz (d) 1 Hz ∵ Common-mode rejection ratio (CMRR) = d
IES-2020 Ac

Analog Electronics 425 YCT

  1 V  Ans. (b) : The switch will be open-
∴ Vo = A d Vid 1 + . c
 CMRR Vid 
Given data -
V1 = +50 µV, V2 = –50 µV
CMRR = 100
Vid = V1 − V2 = 50 − ( −50 ) = 100 µV
1
Vcm = ( V1 + V2 )
2 Apply point A nodal analysis
1 Vi − 0 0 − V0
= 50 + ( −50 )  = 0V =
2 R 2R
 1 0  Vi −V0
∴ V01 = A d ×100 1 + .  =
 100 100  R 2R
V01 = 100 A d µV ................. (i) V0
= −2
And second saturation of input - Vi
V1 = 1050 µV and V2 = 950 µV ∵ Given in this question
Vid = V1 − V2 = 1050 − 950 = 100µV V0
= x = −2 ............. (i)
Vi
1
Vcm = (1050 + 950 ) = 1000 µV Now, switch will be closed then,
2
Vi − 0 0 − V0
 1 1000  =
V02 = A d × 100 1 + × R R
 100 100 
Vi −V0
V02 = 110 A d µV .................... (ii) =
R R
From equation (i) and (2) V0
Percentage difference in the output voltage = −1 ......................(ii)
Vi
V02 − V01 ∴ from equation (i) and (ii),
%V0d = × 100
V01 V0 x
=
110A d − 100A d Vi 2
= ×100
100A d 87. An op-amp is used in a notch filter. The notch
10 frequency is 2 kHz, lower cut-off frequency is
= ×100 = 10% 1.8 kHz and upper cut-off frequency is 2.2 kHz.
100 Then Q of the notch filter.
86. The magnitude of the gain V0/Vi in the (a) 3.5 (b) 4.0
inverting op-amp circuit shown in the figure is (c) 4.5 (d) 5.0
x with switch S open. When switch S is closed, IES-2018
the magnitude of the gain will be Ans. (d) : The bandwidth is defined as the difference in
the upper and lower cut-off frequency.
BW = f upper − f lower

ω0 L X L f
Q= = = r
R R BW
Given value -
fupper = 2.2 kHz, notch frequency = 2 kHz = fr
fLower = 1.8 kHz
x ∴ B.W. = 2.2 – 1.8 = 0.4 kHz
(a) x (b)
2 Then,
2 f 2 kHz
(c) 2x (d) Q= r =
x BW 0.4 kHz
IES-2018 Q = 5

Analog Electronics 426 YCT

88. In op-amp based inverting amplifier with a Apply KCL at inverting terminal,
gain of 100 and feedback resistance of 47kΩ, V1 − 0 0 − V2
=
the op-amp input offset voltage is 6 mV and 1 15
input bias current is 500 nA. the output offset −V2
voltage due to an input offset voltage and an V1 =
15
input bias current, are
− V2 = 15V1
(a) 300 mV and 23.5 mV
(b) 606 mV and 47.0 mV V2 = −15V1
(c) 300 mV and 47.0 mV Apply KCL at y
(d) 606 mV and 23.5 mV 0 − V2 V2 V2 − V0
IES-2018 = +
15 1 15
Ans. (d) : Output offset voltage (V0)offset due to input −V = 16V − V
2 2 0
offset
−17V2 = −V0
 R 
( V0 )offset = 1 + f  Vio −17 × 15V1 = V0
 Ri 
V
∵ Given value - Gain = 100 Ib = 500 nA −255 = 0
V1
Vio = 6 mV,
Feedback resistance = 47 kΩ V0
= −255
Input bias current = 500 nA V1
Then, 90. If an input impedance of op-amp is finite, then
( V0 )offset = (1 + 100 ) × 6 mV which one of the following statements related to
virtual ground is correct?
= 101 × 6 (a) Virtual ground condition may exist.
= 606 mV (b) Virtual ground condition cannot exit
(V0)offset due to input bias current (c) In case of op-amp, virtual ground condition
( V0 )offset = R f I b always exists.
= 47 kΩ × 500 nA (d) Cannot make a valid declaration
IES-2017
= 23.5 mV
Ans. (b) :
89. What is the gain of the amplifier circuit as
In ideal case,
shown in the figure?
Ri = ∞
AV = ∞

V0 = AvVd
V0 = A v ( V1 − V2 ) V1 = Non- inverting voltage
V0
(a) 255 (b) 31 V1 − V2 = V2 = Inverting voltage
(c) –31 (d) –255 Av
IES-2018 ∵ In ideal case Av = ∞
Ans. (d) : V
V1 − V2 = 0
∞
V1 − V2 = 0
V1 = V2 Virtual ground condition.
∴ Virtual short circuit is valid.
Such that, from the equivalent circuit of op-amp, there
is a drop in Ri and
V1 ≠ V2
So, virtual short circuit not valid.

Analog Electronics 427 YCT

91. Hysteresis is desirable in a Schmitt-trigger 93. The transient response rise time (unity gain) of
because an op-amp is 0.05µs. The small signal
(a) Energy is to be stored/discharged in parasitic bandwidth is
capacitances (a) 7 kHz (b) 20 kHz
(b) Effect of temperature variations would be (c) 7 MHz (d) 20 MHz
compensated IES-2016
(c) Devices in the circuit should be allowed time Ans. (c) : ∵ Given value,
for saturating and de-saturating transient rise time (tr) = 0.05 µsec.
(d) It would prevent noise from causing false Relation between rise time (tr) and bandwidth
trigging 0.35
IES-2017 B.W. = ......(i)
tr
Ans. (d) : Schmitt trigger - A Schmitt trigger is a
comparator circuit with hysteresis implemented by 0.35
B.W. =
applying positive feedback to the non-inverting input of 0.05 µ sec
a comparator or differential amplifier. 0.35
=
0.05 × 10−6
B.W. = 7 MHz
94. What is the maximum frequency for a sine
wave output voltage of 10 V peak with an op-
amp whose slew rate is 1V/µs.
(a) 15.92 kHz (b) 19.73 kHz
(c) 23.54 kHz (d) 27.36 kHz
IES-2016
Ans. (a) : Given that -
Slew rate = 1V µs
Upper threshold is given -
 dV 
Slew rate =  0  = 2πf max V0 max
 dt  max
Slew rate ×106
f max =
2πVm
1×106
f max = = 15.92 kHz
2π × 10
Vupper =
Vsat R 1 f max = 15.92 kHz
R1 + R 2 95. An FET-input IC operational amplifier has an
Lower threshold open loop differential gain of 1,00,000 and a
−Vsat R1 common mode gain of 25. Then the common
VL = mode rejection ratio is
R1 + R 2 (a) 46 dB (b) 72 dB
VH = VU − VL (c) 106 dB (d) 144 dB
IES-2015
So, as long as, noise amplitude is in between VLower and Ans. (b) : Given value -
Vupper, the triggering of the circuit does not takes place Ad = 100000
and this prevents noise. Ac = 25
92. In an op-amp, if the feedback voltage is ∴ Common mode rejection ratio
reduced by connecting a voltage divider at the
A 100000
output, which of the following will happen? CMRR = d =
1. Input impedance increases Ac 25
2. Output impedance reduces = 4000
3. Overall gain increases |CMRR|dB = 20 log 4000
(a) 1 only (b) 2 only = 20× 3.60
(c) 3 only (d) 1, 2 and 3 = 72 dB
IES-2019 96. If the inverting input terminal of an
operational amplifier is grounded and a
Ans. (c) : If feedback voltage are reduced by connecting sinusoidal voltage waveform is applied at the
the voltage divider at the output then overall voltage non-inverting input terminal, the output will
gain has increased. be:
Analog Electronics 428 YCT
 (a) Square wave 98. The differential gain of op-amp is 4000 and
(b) Triangular wave value of CMRR is 150. Its output voltage, when
(c) Half-wave rectified sine wave the two input voltages are 200 µ V and 160 µV
(d) full-wave rectified sine wave respectively, will be
IES-2017, 2015 (a) 16 V (b) 164.8 mV
(c) 64 mV (d) 76 mV
Ans. (a) : In an op-amp-
IES-2014
Open loop gain A = ∞ (Ideal case)
Inverting terminal voltage = 0V (according to the given Ans. (b) :
op-amp) Given value –
So, If Vin > 0V that is output saturate (+Vsat). A d = 4000 V1 = 200µV
If Vin < 0V, then output is saturated (–Vsat). CMRR = 150 V2 = 160µV
Note - In open loop it acts as a comparator. Q CMRR for differential Amplifier –
Ad
CMRR =
Ac
4000
150 =
Ac
A c = 4000 /150
= 26.66
Q Differential voltage Vd = V1 − V2
Vd = 200 − 160 = 40µV
So, the output will be square wave for the given Q common-mode input of the op-Amp
sinusoidal input. V + V2
97. An op-amp has the following open loop Vc = 1
2
parameters Zin = 300 kΩ, Zout = 100 Ω, A =
200 + 160 360
50,000. The low frequency system input and Vc = =
output impedance, when closed loop gain is set 2 2
to 100, are = 180 µV
(a) 0.6 Ω and 50 k Ω ∴ Output voltage V0 = A d Vd + A c Vc
(b) 150 M Ω and 0.2 Ω
(c) Same as in open loop V0 = 4000 × 40µV + 26.66 × 180µV
−6
(d) None of the above = (160000 + 4798.8 ) ×10
IES-2014 = 164798.8 × 10−6
Ans. (b) : = 164.798mV
Q Given value. 99. An amplifier using op-amp with a slew rate SR
Zin = 300k Ω , = 1 V/µsec has a gain of 40 dB. If this amplifier
Zout = 100 Ω , has to faithfully amplify sinusoidal signals from
A = 50000 10 to 20 kHz, without introducing any slew-rate
AcL = 100 induced distortion, then the input signal level
A must not exceed.
Q A CL = (a) 795 mV (b) 395 mV
1 + Aβ
(c) 79.5 mV (d) 39.5 mV
50000
1 + Aβ = = 500 GATE-2002
100 Nagaland PSC CTSE (Degree)-2017, Paper-II
Q The input for an op-Amp increase with feedback IES-2014
Zif = Zi (1 + Aβ ) Ans. (c) : Given that,
Zif = 300kΩ × 500 Slew rate = 1V / µ sec
f m = 20kHz
Zif = 150MΩ
Q after feedback output impedance 20 log10 A v = 40dB
Z0 100 A v = 100
Zof = =
1 + Aβ 500  dV 
Q slew rate =  0  = A v Vm 2πf m V/µsec
Zof = 0.2Ω  dt  max

Analog Electronics 429 YCT

Q Slew rate = A v Vm 2πf m Vo(s) 1
=
1V / µ sec = 100 × Vm × 2 × 3.14 × 20 ×10
3
Vi(s) sR i C
10 6 f=0 (at low freqeuncy)
Vm = V0 ( s )
314 × 20 × 2 ×10 3
=∞
= 79.61775 × 10 −3 Vi ( s )
Vm = 79.5mV At low frequency, gain = ∞ and the op-amp saturates.
Thus, Rf is used to prevent saturation.
100. A 5 mV, 1 kHz sinusoidal signal is applied to
the input of an op-amp integrator for which R 102. What is the output voltage for the below
= 100 kΩ and C = 1µF. the output voltage is: circuit?
1
(a) cos(2000πt − 1) (b) cos(2000πt − 1)
40π
−1
(c) cos(2000πt − 1) (d) − cos(2000πt − 1)
40π
IES-2013
Ans. (a) : Given that,
f = 1kHz, R = 100kΩ,C = 1µF (a) –4.8V (b) +1.2V
(c) –2.4V (d) +2.4V
Let, Vi = 5mV sin ( ωt − 1) (Q ω = 2πf )
IES-2011
Vi = 5 × 10−3 sin ( 2π× 103 t − 1) Ans. (c) :

In the integrator circuit –

−1 t
V0 ( t ) = v i ( t ) dt
RC ∫0
−1 Q given value –
5 × 10−3 sin ( 2π×103 t − 1) dt
t
V0 ( t ) = −6 ∫0 V1 = 40mV V2 = 20mV
100 × 10 × 10
3

1 Apply KCL at node A

V0 ( t ) = cos ( 2000πt − 1) mV
40π VA − V0 VA − V1 VA − V2
+ + =0
101. In the circuit shown, the need of the resistor RF 470 47 4.7
is Q VA = 0 (Virtual ground).
0 − V0 0 − 40 0 − 20
+ + =0
470 47 4.7
V 20 40 200 40
− 0 = + = +
470 4.7 47 47 47
V0 240mV
− =
(a) To increase the overall gain 470kΩ 47kΩ
(b) To stabilize the circuit V0 = −2.4 volt
(c) To increase input impedance 103. The output of the below op-amp circuit is
(d) To prevent saturation
IES-2012
Ans. (d) : When resistance (Rf) is not present

Ri

(a) –0.75 volts (b) –cosωt volts

(c) –4 cosωt volts (d) 16 volts
IES-2010
Analog Electronics 430 YCT
Ans. (c) : Ans. (b) : Two type applications of op-amp linear and
non-linear.
1. Linear application of op-amp-
Addition
Substration
I to I or V to V converter
I to V converter
Instrumentation amplifier.
Q According to circuit diagram –
2. Non-linear application of op-amp-
By virtual ground,
Clipper Clamper Limiter circuit
V1 = V2
Comparator Peak detector Log amplifier
Then, Rectifier
R
V2 = ( 4 − 2cos ωt ) + R ( −4 ) 106. Consider the following statements :
2R 2R Dominant-pole frequency compensation in an
1 1
= ( 4 − 2 cos ωt ) + × −4 op-amp :
2 2 1. Increases the slew-rate of the op-amp
= 2 − cos ωt − 2 2. Increase the stability of the op-amp
V2 = − cos ωt 3. Reduce the bandwidth of the op-amp
Therefore, output voltage, 4. Reduces the CMRR of the op-amp
 3R  ( Which of the statements given above are
∴ Vout = 1 +  − cos ωt ) correct?
 R 
Vout = −4cos ωt (a) 1 and 3 only (b) 1, 2 and 4
(c) 1 and 2 only (d) 2 and 3 only
104. Consider the following statements regarding an IES-2008
op-amp :
Ans. (c) : Dominant pole compensation is an external
1. All types of negative feedback reduce
compensation technique used in amplifiers and
nonlinear distortion.
especially in amplifiers employing negative feedback. It
2. All types of negative feedback reduce the usually has two primary goals. To avoid the
output offset voltage. unintentional creation of positive feedback, which will
3. Non-inverting (current and voltage) feedback cause the amplifier to oscillate and to control overshoot.
increases the input impedance. It is also used extensively to improve the bandwidth of
4. Inverting (current and voltage) feedback system. Increases the slew rate, improve the CMRR and
decreases input impedance. overall improve the stability.
Which of the above statements is/are correct? 107. Which one of the following causes phase shift
(a) 1 only (b) 2 and 3 only through an op-amp?
(c) 2 and 4 only (d) 1, 2, 3 and 4 (a) Internal RC circuits
IES-2009 (b) External RC circuits
Ans. (d) : Op-amp characteristics- All types of (c) Gain roll off the internal transistor
negative feedback reduces in non linear distortion and (d) Negative feedback
reduce output offset voltage. Non-inverting (like current IES-2007
and voltage) feedback increases the input impedance Ans. (c) : Phase shift occurs in op-amp due to gain roll
and decreased inverting input impendence. off of the internal transistor.
105. Which of the following are the non-linear 108.
applications of op-amp?
1. Current-to-voltage converter
2. Comparator
3. Peak detector
4. Limiter
Select the correct answer from the codes
given below :
(a) 1, 2 and 3 (b) 2, 3 and 4 What is the output voltage V0 of the above
(c) 1, 3 and 4 (d) 1, 2 and 4 circuit?
Nagaland PSC CTSE (Diploma)-2017, Paper-II (a) –11 V (b) 6 V
RPSC Lect.-2011 (c) 11 V (d) –6 V
IES-2009 IES-2007
Analog Electronics 431 YCT
Ans. (a) : From the circuit-
Vy = Vx − i x Z2
= 0 − I1Z2 ...........(i)
Again,
Vy = 0 + I0 Z1 ...........(ii)
From equation (i) and (ii),
− I1Z2 = I0 Z1
According to circuit diagram,
Point A to B current (I), I0 Z 
∴ = − 2 
2 −1 I1  Z1 
I= = 0.5mA.
2kΩ 110. Consider the following statements :
Q Point C, apply KCL at node C, 1. Stray capacitance at the input terminal of an
V1 = 2 + 10I = 7V. op-amp effectively introduces an additional
Apply KCL at node D, phase lag network in feedback loop.
V2 = 1 − 10I = −4V 2. Stray capacitance depends upon the value of
∴ At the point E, resistor used in feedback.
4.7 3. Low value of resistance has higher effects on
V3 = × V2 stray capacitance.
4.7 + 4.7
4.7 1 4. High value of resistances has higher effects
= × V2 = × −4 on stray capacitance.
9.4 2
Which of the statements given above are
= −2 Volt.
correct?
Therefore, output voltage in circuit,
(a) 1, 2 and 3 (b) 2,3 and 4
V1 − V3 V3 − V0
= (c) 1, 3 and 4 (d) 1,2 and 4
4.7 4.7 IES-2006
V0 = 2V3 − V1
Ans. (a) :
= 2 × ( −2 ) − 7
V0 = −11 Volt
109. In the circuit shown below, what is the value of
transfer function I0/I1?

Stray capacitance effects (Cs) at the input terminal of an

operational amplifier effectively introduces an
additional phase-lag network in the feedback loop. Thus
Z2 Z1 making the Op-amp circuit unstable.
(a) − (b) −
Z1 Z2 With low resistances, small stray capacitances normally
have little effect on the circuit stability.
Z   Z1 
(c) 1 +  2  (d) 1 +   111. An I.C. operational amplifier has a typical
 Z1   Z2  open loop gain of 1200 and the common mode
IES-2006 rejection of 55 dB. What is the common mode
Ans. (a) : rejection ratio (CMRR)?
(a) 550 (b) 560
(c) 570 (d) 580
IES-2006
Ans. (b) :
Given data–
Open loop gain ( A OL ) = 1200
CMRR = 55 dB

Analog Electronics 432 YCT

20log10 ( CMRR ) = 55 From virtual ground concept-
55 V + = V − = V1
log10 ( CMRR ) =
20 Apply KCL at inverting terminal–
CMRR = 10 55 20 I1 = I 2 + I3
CMRR = 562.34 Q I3 = 0A
CMRR ≈ 560 I1 = I2
112. Pulses of definite width can be obtained from Vs − V1 V1 − V0
irregular shaped pulses : = ⇒ Vs − V1 = V1 − V0
(a) When it is given as input to a monostable R1 R1
multivibrator Apply KCL at Non-inverting terminal voltage.
(b) When it is given as triggering signal to a I 4 = I5 + I 6 + I L
bistable multivibrator
(c) When it is used as input to a Schmitt-trigger Q I6 = 0A
(d) When it is used as input to a pulse V0 − V1 V1
transformer = + IL
R2 R2
IES-2005
Ans. (c) : Schmitt trigger works on the principle of V0 − V1 V1 + R 2 ⋅ I L
=
positive feedback. Here are two special case where R2 R2
output is triggered two level– From eqn (i)
(i) UTP (upper threshold point) V1 − Vs = V1 + R ⋅ I L
(ii) LTP (lower threshold point)
Above both level Schmitt trigger switches to saturation −Vs
IL =
level. R2
thus, Schmitt trigger can be used to generate pulses of 114. For a given op-amp, CMRR = 105 and
definite width. differential gain = 105. What is the common
113. For the circuit given below, what is IL equal mode gain of the op-amp?
(a) 1010 (b) 2 × 105
5
(c) 10 (d) 1
IES-2005
Ans. (d) : We know –
A
CMRR = dm
A cm
Where:-
A dm = Differential mode gain (105)
A cm = Common mode gain
−Vs V
(a) (b) s CMRR = (Common mode rejection ratio) (105)
R2 R2
105
−Vs Vs 105 =
(c) (d) A cm
RL R1
ISRO Scientist Engg.-2008 A cm = 1
IES-2005 115. Consider the following op-amp circuit :
GATE-2004
Ans. (a) :

What is the output voltage V0 in the above

op-amp circuit ?
(a) +10 V (b) –10 V
(c) +11 V (d) –11 V
IES-2004
Analog Electronics 433 YCT
Ans. (b) :

(a) –5 mA (b) –10 mA

Using super position theorem – (c) +25 mA (d) +50 mA
Case- I IES-2004
Ans. (b) :
When 1 volt active and 2 volt will be ground.

( V0 ) ' = 1 +
RF  Apply KCL at inverting terminal –
 ⋅ Vx
 R  I1 = I 2 + I3
 100  1× 100  Q ( I 2 = 0A )
= 1 +  
 10  110  10 − V1 V1 − V0
=
110 100 1 1
= × −2V1 = −V0 − 10
10 110
( V0 ) ' = 10V V0 + 10
V1 = ...........(i)
2
Case-II
Apply KCL at Non-inverting terminal –
When 2 volt active and 1 volt will be ground. I 4 = I L + I5 + I 6
Q ( I6 = oA )
V0 − V1 V
= IL + 1
1 1
I L = V0 − 2V1
 V + 10 
= V0 − 2  0 
 2 
I L = −10 mA
( V0 ) " =  − F  ⋅ Vin
R
117. Consider the following circuit :
 R 

( V0 ) " =  −
100 
× 2
 10 
( V0 ) " = −20 Volt.
O/P voltage (when both active)
V0 = ( V0 ) '+ ( V0 ) " = 10 − 20 = −10V
What is the value of R4 in the above circuit, if
116. What is the load current IL in the circuit
the voltage V– and V+ are to be amplified by the
below? same amplification factor?
Analog Electronics 434 YCT
 (a) 7 kΩ (b) 22 kΩ Ans. (c) :
(c) 33 kΩ (d) 35 kΩ Case-I
IES-2004 When V = + Ve
0
Ans. (c) :
Then diode will be in Reverse bias.

V0 = 0V
When V– active and V+ ground.
Case-II
−R 2
( V0 ) ' = ( V– ) When V0 = − Ve
R1
Then diode will be in forward bias.
When V+ active and V− ground.
 R2   R 4 × V+ 
( V0 ) " = 1 +  
 R1  R3 + R4 
V0 = ( V0 ) '+ ( V0 ) "
 R   R  R4 
V0 =  − 2  ( V− ) + 1 + 2    V+ V0 = Vi
 R 1   R1   R 3 + R 4 
there are V− and V+ has to be amplified by same
amplification factor.
V− = V+ = V0
given – R 1 = 10kΩ R 2 = 22kΩ
R 3 = 15kΩ R4 = ?
Hence the circuit works as a positive clipper.
22kΩ  22kΩ   R4 
= 1 +   119. The stage marked X in the shown below
10kΩ  10kΩ   15kΩ + R 4 
architecture of a two-stage op-amp is
22  22   R4 
= 1 +   
10  10   R 4 + 15kΩ 
2.2 R4 (a) Direct coupled amplifier
= ⇒ 2.2R 4 + 33 = 3.2R 4 (b) Buffer amplifier
3.2 R 4 + 15kΩ
(c) Level shifter
⇒ R 4 = 33kΩ (d) Blocking oscillator
118. Consider the following circuit : IES-2003
Ans. (c) :

How does the above circuit work

(a) As a logarithmic amplifier
(b) As a negative clipper
(c) As a positive clipper
(d) As half-wave rectifier
IES-2004 Internal architecture of op-amp.

Analog Electronics 435 YCT

120. The current through the resistor R in the below 122. An op-amp circuit is shown in the figure given
below. Different inputs and output are given
under List-I and List-II. Match List-I (Input)
with List-II (Outputs) and select the correct
answer using the codes given below the list :

List-I List-II
(a) 1 mA (b) 4 mA
(c) 8 mA (d) 10 mA
IES-2003
Ans. (d) :
(a) 1.

(b) 2.

(c) 3.

(d) 4.
Vx = 2V (due to virtual short concept) Codes :
 12 − 2  A B C D
I= 
 1kΩ  (a) 2 4 1 3
I = 10mA (b) 1 3 2 4
Here Q β = ∞ ∴ I B = 0A (c) 2 3 1 4
So IC = I E = I R L (d) 1 4 2 3
I R L = 10mA IES-2002
Ans. (a) :
121. In a circuit, if the open loop gain is 106 and
output voltage is 10 volt, the differential voltage
should be
(a) 10 µV (b) 0.1 µV
(c) 100 µV (d) 1 µV
IES-2002
Ans. (a) : We know–
In op-amp
VO = A OL × Vid
This circuit is differentiator circuit.
Where –
A OL → Open loop gain dVin
O/P will be V0 = −RC
Vid → Input differential voltage. dt
VO 10 As we know–
Vid = = 6 = 10µV
A OL 10 Ramp signal  
d dt
→ step signal  
d dt
→ Impulse signal

Analog Electronics 436 YCT

123. A non-inverting op-amp is shown below Ans. (a) :
(assume ideal op-amp)

 1 
The output voltage VO for an input Vx =   sin t
Vi = [2+ sin(100t)]V  1 + RCs 
(a) 3/2 sin (100t) (b) 3 sin (100t)  1 
= −6  sin t
 1 + 10 × 10 ⋅ s 
6
(c) 2 sin (100t) (d) 3 sin (100t) + 1/2
Nagaland PSC CTSE (Degree)-2017, Paper-II  1 
=  sin t
IES-2002 1+ s 
Ans. (a) :  1  1
=  sin t ⇒  − tan −1 (1 1)  sin t
 1 + jω  2
sin t
Vx = ∠ − 45º
2
 4.14 
V0 = 1 +  ⋅ Vx
 10 
 14.14  sin t
At Non inverting terminal- V0 =   ∠ − 45º
 10  2
 2R 
V0 = 1 +  ⋅ Vx 2
 R  V0 = sin t ∠ − 45º
2
V0 = 3Vx .......... (i)
V0 = sin ( t − 45º )
Apply KCL at Node Vx
V0 = sin ( t − π 4 )
I1 + I2 + I3 = 0
125. In a 741 op-amp, there is 20 dB/decade fall-off
Q I1 = 0A starting at a relatively low frequency. This is
Vx + 2 Vx − ( 2 + sin100t ) due to the
+ =0 (a) Applied load
R R
(b) Internal compensation
2Vx − sin100t = 0
(c) Impedance of the source
sin (100t ) (d) Power dissipation in the chip
Vx =
2 APGENCO AE-23.04.2017
n
Put the value of Vx in eq (i) IES-2001
Ans. (b) : In op-amp, there is 20dB/decade fall-off
3
V0 = sin (100t ) starting at a relatively low frequency this is due to
2 internal compensation.
124. In the circuit shown in the given figure, V0 is 126. The input differential stage of op-amp 741 is
given by biased at about 10µA current. Such a low
current of the input stage gives
1. High CMRR
2. High differential gain
3. Low differential gain
4. High input impedance
Which of these are correct :
(a) sin (t–π/4) (b) sin (t+π/4) (a) 1 and 2 (b) 1, 2 and 4
(c) sin t (d) cos t (c) 3 and 4 (d) 1, 2, 3 and 4
IES-2001 IES-2001
Analog Electronics 437 YCT
Ans. (b) : 2−0
IC = = IE = 5mA
• An ideal op-amp have high CMRR. RL
A ↑ 2
↑ CMRR = dm RL =
A cm ↓ 5 × 10−3
• Differential mode gain is high. R L = 0.4kΩ
• Common mode gain is low.
R L = 400Ω
• Input resistance is high.
127. The main drawback in the performance of 129. In the circuit shown in the given figure, the
shunt peaked wide band amplifier is current through the resistance R is
(a) To low gain at low frequency
(b) Reduced gain at middle frequency
(c) Poor phase response
(d) That the maximum gain of the stage is small
IES-2001
Ans. (c) : The main drawback in the performance of
shunt peaked wide band amplifier is poor phase
response.
128. A circuit is shown in the given figure. The
largest value of RL that can be used is
(a) 100 µA (b) –100 µA
(c) 1 mA (d) –2 mA
IES-2001
Ans. (d) :

(a) 100 Ω (b) 400 Ω

(c) 2 kΩ (d) 20 kΩ
IES-2001
Ans. (b) : Here Vx1 = Vx 2 (due to virtual short concept)
Apply KCL at inverting terminal –
I1 = I2
2 − Vx 2 Vx 2 − V0
=
10 10
2Vx 2 = V0 + 2

V + 2
Vx 2 =  O  .............(i)
Vx = 2V (due to virtual short concept)  2 
12 − Vx 12 − 2 Apply KCL at Non-inverting terminal –
IE = =
2kΩ 2kΩ I 3 = I 4 + I5
I E = 5mA V0 − Vx1 Vx1 Vx1
= +
→ When β (current gain) of transistor i.e. not given we 1 1 10
assumed β = ∞ Vx1
V0 − 2Vx1 =
I 10
β= C 10V0 − 20Vx1 = Vx1
IB
IB = 0 10V0 = 21Vx1

I E = IC 10V0 = 21Vx 2 (Q Vx1 = Vx 2 )

Analog Electronics 438 YCT

 21  V0 + 2  I B = 0mA
V0 =  ( from eq (i) )
n

10  2  IC = I E
21 21
V0 = V0 + I E = 8mA
20 10
V0 = − 42V 132. The V0 of the op-amp circuit shown in the
given figure is
Put the value of V0 in eqn (i)
2Vx 2 = − 42 + 2

Vx 2 = −20V = Vx1
Vx 2 −20
I= = = −2mA
10KΩ 10
I = −2mA
(a) 11 Vi (b) 10 Vi
130. The effect of a finite gain of an operational (c) Vi (d) zero
amplifier used in an integrator is that
IES-1999
(a) It would not integrate
Ans. (d) :
(b) The slope of the output will very with time
(c) The final value of the output voltage will
reduce
(d) There will be instability in the circuit.
APGENCO AE-23.04.2017
IES-2001
Ans. (d) : The effect of a finite gain of an op-amp used
in an integrator is that there will be instability in the
circuit. Output voltage in op-amp.
−10  1 + 10   10 
131. In the circuit shown in the given figure, the V0 = × Vi +  ×  × Vi
current flowing through resistance of 100Ω 1  1   1 + 10 
would be −10 11 10
= × Vi + × × Vi
1 1 11
= –10Vi +10Vi
V0 = 0V
133. The output voltage Vo of the given circuit

(a) 8 mA (b) 10 mA
(c) 20 mA (d) 100 mA
IES-2000
Ans. (a) :
(a) –100 V (b) –100 mV
(c) 10 V (d) –10 mV
IES-1999
Ans. (d) :

Vx = 2V (due to virtual short concept)

10 − 2
IE = = 8mA
1kΩ
Here β is not given so we assume ( β = ∞ )
IC 1st output op-amp
β=
IB Vo1 = −1µA × 1k

Analog Electronics 439 YCT

 = −1mV then red LED will be glow
Second stage of op-amp. For op-amp 2-
Output voltage at non inverting op-amp. V+ < V− then
 R  V0 = −Vsat
Vo = 1 + f  Vin
 R in  then green LED will not be glow
So, clearly only red LED will be glow.
Vin = V01
R F = 90 136. In the circuit shown, it is required that V0 = Vi
the values of l , m, n are respectively.
R in = 10kΩ
(x represents don't care condition)
Put the value
 90 
Vo = 1 +  × −1× 10−3
 10 
= −10 × 10 −3 V
Vo = −10mV
134. In a single-stage differential amplifier, the (a) 0, 1, 1 (b) ∞, x, x
output offset voltage is basically dependent on (c) x, ∞, x (d) 0, x, ∞
the mismatch of IES-1998
(a) VBE, IB and β (b) VBE and IB Ans. (b) :
(c) IB and β (d) VBEand β
LMRC AM (S&T)-13.05.2018
IES-1999
Ans. (c) : Output offset voltage -
Voffset = Input offset voltage × gain +(feedback
resistance) × IB
= Vin (offset) × A v + R f I B Voltage at non-inverting terminal (at node 2)
Here, Av depend upon β and I B lR
Vm = × Vi
So output offset voltage depend upon β and I B (n + l ) R
135. In the circuit shown in the figure, l
Vm = × V …(i)
(n + l) i
KCL apply at node (1)
V0 − Vm Vm − Vi
=
mR R
m ( Vm − Vi ) = V0 − Vm
mVm − mVi = V0 − Vm

(a) Only red will glow V0 = Vm (1 + m ) − mVi …(ii)

(b) Only green will glow From equation (i) and (ii)
(c) Both red and green will glow  l 
Vo = ( m + 1)   ⋅ Vi − mVi
(d) Neither red nor green will glow  n +l 
IES-1998  
Ans. (a) :  1 
Vo = ( m + 1) ⋅ − m  Vi ........ (iii)
  n 
 1 +  
 l
From equation no. (iii). if l → ∞ then
 ( m + 1) 
Vo =  − m  Vi
 (1 + 0 ) 
For op-amp 1- Vo = Vi
V+ > V− then If l → ∞ then it does not matter what is m and n
V0 = + Vsat Hence, m = x, n = x

Analog Electronics 440 YCT

137. In the case of the circuit shown in the figure, 138. For a sinusoidal input, the circuit shown in the
Vio = 10 mV dc maximum, the maximum figure will act as a
possible output offset voltage V∞ caused by the
input offset voltage Vio with respect to ground
is :

(a) Pulse generator (b) Full-wave rectifier

(c) Ramp generator (d) Voltage doubler
ISRO Scientist Engg.-2008
IES-1997
Ans. (b) :
(a) 60 mV dc (b) 110 mV dc
(c) 130 mV dc (d) 150 mV dc
IES-1997
Ans. (b) :

This circuit can be rearranged.

Apply the KCL at node VA

0 − VA VA − Vo
= –––––––––(i)
R1 R2
Diode D1 and diode D 2 will produce negative and
VA = Vio positive signal at output ( Vo ) . So, given circuit act as a
Put the value of equation (i) full wave rectifier.
−Vio Vio − Vo 139. An instrument needs an amplifier to amplify
= pulses of one microsecond duration. This
R1 R2
amplifier must have a bandwidth of at least.
−10mV 10mV − Vo (a) 10 kHz (b) 10 MHz
=
1kΩ 10kΩ (c) 1 kHz (d) 1 MHz
IES-1997
−10 × 10−3 10 × 10−3 − Vo
= Ans. (d) : Amplifier pulse duration ( T ) = 1 × 10 −6
1 10
second
−100 × 10 −3 = 10 × 10 −3 − Vo 1
Frequency =
Vo = 100 × 10−3 + 10 × 10 −3 Time duration
1
Vo = 110 × 10−3 =
1×10−6
= 1MHz
Vo = 110mV
Hence bandwidth = 1MHz

Analog Electronics 441 YCT

140. The op-amp circuit shown in the given figure 142. Op-amp circuit shown in the given figure is
be used for

(a) Addition (a) A sample and hold circuit

(b) Subtraction (b) An integrator
(c) Both addition and subtraction (c) A zero crossing detector
(d) Logarithmic (d) A half-wave precision rectifier
IES-1995
IES-1996
Ans. (a) : Given circuit represents a sample and hold
Ans. (d) : circuit.
143. The op-amp of the circuit shown in the figure
has a unity gain frequency of 1MHz. The cut
off frequency of the feedback amplifier is

Given circuit is a logarithmic amplifier.

141. When z >> z' the op-amp circuit shown in the
given figure behaves as a/an
(a) 100 kHz
(b) 1 MHz
(c) 10 MHz
(d) 90 MHz
IES-1995
Ans. (a) :

(a) Inverting amplifier

(b) Schmitt trigger
(c) Non-inverting amplifier
(d) Voltage follower
IES-1995
Ans. (d) :

Given, R f = 90kΩ, R in = 10kΩ and unity gain

frequency f T = 1MHz
R 
Av = 1+  f 
A voltage follower (also known as a buffer amplifier.)  R in 
Unity-gain amplifier. 90
= 1+ = 10
Whose output is voltage is equal to the input voltage. 10
Unity frequency gain
 z' 
V0 = Vs  1 +  f T = gain × f 3dB
 z
fT 1000000
= Vs 1 + 0 )
( (Q z >> z ') So, f 3dB =
gain
=
10
V0 = Vs f 3dB = 100kHz

Analog Electronics 442 YCT

144. The circuit given in the figure is a 146. Under what condition will the instrumentation
amplifier circuit given in the figure possess
highest CMRR?
( R S1 and R S2 source resistances)

(a) Low-pass filter (b) High-pass filter

(c) Band-pass filter (d) Notch filter
IES-1997, 1994
Ans. (c) :

R1 R 3
(a) =
R2 R4
R S1 + R1 R S2 + R 3
(b) =
R2 R4
R S1 + R 2 R S2 + R 4
This circuit is a band pass filter. (c) =
R1 R3
At low frequency, X c → ∞ then open circuit
R S1 R S2
High frequency, X c → 0 then short circuit. So in both (d) =
R2 R4
case we get small signal in output.
IES-1994
145. Considering the following statements regarding
the state variable section given in the figure A
Ans. (b) : CMRR = d
Ac
For high value of CMRR
Ac should be very low.
Ac ≈ 0
For this condition
R s1 + R1 R s2 + R 3
=
R2 R4
1. V1 is the notch filtered output of Vi 147. The output offset voltage is zero for circuit
2. V3 is the low pass filtered output of Vi given in the figure, when
3. V2 is the band pass filtered output of Vi
Of these statements :
(a) 1, 2 and 3 correct (b) 1 and 2 are correct
(c) 2 and 3 are correct (d) 1 and 3 correct
IES-1994
Ans. (a) :

(a) V1 = 0, I −B = I +B and V1 = V2
(b) V1 = 0 and I−B = I+B
(c) I −B = I +B and V1 = V2
V1 is notch filter output of Vi and V2 is the band pass (d) V1 = 0 and V1 = V2
filter due to capacitor, V3 is low pass filter output of Vi IES-1994

Analog Electronics 443 YCT

Ans. (a) : 149. The approximate input impedance of the op-
amp circuit shown in given figure is

Given offset voltage = 0

V1 = V2 = 0 and I −B = I +B (a) Infinity (b) 120 kΩ
V
+
From above circuit, I = 2
B [Q V2 = 0] (c) 110 kΩ (d) 10 kΩ
R4 IES-1993
+
I =0
B
Ans. (d) :
148. Which one of the following conditions would
give Vo = 0 in the circuit shown in the figure?

Due to the presence of virtual ground at input, the

resistances in the series path of input of inverting
(a) R = R1 + R2 (b) R = R2/R1 amplifier is input impedance,
(c) R = R2 – R1 (d) R = R1 || R2 V+ = V− = 0
IES-1993 Apply KVL at input loop-
Ans. (d) :
− Vin + 10K ( I ) + 0 = 0
Vin
= 10K = R in
I
150. Consider the following statements regarding
the circuit shown in the given figure :

Q Given conditions V0 = 0
AV = ∞
Vid = V1 − V2 = 0
∴ Both input virtual ground.
Apply KCL at inverting terminal,
0 − V1 V − Vo
=I+ 1
R1 R2
–V1 V −0
Q = I+ 1
R1 R2
1. The circuit represents an active low pass
–V1 V
= I+ 1 filter.
R1 R2 2. The circuit represents a second order
and V1 = V2 = −IR active filter.
IR
= I+
( −IR ) 3. The circuit has a roll-off rate of 40 dB/
decade.
R1 R2
(a) 1, 2 and 3 are correct
R
= 1+
( −R ) , 1 = 1 + 1 (b) 1 and 2 are correct
R1 R2 R R1 R 2 (c) 1 and 3 correct
(d) 2 and 3 are correct
∴ R= R1 || R 2 IES-1993
Analog Electronics 444 YCT
Ans. (a) : ∴ Vm = peak value of output signal
Given value –
Slew rate = 100 V µ sec = 100 ×106 V second .
given, f m = 10MHz
100 ×10 = 2 × π × 10 × 106 × Vm
6

10 5
Vm = =
The given circuit represents a second order active low 2× π π
pass filter and roll-off rate = 40 dB/decade. 153. In the Op-Amp circuit shown in, the output
151. The hysteresis phenomenon in Schmitt trigger would be
has which of the following features :
1. It is due to negative feedback
2. In the inverted mode, circuit triggers at a
higher voltage for increasing signals than
for decreasing signals
3. Noise signal voltages greater than VH are
cut-off, where VH is the hysteresis voltage
4. Slowly varying signals are converted to
output waveform with abrupt changes at
two specified levels of input signals. (a) 400 mV (b) 300 mV
Of these four statements, the true statements (c) 200 mV (d) 100 mV
are : TANGEDCO-2015
(a) 2 and 3 only (b) 2 and 4 only
IES-1991
(c) 2, 3 and 4 only (d) 3 and 4 only
IES-1992 Ans. (c) :
Ans. (b) : Hysteresis phenomenon in Schmitt trigger –
• In inverted mode, circuit triggers at a higher voltage
for increasing signal than for decreasing signal.
• Slowly varying signals are converted to output
waveform with abrupt changes at two specified
levels of input signals.
• Schmitt triggers a comparator circuit with hysteresis
implemented by applying positive feedback to the
monitoring input of a comparator or differential Ideal open amplifier,
amplifier. A V = ∞, R i = ∞
Vo = A V Vid
Vid = V+ − V– = 0
Output voltage in op-amp,
10  10  10
V0 = −10 × +  1 +  × × 30
152. An operational amplifier has a slew rate of 1  1  10 + 1
100V/microsecond. For a frequency of 10 MHz, = − 100mV + 300mV
the maximum (peak) value of the sine wave
output voltage will be = 200mV
50 154. In an operational amplifier circuit, the
(a) 100 V (b) V
π maximum frequency for the undistorted output
5 is 100 kHz for 10 Volts P - P output because of
(c) 10 V (d) V the finite slew rate of the op-amp. The
π
maximum frequency for undistorted output of
TANGEDCO-2015
5 volts P - P.
IES-1991
(a) Will be approximately 100 kHz
Ans. (d) : Given , slew rate = 100V/µsec, f = 10MHz
(b) Will be less than 100 kHz
Q Slew rate (Maximum case)
(c) Will be more than 100 kHz
 dVo  (d) Cannot be determined from the given data.
SR =   = 2π[Link]
 dt  max IES-1991

Analog Electronics 445 YCT

Ans. (c) :
∴ Slew rate in op-amp
 dV 
SR =  o  = 2πf m Vm
 dt  max
(d)
Vm = 10V, f max = 100kHz
SR = 10 × 100 × 103 × 2π
SR = 2π × 106 ………….. (1) ISRO Scientist Engg. -2020
When, Vm = 5V, then, Ans. (a) :
SR = 2π × f m × 5
2π × 106 = 2π × f m × 5
f m = 200kHz
Hence, Q f m > 100kHz
155. In the circuit shown, diodes are ideal. Which is
the correct representation of transfer
characteristics of the circuit?

Q In op-amp output voltage can be either +10V to –

5V.
Ideal op-amp-Av = ∞ ,
R i = ∞ , ( Vsat ) = ∞ [ +10V to − 5V ]
V+ = V− = 0 virtual ground
Q Upper threshold voltage , If D2 = on, D1 = off
V .R
VUTP = sat 3
R3 + R2
10 × 4 40
= = = 6.67V
4+2 6
And lower threshold voltage, If D2 = off, D1 = on,
− Vsat .R 3 −5 × 4 −20
(a) VLTP = = = = −3.33V
R 3 + R1 4+2 6

(b)

156. Most of the linear ICs are bases on two

transistor differential amplifiers because of
(a) Input voltage-dependent linear transfer
characteristic
(b) High voltage gain
(c) (c) High input resistance
(d) High CMRR
IES-2013
Analog Electronics 446 YCT
Ans. (d) : Differential Amplifier :- The Given circuit is a Schmitt trigger with positive
• High CMRR can be achieved by employing two- feedback. OP-amp circuit as comparator.
transistor differential amplifiers in most of the linear Vo = +Vcc = +10V, if V+ > V–
ICs. Vi = –Vcc = –10 V, if V– > V+
A Case-I
• CMRR = d
Ac Vi is increase from –∞ to +∞
• Differential Amplifier can reduce external interface. initially V+ dominates Vi = –∞
• Differential amplifier has property of noise Vo = +10 Volt, D2 is forward biased
cancellation. and D1 is reverse biased
157. Given the ideal operational amplifier circuit 2
shown in the figure indicate the correct V+ = 10 × = 8 Volt
transfer characteristic assuming ideal diodes 2 + 0.5
with zero cut-in voltage. then, Vo = +10 Volt, V– < + 8V
if Vi ≥ +8V, then V– dominate.
Vo = –10 Volt.

(a)
Case-II
Vi decreasing from +∞ to –∞
V– dominates initially, Vo = –10 V
D1 is FB and D2 is RB
(b) 2
V+ = –10 × = –5 V
2+2
Hence, V0 = –10 V, Until Vi < – 5 V
V0 = +10 V, When Vi ≤ + 8 V
158. Consider the Schmitt trigger circuit shown
(c) below:

(d)

GATE-2005
Ans. (b) :

A triangular wave which goes from –12V to

12V is applied to the inverting input of the OP-
Amp. Assume that the output of the OP-Amp
swings from +15 V to –15V. The voltage at the
non-inverting input switches between
(a) –12 V and +12V
(b) –7.5 and +7.5 V
(c) –5 V and +5V
(d) 0V and 5V
GATE-2008

Analog Electronics 447 YCT

Ans. (c) : = 1× 10−3 × −103
= −1V
It can be either positive or negative that is ±1V, voltage
follower.
So, output voltage Vo = ±1V
160. The circuit of figure uses an ideal Op-Amp for
small positive values of Vin, the circuit works as

Condition 1 – If Vi = –12 V and V0 = +15 V

Vr – ( +15 ) Vr – ( –15 ) Vr – V0
KCL at Vr, + + =0 (a) A half wave rectifier
10 × 103 10 × 103 10 × 103
Vr – 15 + Vr + 15 + Vr – (–15) = 0 (b) A differentiator
3Vr = –15 (c) A logarithmic amplifier
Vr = +5V (d) An exponential amplifier
Condition 2 – If Vi = +12 V and V0 = –15 V UKPSC Assistant Radio Officer Screening Exam-2011
IES-1994
Vr – 15 Vr – ( –15 ) Vr – V0
KCL at Vr, + + = 0 GATE-1992
10 × 103 10 × 103 10 × 103 Ans. (c) :
Vr –15 + Vr + 15 + Vr – (–15) = 0
3Vr = –15
Vr = –5 V
Hence, the voltage at the non-inverting input (Vr)
switches between –5V and +5V
159. An Op-Amp has an offset voltage of 1mV and
is ideal in all other respects. If this Op-Amp is Q In Ideal op-amp, R = ∞
i
used in the circuit shown in fig. The output
voltage will be (Select the nearest value). So, I + = I − = 0
and gain A OL = ∞
So, Vo = A OL × Vid
Vo V
Vid = = o =0
A OL ∞
 Where V+ = non inverting 
 
Vid = V+ − V− = 0  terminal 
(a) 1 mV (b) 1 V  V = Inverting terminal 
(c) ± 1 V (d) 0 V  – 
RPSC VP/Suptd. ITI 05.11.2019 V+ = V− (Virtual ground)
ISRO Scientist Engg.-2008 V − 0 Vin
GATE-1992 Q I= in = ......(1)
R R
Ans. (c) :
( )
I = Io e V VT − 1 Io ⋅ e V VT
(diode current in forward bias)
I   I  V
= eV VT ⇒  V = VT ln    (where, I = i )
Io   Io   R
 I 
− Vout = VT ln  
 Io 
–R f −106 V 
Q gain= = = −103 = −VT ln  in 
Ri 103  Io R 
Since Vin = Voffset = 1mV
V 
Q Output voltage in op-amp, Vout ∝ −VT ln  in 
Vo = Vin Gain  Io R 

Analog Electronics 448 YCT

161. The circuit shown in the figure is that of Ans. (d) :

(a) A non-inverting amplifiers

(b) An inverting amplifier Q In op-amp open loop gain A oL = ∞, R i = ∞
(c) An oscillator Q V0 = A oL ⋅ Vid
(d) A Schmitt trigger V0 = 0 = V+ − V−
GATE-1996
V+ = V− Virtual ground.
Ans. (d) : Represented circuit diagram → Schmitt
trigger. KCL apply at inverting terminal.
V− − 2 V− − V0
+ =0
5 10
V +4
V− = 0 ............ (1)
3
Again KCL apply at non inverting terminal,
V+ V+ − V0
+ =0
10 100
11V+ − V0 = 0
V0
V+ = ............(2)
11
(Concept of hysteresis in Schmitt trigger circuit) Q V+ = V− ( Virtual ground )
→ Schmitt trigger is form of comparator circuit that has
V0 V0 + 4
hysteresis switching levels to change input to output = from equation (1) and (2)
11 3
between the two states.
3V0 = 11V0 + 44
R2
Vin = ⋅ Vout V0 = −5.5 Volt
R1 + R 2
163. One input terminal of high gain comparator
162. The output voltage V0 of the circuit shown in circuit is connected to ground and a sinusoidal
the figure is voltage is applied to the other input. The
output of comparator will be
(a) A sinusoid
(b) A full rectified sinusoid
(c) A half rectified sinusoid
(d) A square wave
GATE-1998
Ans. (d) :
V+= non inverting terminal voltage
V– = inverting terminal voltage

(a) –4 V
Then, V+ > V−
(b) 6V
V0 = + VCC
(c) 5V
(d) –5.5 V Then, V− > V+
GATE-1997 V0 = −VCC

Analog Electronics 449 YCT

 166. If the op-amp in the figure, is ideal, then V0 is

(a) Zero (b) (V1 – V2) sin ωt

(c) –(V1 + V2) sin ωt (d) (V1 + V2) sin ωt
GATE-2000
Ans. (c) :

If Let, R F = R1 = R 2
V0 = − ( V1 sinωt+V2 sin ωt )
V0 = − ( V1 + V2 ) sin ωt.
164. The first dominant pole encountered in the 167. Assume that the op-amp of the figure is ideal. If
frequency response of a compensated op-amp is Vi is a triangular wave, then V0 will be
approximately at
(a) 5 Hz (b) 10 kHz
(c) 1 MHz (d) 100 MHz
GATE-1999
Ans. (a) : First dominant pole encountered in the
frequency response of a compensated op-amp is
approximate = 5Hz.
(a) Square wave (b) Triangular wave
165. In the circuit of the figure, V0 is
(c) Parabolic wave (d) Sine wave
GATE-2000
Ans. (a) :

(a) –1V (b) 2V

(c) +1V (d) + 15V
GATE-2000
Ans. (d) : Op-amp in balance condition,
iC = i R
CdVi 0 − V0
=
dt R
CdVi V0
=
dt R
dVi
In the given circuit, positive feedback is used and in V0 = −RC ⋅
positive feedback op-amp act in its saturation region dt
± Vsat . −dVi
Q V0 ∝ for differentiator op-amp.
Due to positive feedback V0 = + Vsat = +15V dt

Analog Electronics 450 YCT

 t
(a) 10 cos (100 t) ∫
(b) 10 cos(100t)dt
0
t
d
∫
(c) 10−4 cos(100t)dt
0
(d) 10−4
dt
cos(100t)

GATE-2001
Ans. (a) : Apply nodal analysis at node 1,
0 − Vs 0 − V0 '
+ =0
10 XL
−Vs V0 '
=
10 XL
168. If the op-amp in the figure has an input offset −10cos (100t ) V0 '
voltage of 5 mV and an open-loop voltage gain =
10 XL
of 10,000, then V0 will be
V0 ' = −ωL cos (100t )
V0 ' = −100 × 10 × 10−3 cos (100t )
V0 ' = − cos (100t )
Apply nodal Analysis at node 3,
0 + cos (100t ) 0 − V0
+ =0
100 1 ωc
(a) 0 V (b) 5 mV cos (100t )
= V0 ×100 × 10 × 10−6
(c) + 15 V or –15 V (d) +50 V or –50 V 100
GATE-2000 V0 = 10cos (100t )
Ans. (c) : Q Given value 170. If the input to the ideal comparator shown in
Vio = 5mV the figure is a sinusoidal signal of 8 V (peak to
peak) without any DC component, then the
A oL = 10000 output of the comparator has a duty cycle of
V0 = A oL ⋅ Vid

(a) 1/2 (b) 1/3

(c) 1/6 (d) 1/12
GATE-2003
V0 = 5 ×10000 × 10 −3 Ans. (b) : Q Vin = 4sin ωt
V0 = ± 50 Volt. (But wrong)
Q Op-amp saturation case–
If, V+ > V− then V0 = + VCC
ToN
If, V− > V+ then V0 = −VCC Q Duty cycle = = 360º
T
Therefore, V0 = ±15V ( TON = 180 − 2ωt )
169. In the figure assume the op-amps to be ideal. Let, ωt = x, Vin = 2 volt
The output V0 of the circuit is: Vin = 4sin ωt
2 = 4sin x
1
sin x = ⇒ x = 30º
2
TON T
Duty cycle = = ON
TON +TOFF T
180º −60º 120º 1
= = =
360º 360º 3
Analog Electronics 451 YCT
171. If the op-amp in the figure is ideal, the output 1
voltage Vout will be equal to Vo1 = 50Vin ×
1.25

(a) 1 V (b) 6 V
(c) 14 V (d) 17 V V0 V0 Vo 2 V01
GATE-2003 = ⋅ ⋅
Vin V02 V01 Vin
Ans. (b) :
50V02 V02 V01
= ⋅ ⋅
V02 V01 Vin
1 1
= 50 × 50 × × 50 ×
1.25 1.25
= 50 × 40 × 40
Q Inverting op-amp– = 80000
−R F ( A V )dB = 20log ( A V ) = 20log (80000 )
V0− = ⋅ Vin
R1
( A V )dB = 98.061 dB.
−5K
= ⋅ 2V 173. The circuit in the figure is
1K
V0− = −10 volt.
and Non-inverting terminal voltage in op-amp.
 R 
V0+ = 1 + f  ⋅ V+
 R2 
(a) Low-pass filter (b) High-pass filter
 5  8  (c) Band-pass filter (d) Band-reject filter
= 1 +    × 3V
 1   8+1  GATE-2004
8 Ans. (a) :
= 6× ×3
9
V0+ = 16 Volt.
Therefore, total output op-amp voltage.
V0 = −10 + 16 = 6 Volt.
172. Three identical amplifiers with each one having 1
a voltage gain of 50, input resistance of 1 kΩ If f = 0, X C = = ∞, then signal will be pass.
and output resistance of 250Ω, are cascaded. 2πfC
The open circuit voltage gain of the combined 1
and f = ∞, X C = = 0, then signal will not be pass.
amplifier is 2πfC
(a) 49 dB (b) 51 dB Therefore, represented diagram is low pass filter.
(c) 98 dB (d) 102 dB
174. The input resistance Ri of the amplifier shown
GATE-2003
in the figure is
Ans. (c) :
Given value–
Zout = 250Ω
Zin = 1kΩ

30
(a) kΩ (b) 10 kΩ
4
1 (c) 40 kΩ (d) Infinite
Vo2 = 50Vo1 ×
1.25 GATE-2005

Analog Electronics 452 YCT

Ans. (b) : 176. The op-amp circuit shown in the figure is a
filter. The type of filter and its cut-off
frequency are respectively

According virtual short method.

VA = 0V
VS − VA VS − 0 V
= = S =I
10kΩ 10kΩ 10kΩ (a) High pass, 1000 rad/sec.
VS (b) Low pass, 1000 rad/sec
So, R i = = 10kΩ
I (c) High pass, 10000 rad/sec
175. The voltage e0 indicated in the figure has been (d) Low pass, 10000 rad/sec
measured by an ideal voltmeter. Which of the GATE-2005
following can be calculated? Ans. (a) : The op-amp circuit shown in the figure is
high pass filter.
1
ωc =
RC
1
=
1× 103 × 1× 10−6
ωc = 1000 rad / sec
(a) Bias current of the inverting input only 177. For the circuit shown in the following figure,
(b) Bias current of the inverting and non- the capacitor C is initially uncharged. At t = 0,
inverting inputs only the switch S is closed. The voltage VC across the
(c) Input offset current only capacitor at t = 1 millisecond is
(d) Both the bias currents and the input offset
current
OPSC Poly. Lect.(Instrumentation)-2018, Paper-I
GATE-2005
Ans. (c) : The algebraic difference between the currents
into the inverting and non-inverting terminals is referred
to as input offset current Iio i.e., In the figure shown above, the Op-amp is
Iio = I B1 − I B2 supplied with ± 15V.
(a) 0 Volt (b) 6.3 Volts
(c) 9.45 Volts (d) 10 Volts
GATE-2006
Ans. (d) :

Due to virtual ground method – V2 = V1

V2 = −I B 2 × 1MΩ, V1 = I B1 ⋅1MΩ
Drop in feedback resistance = I B2 × 1MΩ 10 − 0
I= = 10mA = constant current.
e0 = V2 + IB2 ⋅1MΩ 1K
= −IB2 ⋅1MΩ + I B1 ⋅1MΩ V
Q Ideal op-amp, A V = ∞ = 0
Vid
( )
= I B1 − I B2 ⋅1MΩ
V0 V0
Vid = =
e0 = Ii0 ⋅1MΩ , Where I B1 − I B2 = Iio AV ∞

Analog Electronics 453 YCT

Vid = 0 = V+ − V− − virtual ground. Total output voltage in op-amp circuit,
V0 = V01 + V02
At t = 0, switch is closed.
= −2 + 1.5
R i = ∞ → so, no internal current, I + = I − = 0 = −0.5 Volt
A current of 10mA is flowing through capacitor. 179. In the op-amp circuit shown, assume that the
∴ Current flowing through capacitor is constant diode current follows the equation I = Is exp
1 1 t (V/VT). For Vi = 2V, V0 = V01, and for Vi = 4 V,
VC = ∫ idt = ∫ Idt
C C 0 V0 = V02. The relationship between V01 and V02
1 t I is
VC ( t ) = ∫ Idt = × t
C 0 C
∴ Given t = 1ms
1× 10−3 × 10 ×10−3
VC(1ms ) =
1×10−6
= 10 Volt
178. For the op-amp circuit shown in the figure, V0 (a) V02 = 2 V01 (b) V02 = e2 V01
is (c) V02 = V01 ln 2 (d) V01 – V02 = VTln 2
BSNL (JTO)-2009
GATE-2007
Ans. (d) :

(a) –2 V (b) –1 V
(c) –0.5 V (d) 0.5 V
BSNL (JTO)-2009 V0 = −V
GATE-2007 or
Ans. (c) : V = −V0
I = ISe( V VT )
I
= e V VT
IS
V
= ln ( I IS )
VT
KCL at node x, V = VT ln ( I IS )
R2 V0 = − V = −VT ln ( I IS )
V01 = −
× Vin
R1 V0 = −VT ln ( I IS )
−2
= × 1 = −2 Volt  1mA 
1 V01 = −VT ln   .........(1)
Apply KCL at node y,  IS 
 R   2mA 
V02 = 1 + 2  × Vy ……………(i) V02 = −VT ln   ..........(2)
 R1   IS 
 R3  1 2
Where Vy =  × Vin  V01 − V02 = − VT ln   + VT ln  
 R3 + R 4  I
 S  IS 
 R  R3   2  1  m
V02 = 1 + 2    × Vin From equation (i) = VT  ln   − ln    log m − log n ⇒ log
 R1  R 3 + R 4    IS   IS   n
 2  1    2 I 
= 1 +   ×1 ⇒ VT  ln  × S  
 1  1 + 1   
  IS 1  
1
= 3 × = 1.5 Volt V01 − V02 = VT ln2
2

Analog Electronics 454 YCT

180. Consider the following circuit using an ideal Ans. (d) : Suppose the transistor is off:-
op-amp. The I-V characteristics of the diode is Which means the op-amp will act as comparator
 V  Vt = 10V, V– = 5 Volt
described by the relation I = I0  e VT − 1  where
  V = + Vsat ⇒ transistor will be on.
 
VT = 25 mV, I0 = 1 µA and V is the voltage ⇒ The op-amp will operate in the linear region.
across the diode (taken as positive for forward Ideal op-amp.
bias). V V
i.e A = = =∞
Vid V+ − V−
⇒ V+ − V− = 0 (virtual ground condition)
⇒ V+ = V− = 5V

For an input voltage Vi = –1V, the output

voltage V0 is
(a) 0 V (b) 0.1 V
(c) 0.7 V (d) 1.1 V
GATE-2008
Ans. (b) : Output voltage,
V0 = V4K + V = I ( 4K ) + V …………..(i)
Where, 10 − 5
I= = 1mA , I E = 1mA
V4K → Voltage across 4kΩ 5
V → Voltage across diode. VE = IERE =1mA×1.4kΩ
VE = 1.4V
0 − ( −1)
I= = 10µA VBE = V − VE
100kΩ
From the given equation diode current, V = VBE + VE
 V  V = 0.6 + 1.4 = 2V
I D = I = 10µA = I0  e VT − 1
 
  Negative feedback, V = 2V
10µA = 1µA ( e V 0.25 − 1) 182. Assuming the op-amp to be ideal, the voltage
V = 0.06V gain of the amplifier shown below is
V0 = I ( 4K ) + V (equation- i)
V0 = 10µA × 4kΩ + 0.06
V0 = 0.04 + 0.06
V0 = 0.1 Volt
181. In the circuit shown below, the op-amp is ideal,
the transistor has VBE = 0.6 V and β = 150. R2 R3
Decide whether the feedback in the circuit is (a) − (b) −
R1 R1
positive or negative and determine the voltage
V at the output of the op-amp.  R || R 3   R + R3 
(c) −  2  (d) −  2 
 R1   R1 
GATE-2010
Ans. (a) : Redraw the circuit-

(a) Positive feedback V = 10 V

(b) Positive feedback, V = 0 V
(c) Negative feedback, V = 5 V
(d) Negative feedback, V = 2V
GATE-2009
Analog Electronics 455 YCT
I1 = I2 20 Vi V0
+ + =i
Vi − 0 0 − V0 4R R R
= If V0 is positive not conduct i = 0
R1 R2
Then,
−R 2 Vi 20 Vi V0
V0 = + + =0
R1 4R R R
V0 R 5+Vi+V0 = 0
=− 2 At Vi = –10V
Vi R1 V0 = –5+10 = 5V
183. The transfer characteristic for the precision At Vi = –5V
rectifier circuit shown below is (assume ideal V0 = –5+5 = 0V
op-amp and practical diodes) 184. In an op-amp, non-inverting terminal is
grounded, input is connected to inverting
terminal and there is no feedback resistance.
The output is
(a) A Vin (b) –A Vin
(c) A/Vin (d) –A/Vin
SAIL- 2014
Ans. (b) :

When input is connected to inverting terminal and there

is no feedback resistance then-
(a) V0 = –A Vin
185. A differential amplifier has a differential mode
gain of 100 and a common mode rejection ratio
of 1000. If the two applied input voltages are v1
and v2, then the output voltage will be :
(b) (v + v 2 )
(a) 100(v1 − v 2 ) + 0.1 1
2
(v1 + v 2 )
(b) 100 + 0.1(v1 − v 2 )
2
(v + v 2 )
(c) 100(v1 − v 2 ) + 105 1
(c) 2
(v1 + v 2 )
(d) 100 + 100(v1 − v 2 )
2
BSNL(JTO)-2002, 2001
Ans. (a) : Given that,
Common mode rejection ratio (CMRR) = 1000
(d) Differential mode gain (Ad) = 100
A
Q CMRR = d (Where Ac is common mode gain)
Ac
GATE-2010
100
Ans. (b) : 1000 =
Ac
1
Ac =
10
For two input voltage v1 & v2
Output voltage = Ad vd + Ac vc
1  v 1 + v2 
Output voltage = 100 (v1 – v2) +  
10  2 
(v + v 2 )
Output voltage = 100 (v1 – v2) + 0.1 1
i1 + i2 + i3 = i 2

Analog Electronics 456 YCT

186. Schmitt trigger can be used as 188. In the circuit shown below what is the output
(a) Comparator (b) Square-wave generator voltage (Vout) if a silicon transistor Q and an
(c) Flip-flop (d) All of these ideal op-amp are used?
Nagaland PSC CTSE (Degree)-2016, Paper-II
Nagaland PSC CTSE (Degree)-2015, Paper-II
TSGENCO AE-2015
Ans. (d) : Schmitt-trigger can be used as square wave
generator.
• Schmitt trigger work as a principle of positive
feedback configuration
• Schmitt trigger also used to remove noise from an (a) –15V (b) –0.7 V
analog signal while converting it to a digital signal. (c) +0.7 V (d) +15 V
• A Schmitt trigger is basically an inverting comparator GATE-2013
circuit with positive feedback. Ans. (b) : Input to the op-amp is given to inverting
• It converts any wave into a square wave. terminal the output will be negative value.
• It can be used as a flip-flop. Transistor is biases → positive voltage (Collector) and
187. The circuit below implement a filter between negative voltage (Emitter) and base → ground.
the input current ii and output voltage V0. Therefore, base to collector junction → reverse and
Assume that the op-amp is ideal. The filter base to emitter junction → forward bias.
implemented is a Then, transistor (Si) cut- in voltage = 0.7 volts.
So, base to emitter voltage drop = 0.7 volts
VB − VE = 0.7
Q BJT VB = 0, IC = 5mA
∴ 0 − VE = 0.7
VE = −0.7 (Q Base is ground)
VB = 0V
∴ given circuit Vout = VE
(a) Low pass filter (b) Band pass filter
V0 = −0.7
(c) Band stop filter (d) High pass filter
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I 189. In the circuit shown, the op-amp has finite
GATE-2011 input impedance, infinite voltage gain and zero
Ans. (d) : input offset voltage. The output voltage Vout is
Effective impedance in feedback path
Z P = X L1 || R 1
Vout = i i ( Z P )
(
Vout = ii X L1 || R1 )
X L1 = 2 πfL1 (a) –I2 (R1 + R2) (b) I2 R2
(c) I1 R2 (d) –I1 (R1 + R2)
For low frequency - as f 0 = 0, X L = 0 UPPSC ITI Principal/Asstt. Director-09.01.2022
Vout = ii1 ( 0 || R1 ) GATE-2014
Ans. (c) :
Vout = 0 (that is DC component is not passed)
So that output is going to be block in the DC
component.
For large frequency of
f ↑ X L ↑ ( L arg e )
( )
V0 = ii X L1 || R 1 ≅ ii ( R1 )
Because X L1 is large as compared to R1 so parallel KCL at node A
V2 = (R1|| R2)I1….(i)
combination always gives the smaller than the smallest Apply KCL at node A
one V0 ≅ i1 ( R 1 ) = output occurs for large value of
I1' + I1" = 0
frequency.
→ This filter is rejecting the low frequency and it is 0 − V2 V0 − V2
+ =0
passing the High frequency. R1 R2

Analog Electronics 457 YCT

 V0 − V2 V2  β + 1  Vref  β  Vref
= (a) I0 =   (b) I0 =  
R2 R1  β  R  β +1 R
V0 V2 V2
− =  β + 1  Vref  β  Vref
(c) I0 =   (d) I0 =  
R 2 R 2 R1  β  2R  β + 1  2R
V0  1 1  GATE-2016
= V2  + 
R2  R1 R 2  Ans. (b) :
from equation i & ii, V+ = Vcc − Vref = V−
V0 = I1R 2 Vcc − V− Vref
IE = =
190. Assuming that the op-amp in the circuit shown R R
is ideal, V0 is given by V+ = non inverting voltage
V– = inverting voltage

5 5
(a) V1 − 3V2 (b) 2 V1 − V2
2 2
3 7 11
(c) − V1 + V2 (d) −3V1 + V2
2 2 2
GATE-2014
Ans. (d) :

IE = I
β β V
I0 = Ic = α I E = IE = × ref
1+ β 1+ β R
Apply KCL at node A, we get
V2 − V1 V2 V2 − V0  β  Vref
+ + =0 I0 =  
R 2R 3R  1+ β  R
6V2 − 6V1 + 3V2 + 2V2 − 2Vo
=0 192. For the operational amplifier circuit shown, the
6R
output saturation voltages are ± 15 V. The
11V2 − 6V1 = 2V0
upper and lower threshold voltages for the
11 circuit are, respectively,
V0 = −3V1 + V2
2
191. Consider the constant current source shown in
the figure below. Let β represent the current
gain of the transistor.

(a) +5 V and –5 V
(b) +7 V and –3 V
(c) +3 V and –7 V
(d) +3 V and –3 V
The load current I0 through RL is GATE-2017

Analog Electronics 458 YCT

Ans. (b) : 1
= × 10−3 t1
10−6
= 1000t1 …(i)
Q Capacitor C 2 across voltage Vc2
1 t
{Q C 2 = 1µF}
C2 ∫0
= Ic dt

1 t
Ic dt = 1000 ( t 2 )
10−6 ∫0
…(ii)
KCL at node A
Q t = 0 switch closed then zener diode will be open.
VA − Vo VA − 3 Vc = Vc = 2.5 volt (zener diode turn on).
+ =0
10kΩ 5kΩ
1 2

Put value equation (1),

VA − Vo + 2VA − 6 = 0
2.5 = 1000t1
6 + Vo
VA = t1 = 2.5ms (zener turn on)
3
For UTP, Vo= +15V ∴ C1 continue to charge = 7.5 volt
Then, Q Vc2 = 5 volt
6 + 15 ∴ 5 = 1000 × t 2 (from equation …ii)
VUTP = = 7V
3
t 2 = 5msec
For LTP, Vo = –15V
6 − 15 ∴ Total time T = t1 + t 2
Then, VLTP = = −3V = 2.5 + 5
3
193. In the circuit shown below, the op-amp is ideal = 7.5m sec
and Zener voltage of the diode is 2.5 volts. At 194. The components in the circuit shown below are
the input, unit step voltage is applied i.e. VIN(t) ideal. If the op-amp is in positive feedback and
= u(t) volts. Also at t = 0, the voltage across the input voltage Vi is a sine wave of amplitude
each of the capacitors is zero 1 V, the output voltage V0 is

(a) A square wave of 5V amplitude

The time t, in milliseconds, at which the output (b) An inverted sine wave of 1V amplitude
voltage VOUT crosses –10 V is (c) A non-inverted sine wave of 2V amplitude
(a) 2.5 (b) 5 (d) A constant of either +5 or –5V
(c) 7.5 (d) 10 GATE-2020
GATE-2018 Ans. (d) :
Ans. (c) :

Given value = Zener diode voltage V2 = 2.5 volt Apply KCL -

Vout = −10Volt V+ − Vi V+ − V0
+ =0
Q Capacitor does not change sudden voltage. 1k 1k
1− 0 Vo = −5V
Ic = = 1mA
1k −5 + Vi
Then, V+ =
1 t 1 2
Q Vc1 = ∫ Ic dt = −6 × Ic t1
C1 0 10 Vo change from –5V to +5V, if V+ > 0

Analog Electronics 459 YCT

 −5 + Vi 198. The output voltage of circuit shown below is
> 0, Vi > 5V
2
In the same way Vo change from +5V to –5V, if Vi<–
5V, but Vi has maximum value of 1V, so output cannot
change from +5V to –5V or –5V to +5V. Hence output
remain constant at +5V or –5V.
195. The components in the circuit given below are
ideal. If R = 2 kΩ and C = 1 µF, the –3 dB cut-
off frequency of the circuit in Hz is
(a) –10V (b) 5 V
(c) –5V (d) 0.5V
TSGENCO AE-2015
Ans. (c) : Apply KCL at node 2,
0 − 500 0 − Vout
+ =0
R1 R2
(a) 34.46 (b) 79.58 −500 −Vout
+ =0
(c) 59.68 (d) 14.92 1kΩ 10kΩ
GATE-2020 −500mv V
= out
Ans. (b) : Given value, 1kΩ 10kΩ
R = 2kΩ, C = 1µF Vout = −5V
Q cut off frequency of the circuit. 199. The differential gain of op-amp is 4000 and
1 value of CMRR is 150. Its output voltage, when
ω0 =
RC the two input voltages are 200 µV and 160 µV
1 respectively, will be
2πf 0 = (a) 16 V (b) 76 mV
RC (c) 64 mV (d) 164.8 mV
1 TSGENCO AE-2015
3.14 × 2 × f 0 =
2 × 103 × 10−6 Ans. (d) : Given, V1 = 200 µV, V2 = 160 µV, Ad =
103 4000, CMRR = 150
f0 = V0 = AdVd + AcVc Vd = V1–V2
2 × 3.14 × 2
= 79.6Hz V + V2
Vc = 1
196. The rise time of low pass RC Circuit is given by 2
(a) 2.2 RC (b) 30.2 RC A
CMMR = d
(c) 10 RC (d) 20.2 RC Ac
TSGENCO AE-2015 4000
150 = ⇒ A c = 26.67
Ans. (a) : The rise time of Low pass RC circuit is given Ac
by
Vd = V1 − V2
τ = 2.2 RC
Vd = 200 – 160 ⇒ Vd = 40 µV
197. In RC integrator circuit the output is taken
200 + 160
across Vc = = 180µV
(a) resistor 2
V0 = 4000 × 40 ×10–6+ 26.67 × 180×10–6
(b) transistor
(c) diode V0 = 164.8mV
(d) capacitor 200. In an RC differentiator, the condition for
TSGENCO AE-2015 differentiation is
Ans. (d) : (a) RC >> 0.16T (b) RC << 0.16T
(c) RC >> T/0.16 (d) RC << T/0.16
Kerala PSC Lecturer (NCA) 04.07.2017
Ans. (b) : In an RC differentiator, the condition for
differentiation is τ << 0.16T. A RC differentiator is a
series connected RC network that produce an output
In RC integrator circuit, the output is taken across the signal which corresponds to the mathematical process
capacitor. of differentiator.

Analog Electronics 460 YCT

201. An op-amp is having an open loop gain of V
'10^(5)' and open loop upper cutoff frequency In dB, 20log 0 = 20 dB
of 10 Hz. If this op-amp is connected as an Vi
amplifier with a closed loop gain at 100, then V
the new upper cutoff frequency will be or, 0 = 10 = voltage gain
Vi
(a) 10 Hz (b) 100 Hz
As gain bandwidth product remains constant, hence,
(c) 10 kHz (d) 100 kHz
1 × 106 = 10 × Bnew
Kerala PSC Lecturer (NCA) 04.07.2017
MPPSC Forest Exm.2014 Bnew = 105 = 100 kHz
Mizoram PSC AE/SDO-2012, Paper-I 204. An OPAMP-based comparator drives an LED,
Ans. (c) : Given, AOL = 105 fH = 10 Hz with VF = 1.6V, the current through which is
ACL = 100 regulated by a 1kΩ resistor and a silicon diode
5 in series. Assume a ±10V DC voltage is applied
A OL 10
ACL = ⇒1 + A OL .β = as ±VCC respectively to the op-amp. Then find
1 + A OL β 100 out the current through the LED when the
1 + AOL β = 103 comparator output is + 10V.
fCH = fH(1 + AOLβ) = 10×103 (a) 5.4mA (b) 8.5mA
fCH = 10 kHz (c) 7.7 mA (d) 6.7mA
202. Most of the linear ICs are based on the two APPSC POLY. LECT. 14.03.2020
transistor differential amplifier because of its
Ans. (c) :
(a) High CMRR
(b) High voltage gain
(c) High input resistance
(d) Input voltage dependent linear transfer
characteristics
Kerala PSC Lecturer (NCA) 04.07.2017
IES-2013
Ans. (a) : Most of the linear ICs are based on the two
transistor differential amplifier because it has high
CMRR. VD = 1.6 + 0.7
CMRR- It is defined as the ratio of differential voltage = 2.3
gain to common mode voltage gain 10 − 2.3
ID =
CMRR = d
A 1 kΩ
Ac
I D = 7.7 mA
- It indicates the ability of an op-amp to reject common-
mode noise signals and to amplify desired differential 205. When an OP-AMP is used as an inverting
mode signal. amplifier with Rf = 100 kΩ and R1 = 10 kΩ, the
- The ideal op-amp will have the infinite CMRR and closed-loop gain is :
with finite differential gain and zero common mode (a) 10.00 (b) – 10.00
gain. (c) – 11.00 (d) 11.00
-High CMRR can be achieved by employing two-
APPSC POLY. LECT. 14.03.2020
transistor differential amplifiers in ICs.
203. A 741-type op-amp has a gain-bandwidth Ans. (b) : Given, Rf = 100kΩ , R1 = 10kΩ
product of 1 MHz. A non-inverting amplifier R
using this op-amp and having a voltage gain of Close loop gain inverting amplifier = – f
Ri
20 dB will exhibit a 3 dB bandwidth of:
(a) 100 kHz (b) 50 kHz Vo −100
= = −10
1000 1000 Vin 10
(c) kHz (d) kHz
17 7.07 206. The transfer function T(s) of a single OPAMP
Punjab PSC Poly. Lect. 20.08.2017 inverting mode filter that has a capacitance C
GPSC Asstt. Prof. 11.04.2017 and resistance R in the feedback path and an
GATE-2002 input resistance R is :
Ans. (a) : Given, (a) –1/{1 + sRC} (b) 1 + sRC
V (c) – sRC/{1 + sRC} (d) sRc/{1 + sRC}
Non inverting amplifier voltage gain = 0
Vi APPSC POLY. LECT. 14.03.2020

Analog Electronics 461 YCT

Ans. (a) : Ans. (c) : The output voltage is the sum of input voltage
with different weighting factor this circuit is called as
inverting summing amplifier.
210. For a non inverting op-amp when Ri = ∞, in an
open circuit, the closed-loop gain becomes
V
A v = 0 = 1 , then output voltage follows the
Vi
Vi × 1/ Cs input; this op-amp circuit is called:
V0 = − (a) Basic amplifier
1
R+ (b) Voltage follower
Cs
(c) Summing amplifier
V0 1 (d) Non inverting amplifier
=−
Vi 1 + RCs UPSC [Link].10.03. 2019
Ans. (b) : For a non-inverting op-amp if the closed loop
V0 1 gain become 1. Then output voltage follow the input
T(F) = =− voltage. This circuit is called voltage follower.
Vi 1 + RCs
211. What is the output voltage of an op-amp for
207. In a regulated power supply, a pass transistor input voltages of Vi1 = 150 µV, Vi2 = 140 µV
is used at the output of OPAMP to :
with amplifier differential gain of Ad = 4000
(a) provide a higher gain in the feedback loop.
and the value of CMRR = 100?
(b) provide a high input impedance to the
(a) 72.2 mV (b) 63.4 mV
OPAMP.
(c) 54.6 mV (d) 45.8 mV
(c) provide a larger current drive to the load.
(d) allow input voltage to pass efficiently to the UPSC [Link].10.03. 2019
output. Ans. (d) : Output voltage V0 = Ad Vd + Ac Vc _____(i)
APPSC POLY. LECT. 14.03.2020 Ad = 4000, Ac = 4000/100 = 40
Vd = 10 µV, Vc = 145 µV
Ans. (c) : In a regulated power supply, a pass transistor
V0 = 4000 × 10µV + 40 × 145 µV
is used at the output of OPAMP to provide a larger
current drive to the load. = 45.8 mV.
208. Consider an inverting amplifier with a 212. The responsivity of the PIN photodiode shown
is 0.9 A/W. To obtain Vout of – 1 V for an
feedback resistor R2 = 10 kΩ and an op-amp incident optical power of 1 mW, the value of R
with parameters; AoL = 105 and Ri = 10 kΩ. to be used is
Assuming the output resistance R0 of the op-
amp is negligible, the closed-loop input
resistance at the inverting terminal of an
inverting amplifier will be nearly:
(a) 0.4 Ω (b) 0.2 Ω
(c) 0.1 Ω (d) 0.05 Ω
(a) 0.9 Ω (b) 1.1 Ω
UPSC [Link].10.03.2019 (c) 0.9 kΩ (d) 1.1 kΩ
Ans. (c) : The open loop gain of inverting amplifier AoL APGENCO AE- 23.04.2017
= 105. Input resistance Ri = 10 kΩ, So closed loop input
I
resistance will be reduce by the factor {1 + (AoL. β)}. Ans. (d) : Responsivity = 0
Pi
R ( Open Loop )
R 1 ( Closed Loop ) = 1 I0 = Resposivity × Pi
(1 + A oL .β )
= 0.9A / W × 1mW
R1 ( Open Loop ) 104
= 5 = 0.1Ω = 0.9mA
A oL 10 So,
209. The output voltage is the sum of the input V0 = I0 × R
voltage, with different weighting factors. This − 1V = 0.9mA × R
circuit is called: R = 1.1kΩ
(a) Non inverting summing amplifier
213. A typical 8 pin op-amp has pin number 6 as
(b) Ideal op - amp
the:
(c) Inverting summing amplifier (a) inverting input (b) noninverting input
(d) Non inverting amplifier (c) output (d) positive power supply
UPSC [Link].10.03.2019 APPSC Poly. Lect. 15.03.2020
Analog Electronics 462 YCT
Ans. (c) : For 8-pin op-amp, 6th pin is output Ans. (a) :

0 − 2 0 − 1 0 − V0
By KCL at node-A = + + =0
5k 2.5k 10k
214.
2 1 V
− − = 0
5 2.5 10
V0 = −8V
217. The output offset voltage of the circuit given
here is______(given VIo = 1.2 mV)

For the given circuit, if Vi = 0.5V, the value of

Vo will be :
(a) – 2.5V (b) – 1.25 V
(c) 2.5V (d) 1.25V
APPSC Poly. Lect. 15.03.2020
Ans. (b) : Given Rf = 25kΩ, Ri =10 kΩ, Vi =0.5 V
(a) 76 mV (b) 15.7 mV
R (c) 91.2 mV (d) 101.5 mV
V0 = − f × Vi
Ri RPSC ACF & FRO 23.02.2021
−25kΩ APPSC Poly. Lect. 15.03.2020
= × 0.5 1
10kΩ Ans. (c) Vof = VI0
Vo = −1.25V β
R in
215. where β =
R f + R in
given,
Input offset voltage (VIo) =1.2 mV
Input resistance (Rin) = 2kΩ
The given circuit represents a/an : feedback resistance(Rf) =150 kΩ
(a) inverting amplifier 2kΩ
(b) non inverting amplifier β=
150kΩ + 2kΩ
(c) voltage follower
β = 0.01316
(d) difference amplifier
APPSC Poly. Lect. 15.03.2020 1
= 76
 R  β
Ans. (b) : Since Vo = Vi 1 + 2  → ( + ve) Vof = 1.2 × 76mV
 R1 
A non inverting amplifier is an operational amplifier Vof = 91.2mV
circuit with an output voltage that is in phase with the 218.
input Voltage. Inverting op-amp which produces an
output signal that is 180º out of phase.
216.

Vo for the above op-amp circuit is :

(a) – 8V (b) – 4V
(c) 8V (d) 4V
APPSC Poly. Lect. 15.03.2020
Analog Electronics 463 YCT
 For the differential amplifier circuit shown (c) Square output when the input is trapezoidal
here Vc1 and Vc2 are respectively. (d) Rectangular output regardless of the input
(a) 12V and 2.7V (b) 12V and 9.7V waveform
(c) – 12V and 2.7V (d) – 12V and 9.7V APPSC Poly. Lect. 15.03.2020
APPSC Poly. Lect. 15.03.2020 Ans. (d) : A Schmitt trigger is a digital circuit that
Ans. (b) : From circuit Vc1 = 12V produces rectangular output regardless of the input
waveform as it saturates at a positive high for some time
12 − 0.7 12 − 0.7 and negative high for the other time. So only produces a
IE = = = 0.452mA
RE 25k square wave.
I 221. A difference mode gain of an amplifier is 2000,
Ic2 = E = 0.226mA CMRR = 100, difference mode input = 0.1 mV,
2
common mode input is 0.95 mV. The output is
∴ Vc2 = Vcc − Ic2 .R c2
(a) 438 mV (b) 219 mV
= 12 − (0.226 × 10−3 × 10 × 103 ) = 9.74V (c) 657 mV (d) 200 mV
219. Nagaland PSC (Degree) 2018, Paper-II
Ad
Ans. (b) : ∴ CMRR =
A cm
2000
∴ Acm = = 20
100
Vout = AdVd + AcmVcm
= (2000 × 0.1 + 20 × 0.95) mV
= 219 mV
222. A differential amplifier has inputs V1 = 1050
µV, the inverting terminal V2 = 950µV and
CMRR = 1000. The error in the differential
The instrument amplifier shown here is an output is
amplifier of low level signals used in process (a) 10% (b) 1%
control and commercially available in single-
package units. Vo for the instrument amplifier (c) 0.1% (d) 0.01%
is : Nagaland PSC (Degree) 2018, Paper-II
Nagaland PSC CTSE- 2015, Paper-II
R2  R3 
(a) v o = 1 +  (v 2 − v1 ) IES-2006
R 1  2R 4  Ad
Ans. (b) :CMRR = .........(I)
R  2R 3  A cm
(b) v o = 2  1 +  (v 2 − v1 )
R1  R4  Vo = AdVd + AcmVc
 A V 
R  R  Vo = A d Vd  1 + cm c 
(c) v o = 2  1 + 3  (v 2 − v1 )  A d Vd 
R1  R 4 
 A cm Vc 
Vo = A d Vd 1 + 
R  2R 4   CMRR A V
cm d 
(d) v o = 2  1 +  (v 2 − v1 )
R1  R3   1 V 
Vo = A d Vd  1 + × c
APPSC Poly. Lect. 15.03.2020  CMRR Vd 
Ans. (b) : It is a output of differential amplifier
V 1
 2R 3 
R2 Error in differential output = c × ×100%
Vo = 1 +  [ V2 − V1 ] Vd CMRR
R1
 R4 
V1 + V2 1050 + 950
220. A Schmitt trigger is a digital circuit that Vc = = = 1000µV
2 2
produce
Vd = V1 – V2 = (1050 – 950) = 100µV
(a) Rectangular output when the input is
1000
sinusoidal so error in differential output = × 100
(b) Sinusoidal output when the input is 1000 × 100
rectangular = 1%

Analog Electronics 464 YCT

223. The output voltage for the open loop 225. The circuit shown below is a
differential amplifier of given figure is (Assume
Vin1= 5µV DC, Vin2 = -7µV DC, A = 200,000)

(a) Half-wave rectifier (b) Average detector

(c) Peak detector (d) Clamping circuit
Nagaland PSC CTSE- 2015, Paper-II
TNPSC AE-2019
IES-1997
(a) 10V (b) 2.4V Ans. (c) : Peak detector is a circuit which is used to
(c) -20V (d) -1.4V detect the peak of the applied input signal. It basically
TNPSC AE- 2019 follows the input voltage and store the peak voltage.
Ans. (b) : Open loop differential amplifier

The given circuit is known as Peak detector.

226. In the circuit shown below, find Io

Vd = Vin1 –Vin2
hence, Vd = ( 5+7) µV
Vd = 12µV
Vout = AVd
Vout = 200000 × 12×10-6 Vs R L Vs
= 2. 4 V (a) (b)
Rs (RL + Rs ) Rs
224. The transfer function of a second order low
pass filter shown in Figure is Vs  1 1 
(c) (d) Vs  + 
RL R
 s R L 

Nagaland PSC CTSE- 2015, Paper-II

Ans. (b) :

1
(a)
R C s + 3RCs + 1
2 2 2

RCs
(b)
R 2 C 2s 2 + 3RCs + 1
Vo − Vs
R 2 C 2s 2 + 1 Io =
(c) RL
R 2 C 2s 2 + 3RCs + 1
 R   R + RL 
R 2 C 2s 2 And Vo = 1 + L  Vs =  s  Vs
(d)  R s   Rs 
R 2 C 2s 2 + 3RCs + 1
TNPSC AE- 2019  Rs + RL 
  Vs − Vs
Ans. (a) : Transfer function of second order low pass  Rs   R + RL − Rs 
Then, I o = = Vs  s 
filter RL  R sR L 
Vo ( s ) 1 V
H(s) = = Io = s
Vi ( s ) s 2 R 2 C 2 + 3sRC + 1 R s

Analog Electronics 465 YCT

227. Frequency at which the gain of op-amp is zero
decibel is called
(a) α cut off frequency
(b) α cut off frequency (a)
(c) gain crossover frequency
(d) unity gain cross over frequency
Nagaland PSC CTSE- 2015, Paper-II
TNPSC AE-2013
Ans. (d) : The frequency at which the magnitude is
equal to one is called unity gain frequency.
In dB, 20 log10 (1) = 0 dB (b)
If G ( jω) H ( jω) = 1 (Q log10 1 = 0 )
228. OPAMP circuit given below is a __________

(c)

(a) Differentiating Amplifier

(b) Integrating Amplifier
(c) Differential Amplifier
(d) Summing Amplifier (d)
(e) Inverting Amplifier
CGPSC SO 14.02.2016
DRDO-2008
Ans. (b) : An integrator is an Op-Amp circuit whose
output is proportional to the integral of input signal. An
integrator is basically an inverting amplifier where we
replace feedback resistor with a capacitor of suitable
value (e)

CGPSC SO 14.02.2016
Ans. (a) : (1) Vin < 3 : Vout = Vin
(2) Vin > 3 ; Vout = 3V

−1
t

RC ∫0
Vout = Vin (t)dt

229. Which of the five waveforms of Vout predicts 230. Out of following circuit is _______
the correct output of circuit for Vin as shown
below:

(a) 3 V (b) 6 V
(c) 9 V (d) 12 V
(e) 24 V
CGPSC SO 14.02.2016
Analog Electronics 466 YCT
Ans. (d) : 232. In the given block diagram, which is the
sampling element?

Apply KCL at node x

3− x 3− x
+ =0 (a)Voltage divider using R1 and R2
10 10 (b)Transistor Q2
3− x +3− x = 0 (c)Op-amp
x=3 (d)R3 and Zener diode
Virtual ground concept UPRVUNL AE -19.07.2021, Shift-II
y = 3V Ans. (a) : In given circuit voltage divides using R1 and
Apply KCL at node y- R2 are act as sampling element.
233. Consider the following :
0 − 3 3 − Vout
= 1. Oscillator
10 30 2. Emitter follower
−9 = 3 − Vout 3. Cascaded amplifier
−12 = − Vout 4. Power amplifier
Which of these use feedback amplifiers ?
Vout = 12V (a) 1 and 2 (b) 1 and 3
231. The circuit shown in the fig. below is a (c) 2 and 4 (d) 3 and 4
IES - 2009
Ans. (a) : Oscillator and emitter follower circuit are
used as a feedback amplifier. Most oscillators use
positive feedback.
Common-collector is also known as emitter follower.
234. In the given circuit, assume the op-amp is ideal
and the transistor has a β of 20. The current Io
(in µA) flowing through the load ZL is:

(A1 & A2 are ideal op-amps)

(a)Logarithmic Multiplier
(b)Logarithmic Amplifier
(c)Antilog Amplifier
(d) None of the above
ISRO Scientist Engg.-2018
Ans.(c): For antilogarithmic amplifier,
 1  R1 
V0 = RI f anti log  − Vs .  
 ηVT  R 1 + R 2   (a) 100 (b) 200
(c) 300 (d) 400
V0 = k1anti log ( k 2 Vs ) OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
kT Ans. (c) : By using virtual ground concept,
Where, VT =
q V – = V+ = 2V
η = Ge (1) and Si ( 2 ) 5–2 1
IC = = mA
10.5 × 103 3.5
If = forward current
I 1
V0 ∝ Anti log Vs IB = c = mA
β 3.5 × 20
Analog Electronics 467 YCT
 1 237. The amplifier has a gain of –10 and input
IB = mA resistance of 10 kΩ. The value of Ri and Rf are
70
respectively:
 1 1 
I E = I0 = IC + I B =  +  mA
 3.5 70 
I E = 300µA
235. An Instrumentation amplifier generally uses
the following number of op-amp:
(a) 1 (b) 2
(c) 3 (d) 4
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (a) 10 kΩ and100 kΩ (b) 1 kΩ and10 kΩ
Ans. (c) : Instrumentation amplifier
(c) 5 kΩ and100 kΩ (d) 10 kΩ and 200 kΩ
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Ans. (a) :

–R f
An instrumentation amplifier is usually employed to A v = , R i = 10 kΩ , Av = –10
amplify low-level signals, rejecting noise and Ri
interference signals. R f = –A v R i
Hence the instrumentation amplifier contains 3 op-
amps. Rf = +10 × 10 kΩ
236. For the op-amp shown in the figure, the bias Rf = 100 kΩ
currents are lb1 =450 nA and lb2=350 nA. The 238. In the circuit shown below the op-amps are
values of the input bias current (lB) and the ideal. The Vout in volts is:
input offset current (lf) respectively are:

(a) 400nA and 50 nA (b) 400 nA and 100nA (a) 10 (b) 8

(c) 800 nA and 50 nA (d) 800 nA and 100 nA (c) 6 (d) 4
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Ans. (b) : Bias current and voltage- GATE-2013
Ans. (b) :

Input bias current (IB)

I +I
I B = B1 B2
2
450 + 350
= = 400nA
2
Input offset current
I io = ( I B1 – I B 2 )
Vout = [1 × 2 + 2 ] × 2 = 8V
= ( 450 – 350 ) nA = 100nA

Analog Electronics 468 YCT

239. Assume that the op-amp of the figure is ideal. if Ans. (a) :
Vi is a triangular wave, then V0 will be:

By apply nodal analysis at inverting node,

Va Va − V1
(a) Square wave (b) Sine wave + =0
R R
(c) Triangular wave (d) Parabolic wave
V1 = 2Va ……… (i)
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Apply nodal analysis at non-inverting node,
Ans. (a) : Differentiator-
Va Va − Vs
dv + =0
Vo = –RC 2R 2R
dt
Vs = 2Va ………. (ii)
From equation (i) and (ii),
Vs = V1 = 2Va
Apply nodal analysis at V1 ,
V1 − Vo V1 − Va V1
+ + =0
R R R
If Vi is a triangular wave, then V0 will be square wave. 3V1 − Va = V0
240. The following configuration is an example of V 5V
positive feedback system: V0 = 3Vs − s = s = 2.5Vs
2 2
(a) Inverting amplifier
242. The output voltage for the given circuit is
(b) Non-inverting amplifier V0 = –5V1 + 3V2. Then the value of R1 and R2 is
(c) Schmitt trigger
(d) None of these
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Ans. (c) : The Schmitt trigger or bistable multivibrator
uses positive feedback with a loop-gain greater than
unity to produce a bistable characteristic.
(a) R1 = 25 kΩ and R2 = 25 kΩ
(b) R1 = 25 kΩ and R2 = 50 kΩ
(c) R1 = 50 kΩ and R2 = 25 kΩ
(d) R1 = 50 kΩ and R2 = 50 kΩ
UPPSC ITI Principal/Asstt. Director-09.01.2022
Ans. (d) :
Positive feedback occurs because the feedback resistor
is connected between the output and non-inverting input
terminals.
241. For the circuit shown below, assume that the
OPAMP is ideal. Which one of the following is
TRUE?

Given, V0 = −5V1 + 3V2

Apply KCL,
VA − V1 VA − V0
+ ...( i )
R1 Rf
(a) V0=2.5Vs (b) Vo = Vs
VB − V2 VB  1 1  V2
(c) V0=1.5Vs (d) Vo=5Vs + = VB  + =
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I R1 R2 R
 1 R 2  R1

Analog Electronics 469 YCT

  1 1  V1 V0 Apply KCL,
VA  + − = V01 − 0 V01 − V0
 R 1 R f  R1 R f + =0 ...( ii )
1k 2k
V2
VB = ...( ii ) −1 −1 − V0
+ =0
 R1 
1 +  1k 2k
 R2  −1 − V0 = 2
R  V V0 = −3
V0 = VA  f + 1 − 1 ( R f )
 1  R1
R 244. An op - amp having input voltage Vi1 = 150µV
VA = VB virtual ground and Vi 2 = 140 µV, differential gain Ad = 4000
 Rf  and CMRR = 105, The output voltage of op -
 + 1 amp will be
R
V0 =  1  V −  R f  V …………(iii)
2   1 (a) 45.8 mV (b) 45.102 mV
 R1   R1  (c) 40.006 mV (d) 42.6 mV
1 + 
 R2  UPPSC ITI Principal/Asstt. Director-09.01.2022
Given output voltage with eqn. (iii) Ans. (c) : A d = 4000, CMRR = 105
Rf Vi1 = 150µV, Vi2 = 140µV
=5
R1
Op-amp output voltage,
250kΩ
R1 = = 50kΩ  1 V 
5 Vo = A d Vid 1 + × c
By calculating R 2 = 50kΩ  CMRR Vd 
Q Vd = 150 − 140 = 10µV,
243. Assuming ideal op-amps in the circuit shown
below, the output voltage v0 will be 150 + 140
VC = = 145µV
2
 1 145 
Vo = 4000 ×10 1 + 5 . = 4 ×104 [1.000145]
 10 10 
Vo = 40005.8 µV
Vo 40mV
245. The circuit shown below employs +ve feedback
(a) 21 V (b) -21V and is intended to generated sinusoidal
oscillations.
(c) 2V (d) -3V
UPPSC ITI Principal/Asstt. Director-09.01.2022
Ans. (d) :

If at a frequency f0, feedback factor β(f) =

In Ist op-amp, Vs(f)/V0(f) = 1/6, then to sustain oscillation at this
Apply KCL at node VA, frequency is
VA − 2 VA − V0l (a) R2 = 6R1 (b) R2 = 5R1
+ =0 ...( i ) (c) R2 = R1/6 (d) R2 = R1/5
1 2k
NIELIT Scientists- 2017
VB − 1
=0 Ans. (b) :
1
VB = 1 ( VA = VB ) virtual ground
put value equation….(i)
1– V01 = 2
V01 = –1
In 2nd op-amp,

Analog Electronics 470 YCT

 ∆Vf ( t ) 1
249. For the circuit with an ideal OPAMP shown in
β(f) = = <0 the figure, VREF is fixed.
v0 ( f ) 6
Loop gain = 1
A ⋅β = 1
[Link] is non investing mode.
R
Gain of [Link] = 1 + 2
R1
R2
6=1+
R1
R2 = 5R1 If VOUT= 1 volt for VIN=0.1 volt and VOUT=6
246. A buffer is a device that has volt for VIN=1 volt, where VOUT is measured
(a) a high input impedance and a low output across RL connected at the output of this
impedance OPAMP, the value of RF/RIN is
(b) a high input as well as output impedance (a) 5.555 (b) 2.860
(c) a low input impedance and a high output (c) 3.825 (d) 3.285
impedance GATE-2021
(d) a low input impedance as well as output Ans. (a) : Case-1
impedance When Vin = active , VREF = 0
RPCS Lect.-2011
Ans. (a) : Unity gain buffers have a high input
impedance and low output impedance. The voltage
follower is used as a buffer amplifier, isolation
amplifier, unity gain amplifier (output follows the
input).
247. Gain of 1st amplifier is 50; 2nd amplifier is 10,
then both in cascaded manner overall gain
is_______.
−R F
(a) 500 (b) 60 Then V01 = × VIN –––––(i)
(c) 40 (d) 30 R IN
AAI-2015 Case-2
Ans. (a) : Given, when VIN = 0 , VREF = active
First-stage gain ( A1 ) = 50  V × R2  RF 
Then , V02 =  REF  1 +  ––––––(ii)
and 2 amplifier gain ( A 2 ) = 10
nd
 R1 + R 2  R IN 
∴ Total gain of a two stage cascaded amplifier,
A T = A1 × A 2
= 50 × 10
= 500
248. For an OPAMP, unity gain frequency is 106 if
gain is 20, What is the Bandwidth of the op-
amp _____.
(a) 60kHz (b) 50kHz
(c) 40kHz (d) 100kHz Q From equation (i) and (ii)
NPCIL-2015 So, Total output voltage,
Ans. (b) : Given value, VOUT = V01+ V02
Unity gain frequency = 10 6
 V × R2  RF  RF
VOUT =  REF  1 + − × VIN
and gain = 20  1R + R 2  R IN  R IN
Q Gain × Bandwidth = 106 Given VREF is fixed then non inverting terminal voltage
20 × Bandwidth = 10 6 V+ is fixed.
1000000 VREF × R 2
Bandwidth = V+ =
20 R1 + R 2
Bandwidth = 50kHz For VIN = 0.1 volt, VOUT = 1V

Analog Electronics 471 YCT

  R  V × R 2  R F Then V0 = 0
1 = 1 + F  REF − × 0.1 ∴ Putting value equation (i),
 R IN   R1 + R 2  R IN
VIN − 0 VREF
RF  R  V  − =0
1+ × 0.1 = 1 + F   REF × R 2  ––(iii) R R
R IN  R IN   R1 + R 2  VIN = VREF
For VIN = 1V, VOUT= 6V
R R 251. Using a µA 741 OPAMP, a first order low pass
6 = 1 + F × 0.1 − F ×1 filter is designed to have a cutoff frequency of
R IN R IN
1kHz. If the value of the capacitance used is
RF
6 = 1+ ( 0.1 − 1) 1nF, find the value of R.
R IN (a) 159.15 kΩ (b) 160.87 kΩ
5 =
RF
× ( −0.9 ) (c) 172.42 kΩ (d) 127.78 kΩ
R IN UPPCL AE-05.11.2019
RF −5 Ans. (a) : Cutoff frequency of filter is given by
So, = = −5.55
R IN 0.9 1
fc =
RF 2π ⋅ R 2 C
or = 5.55
R IN 1
R2 =
250. Consider the circuit with an ideal OPAMP 2πf c ⋅ C
shown in the figure.
1
R2 =
2π × 10 × 1× 10−9
3

1000 500
R2 = kΩ = kΩ
2π π
R 2 = 159.15kΩ
252. The reason for using a precision OPAMP based
rectifier diode for detecting weak AM signals is
that.
(a) the demodulation is easy
(b) the signal is amplified and power is less.
(c) the noise is less and easy to filter
Assuming VIN << VCC and VREF << VCC , the (d) the cut-in voltage of the diode is reduced.
condition at which VOUT equals to zero is UPPCL AE-05.11.2019
(a) VIN=0.5 VREF (b) VIN=2+VREF
Ans. (d) : The major limitation of conventional
(c) VIN=2VREF (d) VIN=VREF
rectifier is that it cannot rectify AC voltage below a
GATE-2021
forward voltage drop of diode. So the precision rectifier
Ans. (d) : makes it possible to rectify the input voltage of a very
small magnitude, even less than the forward voltage
drop of the diode.
253. An OPAMP RC phase shift oscillator has three
pairs of R and C ( R = 22kΩ,C = 10pF ) . Find
the frequency of oscillation.
(a) 356.12 kHz (b) 312.98 kHz
In Ideal case , AV = ∞ (c) 512.62 kHz (d) 295.34 kHz
V+ = V– (Virtual ground)
So, using virtual condition, UPPCL AE-05.11.2019
Vx =VY = 0 1
Ans. (d) : f =
Apply KVL at node X, 2πRC 6
VIN − 0 −VREF − 0 0 − V0 1
+ = ––––––(i) ⇒f =
R R RF 2π × 22 × 10 × 10 × 10 −12 6
3

Q Given = 0.0029548946×108
VIN << Vcc and VREF << Vcc f = 295.3 KHz

Analog Electronics 472 YCT

254. A simple single OPAMP inverting amplifier Ans. (a) :
has R F = 220kΩ and R1 = 10k. If two such
stages are cascaded, find the mid frequency
gain of the cascade.
(a) 53.70 dB
(b) -53.70 dB
(c) -26.85 dB
(d) 26.85 dB
UPPCL AE-05.11.2019
R f −220
Ans. (a) : A V1 = = ⇒ A V = −22
R1 10
When two amplifier are cascaded, their gain will be
multiplied
Two input balance difference amplifier
A V = A V1 ⋅ A V2 = −22 × −22 Difference Amplifier:-A differential amplifier is one
A V = 484 whose output is the difference between its two input
signals
In dB = 20 log10 484 = 20 × 2 ⋅ 684 Vo ∝ Vin1 − Vin 2
= 53.70dB Vo = A d ( Vin1 − Vin 2 )
255. A second order RC low pass filter is using 257. In order for an output to swing above and
OPAMP and two pairs of R and C. If the cutoff below a zero reference, the op-amp circuit
frequency is 2.2kHz, and the value of requires−
capacitance is 22 nF, find the value of R. (a) A negative and positive supply
(b) A wide bandwidth
(a) 4.7 k Ω
(c) Zero offset
(b) 3.3 k Ω (d) A resistive feedback network
(c) 2.2 k Ω RRB JE-01.09.2019, 3:00 PM – 5:00 PM
(d) 1.0 k Ω Ans. (a) : To get zero voltage at the output terminal for
this a small amount of DC voltage has to be used at the
UPPCL AE-05.11.2019
input which can be positive or negative. This method is
Ans. (b) : For second order RC low pass filter- called off-set null method.
1 258. In a OPAMP differential mode gain is 20,000
f= CMRR is 40dB common mode gain is
2π R 1 ⋅ R 2 C1C 2
(a) 200 (b) 0
C1 = C 2 = C & R 1 = R 2 = R (c) 300 (d) 400
1 BEL-2015
f= Ans. (a) : Given that
2πRC
A d = 20000
1
R= CMRR = 40dB
2πfC
A
R=
1 CMRR = 20log d
2π × 2.2 × 103 × 22 × 10−9 Ac
20000
R = 3.3kΩ 40 = 20log
Ac
256. A circuit whose output is proportional to the 20000
difference between the input signals is A c = 100
considered to be which type of amplifier?
A c = 200
(a) Differential
(b) Common-mode 259. OP-AMP used as a tuned amplifier, the tuned
circuit connected across
(c) Operational (a) input (b) output
(d) Darlington (c) series impedance (d) feedback impedance
RRB JE-01.09.2019, 3:00 PM – 5:00 PM BEL-2015

Analog Electronics 473 YCT

Ans. (d) : Op-amp used as a tuned amplifier, the tuned 263. Find V0
circuit connected across feedback impedance (Zf).
Tuned amplifier are commonly used to separate a
desired frequency from a composite waveform.
260. In an Op-Amp Ad = 80dB, CMRR = 40dB, Ac
in dB
(a) 40 (b) –40 (a) –100V (b) 111V
(c) 20 (d) 60 (c) 100V (d) –89V
SAIL- 2014 SAIL- 2014
Ans. (d) :
Ans. (a) : Given value
Ad = 80dB, CMRR = 400dB
Q CMRR(dB) = Ad(dB)–AC(dB)
AC (dB) =80 – 40
AC(dB) = 40 dB

NOTE:- → CMRR =
Ad In Ideal op-amp, AV = ∞
AC V+ = V– (virtual ground)
So, VA =VB = 1V
A
→ CMRR (dB) = 20log10 d Apply Nodal analysis point A,
AC 10 − VA VA − V0
=
261. Imax= 32pA, C= 6 µF, SR in µV/Sec? 1kΩ 10kΩ
(a) 5.33 (b) 5.33×10 3
10 − 1 1 − V
= 0
(c) 1.9×103 (d) 1.9×109 1 10
SAIL- 2014 90 = 1–V0
V0 = –89V
Ans. (a) : Given that, I max = 32pA 264. If the OP-AMP shown in the figure below is
C = 6µF ideal, then the output voltage Vout will be equal
to
dV
I max = C
dt
I max dV
=
C dt
dV 32 × 10−12
= = 5.33 ×10−6
dt 6 × 10−6
dV
S.R. = = 5.33 µV sec (a) 17V (b) 1V
dt (c) 6V (d) 14V
262. Find gain of a non-inverting Amplifier, BPSC Polytechnic Lecturer-2014
Ans. (c) :
if Vi = 1 V, RF = 10kΩ, Ri = 1kΩ.
3
(a) 10 (b) 10
(c) 11 (d) ∞
SAIL- 2014
Ans. (c) : For non-inverting amplifier.
Vo  R 
= 1 + f  Q Output voltage in op-amp
Vi  R in 
 5  1+ 5  8×3
Given that, R i = 1kΩ R F = 10kΩ Vi = 1V V0 = −2 ×   +  ×
 1   1  1+ 8
Vo  10 
Av = = 1 +  8
Vi  1  V0 = − 2 × 5 + 6 ×
3
A v = 11 V0 = –10+16
V0 = 6V

Analog Electronics 474 YCT

265. The zero level detector is one application of a Given circuit configuration – Inverting because input is
(a) Comparator connected to the inverting terminal.
(b) Summing amplifier Gain in op-amp at inverting terminal,
(c) Integrator V R
(d) Differentiator AV = 0 = − 2
Vs R1
RRB SSE 02.09.2015, Shift-II
269. Slew rate of the op amp (S) is ______(f is
Ans. (a) : The zero level detector circuit is an important operating frequency and Vm is the output
application of the op-amp comparator circuit. voltage amplitude):
266. A low-pass filter circuit is basically (a) 2πfVm (b) 2πf/Vm
(a) differentiating circuit with low time constant (c) 2m/2πf (d) (1/2πfVm)
(b) differentiating circuit with larger time UPMRC AM – 2020
constant GPSC Asstt. Prof. -11.04.2017
(c) an integrating circuit with low time constant UPPCL AE-16.11.2013
(d) an integrating circuit with larger time Ans. (a) : Slew rate – The maximum rate of change of
constant.
the output voltage ( V0 ) of the op-amp for each unit
TRB Poly. Lect. -2012
Ans. (d) : The filter circuit which allows only low pass time.
frequency components and blocks all other higher  dV 
frequency component is called a low pass filter. A low- SR =  0  = 2πfVm V / µ sec
pass filter circuit is basically an integrating circuit with  dt max
larger time constant. 270. A non-inverting amplifier (in closed loop)
267. A differential amplifier is invariably used in incorporates an op-amp having a gain of 1000.
the input stage of all OP-AMPs. This is done If the nominal gain is 5 then the gain error of
basically to provide OP-AMPs with a very the circuit will be:
high. (a) 5000% (b) 5%
(a) CMRR (b) bandwidth (c) 50% (d) 0.5%
(c) slew rate (d) open-loop gain. UPMRC AM - 2020
TRB Poly. Lect. -2012 Ans. (d) : Given,
Mizoram PSC IOLM-2010, Paper-II Nominal gain, A V = 5
IES-2001 and gain A = 1000
Ans. (a) : A differential amplifier is invariably used in Q Loop gain = A ⋅β
the input stage of all OP-AMPs. This is done basically
to provide OP-AMPs with a very high CMRR. 1 1
Where β = =
268. AV 5
1
∴ Loop gain = × 1000 = 200
5
Therefore, percentage error,
1
%E = ×100
(1 + loop gain )
1
= × 100
(1 + 200 )
The configuration and the gain of the above = 0.49%
circuit is _____ and _____.
%E ≅ 0.5%
R R
(a) inverting, − 2 (b) inverting, 1 + 2 271.
R1 R1
 R  R2
(c) non −  1 + 2  (d) non inverting,
 R1  R1
UPMRC AM - 2020
Ans. (a) :
The Op-amp circuit configuration is:
(a) unity gain buffer
(b) a square root amplifier
(c) a precision rectifier
(d) a logarithmic amplifier
UPMRC AM - 2020
Analog Electronics 475 YCT
Ans. (c) : Analysis the circuit diagram, Ans. (b) :
Case-I– Diode work as forward biased (Diode on)
when Vin > 0 then,
Vo = V+ = V– = Vin
It is so because the forward biased diode provide the
closed loop feedback path.
Case-II– Diode is reverse biased then Op-amp work as
Apply KCL at inverting node amplifier,
a open loop (Diode off).
0 − Vin 0 − Vo
+ =0
R in 1 Cs
0 − Vin
= CsVo
R in
Vo(s) −1
=
Vin(s ) sR in C

274. A sinusoidal input which can be reproduced in

Since, the circuit is a precision half wave rectifier. an op-amp without any distortion having slew
rate of 10π V.(µs)–1 and 5 V peak output
272. Input resistance of inverting amplifier as
amplitude, has the maximum frequency of
shown in figure with ideal op-amp is :
(a) 1 kHz (b) 1 MHz
(c) 31.42 kHz (d) 31.42 MHz
ISRO Scientist December, 2017
Ans. (b) : Given,
Slew rate = 10π V µ sec
Vm = 5V
(a) ∞ (b) zero  dV 
(c) 1 kΩ (d) 10 kΩ Q Slew rate =  o  = 2πfVm
 dt max
MPSC HOD Govt. Poly. -2013
10π
Ans. (c) : = 2π × f × 5
V −0 10−6
Ii = i f = 106 = 1MHz
1kΩ
Vi 275. Which of the following is NOT true for Schmitt
= 1kΩ Trigger ?
Ii
(a) Schmitt trigger can be used as sine-to-square
R in = 1kΩ wave converter
273. What is the transfer function of the following (b) Schmitt trigger uses op-amp in open loop
circuit? mode
(c) Hysteresis exists in Schmitt trigger
(d) All of these
ISRO Scientist December, 2017
Ans. (b) : A Schmitt trigger is a comparator circuit
with hysteresis implemented by applying positive
feedback to the non-inverting input of a comparator or
Vout ( s ) −1 Vout ( s ) −1 differential amplifier and Schmitt trigger uses
(a) = (b) =
Vin ( s ) R in C Vin ( s ) sR in C operational amplifier in closed loop with a positive
V (s) V (s ) feedback.
−s 1
(c) out = (d) out = 276. For the following circuit, determine the output
Vin ( s ) R in C Vin ( s ) sR in C
voltage V0 in terms of input voltages V1 and V2,
NLC GET -24.11.2020 assuming A1 and A2 are ideal op-amps.
Analog Electronics 476 YCT
 Virtual ground concept-
RB
V1 = V2 = × V0 …………………(i)
RA + RB
V1
Iin = , V1 = Iin × R s
Rs
from equation (i) put the value of V1
RB V
Iin = × 0
(a) 11V2 − V1 (b) V2 − 11V1 R A + R B Rs
(c) 11( V2 − V1 ) (d) None of these  R 
V0 = Iin R s 1 + A 
ISRO Scientist December, 2017  RB 
Ans. (c) : Output voltage at inverting node-
278. The voltage gain versus frequency curve of an
 R  op-amp is shown in the figure. The gain
Vo = 1 + f  Vi
 R1  bandwidth product of op-amp is
In first op-amp,
 1 11
V01 = 1 +  V1 = V1 ……… (i)
 10  10
In second op-amp,
 −10   10 + 1 
V02 =   V01 +   V2 ……(ii)
 1   1  (a) 200 Hz (b) 200 MHz
From equation (i) and (ii) (c) 200 kHz (d) 2 MHz
−10 11  10 + 1  LMRC AM (S&T)-13.05.2018
Vo = × V1 +   V2 IES-1999
1 10  1 
= −11V1 + 11V2 Ans. (c) : Given value,
= 11( V2 − V1 ) Gain = 80dB = 104
Bandwidth = 20Hz
277. In the following circuit, find the output voltage
V 0: ∴ Gain bandwidth product = 20 ×104
= 200kHz
279. In the op-amp circuit shown below (assuming
ideal op-amp)

(a) ( R A R B ) × Iin × R s
(b) Iin × R s × (1 + R A / R B )
(c) ( R B / R A ) × Iin × R s
(d) Iin × R s × (1 + R B / R A )
ISRO Scientist December, 2017 (a) Vo = –5V (b) Vo = 0 V
Ans. (b) : (c) Vo = +5V (d) Vo = –2V
LMRC AM (S&T)-13.05.2018
IES-2003
Ans. (b) : Ideal op-amp, A V = ∞, V+ = V– virtual
ground.

At node 2-
RB
V2 = × V0
RA + RB

Analog Electronics 477 YCT

output voltage in op-amp , Ans. (c) : Given
 22   22   22 
V0 = −0.5 ×   + 1 + ×  × 0.5
 2.2   2.2   2.2 + 22 
11× 11
V0 = −5 + = −5 + 5
24.2
V0 = 0V
280. For a voltage follower circuit using an op-amp, Q Diode connected in op-amp feedback reverse bias so,
which of the following is true ? Output voltage in op-amp Vo = 0
(a) both input and output impedance are very
because diode not conduct or behave as a open circuit.
large
(b) input impedance is very large and the output 283. The voltage at the output of the circuit shown
impedance is very small below will be
(c) input impedance is very small and the output
impedance is very large
(d) both input and output impedance are very
small
Mizoram PSC IOLM-2018, Paper-II
Nagaland PSC (Degree)-2018, Paper-II
Nagaland PSC CTSE (Diploma)-2017, Paper-I
Mizoram PSC Jr. Grade-2015, Paper-II
(a) zero (b) +VCC
RPSC Lect.2011
BSNL(JTO)-2002, 2001
(c) triangular wave(d) square wave
BSNL(JTO)-2002, 2001
Ans. (b) : Voltage follower circuit characteristics–
Input Impedance = High Ans. (a) : Output voltage in given operational
Output Impedance = Low amplifier Vo = 0V
Current gain = High 284. The input Vi to the circuit shown in figure
Power gain = High below is a square wave of amplitude ± 1 V and
=
Voltage gain Unity frequency 100 Hz.
Voltage follower used in buffer amplifier, isolation
amplifier, unity gain amplifier.
281. An op-amp based inverting amplifier has a
gain of -10 and a bandwidth of 100 kHz. If the
gain of the amplifier is reduced to unity, its
bandwidth will changes to
(a) 10 kHz (b) 100 kHz
(c) 1 MHz (d) 10 MHz Assuming ideal components, the peak-to-peak
BSNL (JTO)-2001 amplitude of the output V0 is :
Ans. (c) : Gain × Bandwidth = Constant (a) 2 V (b) 5 V
Then, (Gain)1× (Bandwidth)1= (Gain)2×(Bandwidth)2 (c) 10 V (d) 12 V
DRDO-2009
10 × 100 × 103
(Bandwidth)2 = = 106 = 1MHz Ans. (c) :
1
282. When the diode is ideal in the circuit shown
below, the output voltage will be close to

the peak-to-peak amplitude of output voltage.

V 1
(a) 0.7 volts (b) +5 V V0 = =
fRC 100 × 1000 × 10−6
(c) 0 volts (d) -VCC
V0 = 10Volt
BSNL (JTO)-2001
Analog Electronics 478 YCT
285. An inverting amplifier is designed for a gain of Ans. (d) : The gain at the centre frequency for the band
40 dB using an op-amp having open loop gain pass filter,
of 250000 and unity-gain frequency of 750 1
KHz. The bandwidth of the designed amplifier f =−
R1 C2
is : +
R 2 C1
(a) 2.5 kHz (b) 7.5 kHz
(c) 750 kHz (d) 250 kHz 288. For the Schmitt trigger circuit shown in figure,
DRDO-2009 assuming diodes and op-amp are ideal, the
Ans. (b) : Given value, value of lower and upper threshold points of
20 log10 A V = 40dB voltage transfer characteristics, respectively,
are
log10 A V = 2
A V = 100 Q Gain × BW = 750 ×103
750 × 103
B.W =
100
= 7.5kHz
286. Assuming ideal op-amps and that the op-amp
U2 is not saturated, the output voltage
waveform in the circuit shown in figure below
is a :

(a) –8 V, +5 V (b) –5 V, +5 V
(c) –5 V, +8 V (d) –8 V, +8 V
BSNL(JTO)-2009
(a) pulse (b) sine wave Ans. (c) : Given,
(c) triangular wave (d) square wave
DRDO-2009
Ans. (c) : Given circuit, in first op-amp, sine wave
converted into square wave. In second op-amp, square
wave converted into triangular wave because second
op-amp is integrator circuit or feedback op-amp across
capacitor.
287. The gain at the centre-frequency for the band
pass filter shown in figure shown in figure
below is :
(1) When Vo = Vsat = +10V
D1 = OFF and D 2 = ON
2
then VUTH = ×10 = 8V
2 + 0.5
(2) When Vo = Vsat = −10V
D1 = ON and D 2 = OFF
R 1C1 R 2 C2 2
(a) − (b) − VLTH = × ( −10 ) = −5V
R 2 C2 R 2 C2 2+2
R C  1 289. The circuit shown in figure oscillates at an
(c) −  1 + 2  (d) −
 R 2 C1  R1 C 2 angular frequency of ω at a particular R. The
+
R 2 C1 values of ω (in rad/sec) and R (in kΩ),
DRDO-2009 respectively, are

Analog Electronics 479 YCT

 291. For the given figure, the output voltage is

Rf  R + Rf 
(a) V0 = − V2 +  V1 
R R
 1 + R 2 
R  R + R f  R + R f 
(b) V0 = − V2 +   V1 
Rf  R f  R 1 + R 2 
Rf  R + R f   R1 + R 2 
(a) 105 and 20 (b) 2 × 105 and 20 (c) V0 = − V2 +   V1 
R  R  R + Rf 
(c) 2 × 105 and 10 (d) 105 and 10
BSNL(JTO)-2009 Rf  R + Rf  R2 
(d) V0 = − V2 +   V1 
Ans. (a) : Given, R  R  1
R + R 2 
L = 10mH, C = 0.01µF
ESE-2021
1
Angular Frequency ω = Ans.(d) :
LC
1
ω=
10 ×10 × 0.01× 10−6
−3

ω = 105
1 5
And =
1 + R 5 + 100
100 Q Output voltage at inverting node,
R= = 20KΩ
5 −R f
V01 = × V2
290. What is the maximum closed-loop voltage gain R
that can be used when the input signal varies and output voltage at non inverting node,
by 0.2 V in 10 µs with slew rate of op-amp
 R + R f   R 2 V1 
SR = 2 V µs? V02 =  ⋅ 
 R  R1 + R 2 
(a) 40 (b) 50
(c) 80 (d) 100 So, output voltage,
ESE-2021 −R f  R + R f   R 2 V1 
Ans.(d) : Given value, V0 = V01 + V02 = V2 +   
R  R   R1 + R 2 
Vm = 0.2
292. Inside a 741 op-amp the last functional block is
t = 10µs
a
SR = 2V µs (a) differential amplifier
 dV  (b) level shifter
Q Slew rate =  0 
 dt  max (c) class-A power amplifier
dV0 (d) class-AB power amplifier
SR = = 2V µS DRDO-2008
dt
Q Input signal varies by 0.2 V in 10µS Ans. (d) : Inside a 741 op-amp the last function block is
complementary symmetry push-push amplifier or Class
d V0 dt
So, voltage gain A V = AB power amplifier.
dVi dt
293. Assume the op-amps in figure to be ideal. If the
2 input signal vi is a sinusoid of 2 V peak-to-peak
AV =
0.02 and with zero DC component, the output signal
A V = 100 v0 is a

Analog Electronics 480 YCT

 V+ = 5.001 Volt
V– = 4.999 Volt
∴ Output voltage of the op-amp.
 1 V 
V0 = A d ( V+ − V− ) 1 + ⋅ C
 CMRR Vd 
Vd = 5.001 − 4.999 = 0.002V
(a) sine wave (b) square wave V+ + V− 5.001 + 4.999
(c) pulse train (d) triangular wave VC = =
2 2
DRDO-2008 VC = 5
Ans. (d) : Given,
 1 5 
Vi = 2V peak to peak voltage Vo = 2000 × ( 5.001 + 4.999 ) 1 + ×
 1000 0.002 
 5
Vo = 2000 × 0.002 1 + 
 2
Vo = 4 [1 + 2.5] = 4 × 3.5 = 14V
295. For the circuit in figure, if the value of the
capacitor C is doubled, the duty-cycle of the
Case-I- First op-amp. It converts the sinusoidal signal output waveform v0
into a two level fixed square wave.
When V– = Vi > V+
then Vi = +12 Volt
And when, V– < V+ then Vi = −12 Volt.
Case-II- Second op-amp. It is an integrator non-linear
op-amp circuit. So, it converts square wave into a
triangular wave.
−1
RC ∫
V0 = Vid dt

(a) increases by a factor of 2

(b) increases by a factor of 1.44
(c) remains constant
(d) decreases by a factor of 1.44
DRDO-2008
RA + RB
Ans. (c) : Duty cycle = ×100
R A + 2R B
Therefore, Independent of capacitor value.
296. Assume the op-amp in the circuit of figure to
be ideal. The value of the output voltage v0 is

294. An op-amp is ideal except for finite-gain and

CMRR. Given, the open loop differential gain
Ad = 2000, CMRR = 1000, the input to the non
inverting terminal is 5.001 V and the input to
the inverting terminal is 4.999 V, the output
voltage of the op-amp is
(a) 14V (b) 24V
(c) –6 V (d) –8 V
DRDO-2008
Ans. (a) : Given value, (a) 3.2 vi (b) 4 vi
A d = 2000 (c) 9 vi (d) 10 vi
CMRR = 1000 DRDO-2008

Analog Electronics 481 YCT

Ans. (b) :

(a) 15 V (b) 27 V
(c) 13 V (d) 14 V
GATE-2022
Ans. (c) : Given circuit,

2 2
Va = × Vi = Vi
2+3 5
Then
2  9 2
V0 = Vi 1 +  = Vi ×10
5  1 5
V0 = 4Vi Case-I- V0 = +15V and
297. An ideal OPAMP circuit with a sinusoidal D1 = ON and D 2 = OFF
input is shown in the figure. The 3 dB
That capacitor charge,
frequency is the frequency at which the
magnitude of the voltage gain decreases by 3 VC = 15 × R = 5V
dB from the maximum value. Which of the
max
R + 2R
options is/are correct ? Case-II- If V0 = −12V
D1 = OFF and D 2 = ON
That, capacitor discharges
−12 × 2R
VCmin =
2R + R
VCmin = −8V
(a) The circuit is a low pass filter. So, capacitor voltage,
(b) The circuit is a high pass filter. VC = VCmax − VCmin
(c) The 3dB frequency is 1000 rad/s.
1000 VC = 5 − ( −8 )
(d) The 3 dB frequency is rad/s.
3 VC = 13V
GATE-2022, 2012 299. A circuit with an ideal OPAMP is shown. The
Ans. (b,c) : Bode plot for the magnitude (in dB) of the gain
transfer function
( A V ( jω ) = Vout ( jω ) /Vin ( jω ) ) of the circuit is
also provided (here, ω is the angular frequency
in rad/s). The values of R and C are ______.

Q Given circuit is a high pass filter.

1 1
Q ωC = = = 1000rad / sec.
R1C1 103 ×10−6 (a) R = 3 kΩ, C = 1 µF
298. For the following circuit with an ideal OPAMP, (b) R = 1 kΩ, C = 3 µF
the difference between the maximum and the (c) R = 4 kΩ, C = 1 µF
minimum values of the capacitor voltage (Vc) is (d) R = 3 kΩ, C = 2 µF
_______. GATE-2022
Analog Electronics 482 YCT
Ans. (a) : Given, Ans. (d) : At low frequency
1
ω → 0, X C =
ωC
X C = ∞ ( open circuit )

Maximum gain = 12dB

20 × log A max = 12
20log10 A m = 12
Am = 4
R2
Where A m = 1 +
R1
Apply KCL at virtual node:-
R
∴ 1+ 2 = 4 ⇒ R 2 = 3R1 0 − Vi 0 − V0
R1 +0+ =0
1kΩ 100 kΩ
R 2 = R = 3 ×1
V0 −Vi
R = 3kΩ =
100 K 1K
Q log10 ωc = 3
V0 = −100Vi
ωc = 103
ωc = 1000 rad sec. V0
= −100
Vi
1
Q ωc = V0
R 3C AV = = 100
Vi
1 1
C= = AV in dB = 20 log10 AV
R 3 ωc 1000 × 1000
= 20 log10100
C = 1µF
= 40 dB
300. The main advantage in using three op-amp
instrumentation amplifier over a single stage 302. A low pass filter as shown in following figure is
op-amp differential amplifier lies in built using an operational amplifier having
(a) Higher value of CMRR unity gain bandwidth of 1 MHz. What is the
(b) Lower noise figure bandwidth of this circuit?
(c) Elimination of the need for accurate matching
of resistor
(d) Simplicity of gain adjustment
Nagaland PSC CTSE (Degree)-2017, Paper-II
Ans. (c) : The main advantage in using three op-amp
instrumentation amplifier over a single stage op-amp
differential amplifier is for elimination of the need for
accurate matching of resistor. There is no need for (a) 1 kHz (b) 10 kHz
accurate matching of resistor. (c) 100 kHz (d) 500 kHz
301. The very low frequency gain of the low pass ISRO Scientist Engg.-2013
filter shown in the given figure is
Ans. (c) : As per question diagram, circuit given is the
integrator or low pass filter.
Bandwidth is given by
1
BW =
2πRC
As given R = 10 kΩ & C = 160 PF
∴
1
(a) 10 dB (b) 20 dB BW = = 99, 472 100,000Hz
2π ×10 ×10 ×160 × 10−12
3

(c) 30 dB (d) 40 dB
= 100kHz
ISRO Scientist Engg.-2006
Analog Electronics 483 YCT
303. The probability that an electron in a metal 0 − V 0 − VC
occupies the fermi level at any temperature, at
in
+ =0
R R
any temperature.(>0K)
VC = − Vin
(a) 0 (b) 1
(c) 0.5 (d) 1.0 Again apply nodal analysis at node B,
Nagaland PSC CTSE (Degree) -2015, Paper I VB − VC + VB − Vin + VB − V0 = 0
Ans. (c) : For the fermileval equation we know R1 R2 R3
1 0 − VC 0 − Vin 0 − V0
f (E) = ( E − Ef ) KT = + + =0
1+ e R1 R2 R3
So, the probability that an electron occupy the fermi Put value,
1
level at any temperature will be = = 0.5 − ( − Vin ) − Vin − V0
1+1 + + =0
R1 R2 R3
304. For which of the following conditions, the
circuit shown below will function as precision V0 R 3 .Vin ( R 2 − R 1 )
=
full wave rectifier? R3 R 1R 2
R [Link] ( R 2 − R 1 )
V0 = if ( R 3 = R 2 )
R 1.R 2
R 2 .Vin ( R 2 − R 1 )
V0 =
R 1R 2
V
(a) R1 = R2 = R (b) R1 = R3 = R V0 = in ( R 2 − R1 )
(c) R2 = 2R1 (d) R1 = R2 = R3 R1
ISRO Scientist Engg.-2013 Q full wave- Vin for –ve half cycle,
Ans. (c) : V
V0 = in ( R 2 − R1 ) = Vin if ( V0 = Vin )
R1
R 2 − R1
=1
R1
R 2 − R1 = R1
R2 = 2R1
Condition – 305. The circuit shown represents
Positive half cycle,
D1 = open circuit D2 = short circuit
VA = VB= 0 (Virtual ground )
Apply nodal analysis at node B-
VB − Vin VB − VA VB − V0
+ + =0
R2 R + R1 R3
0 − Vin 0 − 0 0 − V0 (a) A bandpass filter
= + + =0 (b) A voltage controlled oscillator
R2 R + R1 R3
(c) An amplitude modulator
−R 3
V0 = ( Vin ) (d) A monostable multivibrator
R2 GATE-2014
If R 3 = R 2 Ans. (d) : This circuit represent mono stable
V0 = − Vin (+ve half cycle) multivibrater.
Vi can be used as a trigger input to change the output
Negative half cycle,
state. Charging of C1 capacitor will see that the circuit
D1 = Short circuit D2 = open circuit
output comes back to the original state.
VA = VB = 0 ( Virtual ground ) Application of mono stable Multivibrater
Q Apply nodal analysis at node A, (i) Pulse Generation
VA − Vin VA − VC (ii) Delay circuit
+ =0
R R (iii) gating circuit

Analog Electronics 484 YCT

 Ans. (c)
(ix) Multivibrators, Voltage
Regulators & power supply
1. What are the approximate values of t1, t2,
frequency and duty cycle of a 555 timer used as
an astable multivibrator respectively?
(Take C = 680 pF)

Frequency of IC 555 as astable

1.44
f=
( R1 + 2R 2 ) C
R1 = 1K Ω
R 2 = 1K Ω
C = 1µF
(a) 4.76 µsec, 6.997 µsec, 85kHz and 59.5% 1.44
f=
(b) 6.84 nsec, 9.997 nsec, 68 kHz and 59.5% (1 + 2 ) ×103 ×1×10−6
(c) 4.76 µsec, 6.997 µsec, 68 kHz and 68% = 480 Hz
(d) 6.84 µsec, 9.997 nsec, 85kHz and 68% 3. Using a 10 nF of capacitor, find the value of
ESE-2022 Resistor that yields an output pulse of 100 µs in
Ans. (a) : From question figure we can calculate the 555 time based monostable multvibrator.
t1 = TC = charging time = 0.693 (RA+RB)C (a) 5.6 kΩ (b) 2.8 kΩ
(c) 9.8 kΩ (d) 9.1 kΩ
= 0.693 ( 4.7 kΩ + 10kΩ ) × 680 ×10−12
RPSC ACF & FRO 23.02.2021
= 0.693 (14.7kΩ ) × 680 ×10−12 Ans. (d) : Monostable Multi vibrator -
= 0.693 × 14.7 × 680 × 10 −9
= 6.927µ sec 6.997 µ sec
and t 2 = Td = discharging time = 0.693 R B C
= 0.693 × 10kΩ × 680 × 10 −12
= 0.693 × 10 × 680 × 10−9
= 4.705µ sec 4.76 µ sec
Now frequency of oscillation-
1 1
f= = = 85.96kHz T = RC ln (3) = 1.1 RC
t1 + t 2 6.927 + 4.705
The within of the output pulse is a function of only the
85kHz external time constant RC.
And duty cycle 100 µs = 1.1 × R × 10 × 10-9
Tc t 100 ×10−6
%D = = 1 R=
Tc + Td t1 + t 2
1.1×10 × 10−9
6.927 = 9.1 kΩ
= × 100
6.927 + 4.705 4. Calculate the frequency of following circuit
= 0.5955 × 100 = 59.5%
2. If R1=1 kΩ , R2=1 kΩ , C = 1µF, then the
output frequency of IC 555 as astable
multivibrator is:
(a) 4.8 kHz (b) 48 kHz
(c) 480 Hz (d) 48 Hz
UPRVUNL AE -19.07.2021, Shift-II
Analog Electronics 485 YCT
 (a) f = 1270 Hz (b) f =1905 Hz Where n = Number of bits
(c) f = 635 Hz (d) f = 325 Hz
RPSC ACF & FRO 23.02.2021
Ans. (c) : T = 0.693 (RA+2RB)C
T = 0.693 ( 7.5 × 103 + 2 × 7.5 × 103 ) 0.1× 10 −6
= 1.559×10-3sec
l 103
f= = 7.
Consider the following statements :
T 1.559
In order to generate square wave from a
= 641.43 Hz sinusoidal input signal one can use
635Hz 1. Schmitt trigger circuit
5. For given Schmitt trigger, find the upper 2. Clippers and amplifiers.
threshold voltage. Lower threshold voltage 3. Monostable multivibrators
(Assume : the maximum output voltage swing Which of the above statements is/are correct?
is ± 14 V) (a) 1 alone (b) 1 and 2
Vut : upper threshold voltage (c) 2 and 3 (d) 1, 2 and 3
Vlt : lower threshold voltage Nagaland PSC-2018 Diploma, Paper-II
Kerala PSC Lecturer (NCA) 04.07.2017
TRB Poly. Lect-2012, IES-2009, 2002, 2001
Ans. (a) :

(a) Vut = 2.33 V Vlt = -2.33 V

(b) Vut = 84 V Vlt =-84 V
(c) Vut = 1.4 µV Vlt = -1.4µV
(d) Vut = 7.31 V Vlt = -7.31 V
• Schmitt trigger is a comparator circuit with positive
RPSC ACF & FRO 23.02.2021 feedback. It works as an astable multivibrator. It
Ans. (a) : generates square wave form a sinusoidal wave form.
 R1   R1  • Clippers is a circuit that only clips the waveform.
Vut =   VH , Vlt =   VL But it cannot generate square wave from a
 R1 + R 2   R1 + R 2  sinusoidal wave.
 10   10  • Monostable multivibrator generates only square
Vut =   ×14, Vlt =   × ( −14) pulse from a sinusoidal wave form. It is also known
 10 + 50   10 + 50 
as pulse generator or pulse stretcher circuit.
= 2.33 V = – 2.33 V
8. An astable multivibrator has_______
6. For an N bit F-V converter, to ensure less than (a) One stable state (b) Two stable states
1/2 LSB output ripple, the time constant T of (c) No stable state (d) None of the above
simple RC low pass filter must be at least Nagaland PSC (CTSE) Diploma-2017, Paper II
(where T0 is the output period of the n bit Nagaland PSC CTSE (Degree)-2016, Paper II
converter). TNPSC AE- 2013
(a) T = 0.69 (n+1) T0 (b) T = (n +1) T0 Ans. (c)
(c) T = 0.69 nT0 (d) T = nT0
UPMRC AM - 2020
Ans. (a) : Frequency to voltage convertor-
(1) Counter can be used to generate a frequency. The
digital pulse can be averaged using low pass filter to get
voltage.
(2) To ensure less than 1/2 LSB output ripple, the time Astable multivibrators are free-running oscillators that
constant (RC) must be long enough or the output to oscillates between two states continuously producing
two square wave output waveforms. These both states
settle i.e
are not stable as it changes from one state to the other
T ≥ 0.69 ( n + 1) To all the time.

Analog Electronics 486 YCT

9. In a series regulated power supply circuit the Ans. (c) : Current following through a capacitor in an
voltage gain AV of the "pass", transistor AC circuit is displacement current because of change in
satisfies the condition electric field between plates with time.
(a) Av → ∞ (b) 1 << Av << ∞ Q Maxwell equation
(c) Av ≈ 1 (d) Av << 1 ∇ × H = jc + jD
GATE-1998
Where jC = conduction current density
Ans. (c) : VZ = VBE +V0
VBE = VZ –V0 jD = displacement current density
Since VZ is constant. jC = σE, and
∂D
jD =
∂t
∂V
Then IC = C. in capacitor.
dt
12. The approximate O/P Frequency of 555
V0 ↑→ VBE ↓→ IL ↓ I L R Z ↓→ V0 ↓ Oscillator for R A = R B = 2.2 kΩ and C=2000
and V0 ↓→ VBE ↑→ IL ↑→ I L R Z ↑→ V0 ↑ pF-
(a) 110 kHz (b) 109.3 kHz
So, V0 will be regulated
(c) 120.5 kHz (d) 108.9 kHz
for Q , Load in connected at VZ is connected at base.
ISRO Scientist Engg.-2016
V0 ≈ VZ Ans.(b)
So,
Emitter follower base. It is a common collector.
Voltage gain A V ≈ 1
So, In a series regulated power supply circuit, the
voltage AV, In a series regulated power supply circuit,
the voltage gain Av of the 'Pass' transistor satisfies the
condition.
10. In a feedback series regulator circuit, the
output voltage is regulated by controlling the
(a) Magnitude of the I/P voltage IC 555 timer acts as oscillator in astable mode,
(b) Gain of the feedback transistor Given,
(c) Voltage drop across the series pass transistor RA=RB=2.2kΩ
(d) Reference voltage Let RA = R1
ISRO Scientist Engg.-2012 RB =R2
IES-1999 C = 2000pF
Ans. (d) : Feedback series regulator- 1 2
Q During charging of capacitor from VCC to VCC ,
3 3
Then n output is high and times duration is
Thigh = 0.69 ( R 1 + R 2 ) C
And during discharging of capacitor from
2 1
VCC to VCC , the output is low and time duration is,
3 3
TLow = 0.69R 2 C
Maintains the DC output voltage of a power supply Time period (T) = TH+TL
constant respect in AC supply and variations in T = 0.69(R 1 + 2R 2 )C
load current. So, frequency of oscillator
Output does not change due to change in the load 1 1
(f) = =
voltage. (or Reference voltage) T 0.69 ( R A + 2R B ) C
11. The current flowing through a capacitor in an
AC circuit is : 100
f=
(a) Non-existent 69 × ( 2.2 + 2 × 2.2 ) ×103 × 2000 × 10 −12
(b) Conduction current
108
(c) Displacement current = Hz
(d) None of the above 13.2 × 69
ISRO Scientist Engg.-2013 = 109.79 109.8kHz

Analog Electronics 487 YCT

13. The approximate frequency of oscillation of the 16. A Schmitt trigger circuit achieves hysteresis by
circuit shown below is utilizing
(a) The magnetic properties of transformer core
(b) Avalanche multiplication in a Zener diode
(c) The Barkhausen principle
(d) Regenerative positive feedback
GPSC Asstt. Prof. 11.04.2017
Ans. (d) :

(a) 8.3 kHz (b) 16.6 kHz

(c) 7.2 kHz (d) 3.6 kHz
ISRO Scientist Engg.-2010
Vout = V+ if Vin < VL
Ans. (c) : The given circuit is an astable multi-vibrator.
V– if Vin > VH
So the frequency.
Schmitt trigger is a Comparator Circuit with hysteresis
1
f= implemented by applying positive feedback to the non
1.38RC inverting input of a Comparator amplifier.
Given, R = 10kΩ, C =0.01pF It achieves hysteresis by utilizing Regenerative
1 positive feedback.
f=
1.38 × 10 ×103 × 0.01× 10−6 17. An astable multivibrator is also called
f = 7.246 kHz (a) Free running multivibrator
(b) Edge triggered multivibrator
14. A bistable multivibrator has………… (c) Emitter coupled multivibrator
(a) Two stable states (b) One stable state (d) Collector coupled multivibrator
(c) No stable state (d) None of the above Mizoram PSC IOLM -2018, Paper II
Nagaland PSC (CTSE) Diploma-2017, Paper II Ans. (a) : In electronic circuit, astable multivibrators
Nagaland PSC (CTSE) Diploma-2018, Paper I are also known as free running multivibrators as they do
Ans. (a) : not require any additional input.
18. In which circuit duty cycle of any pulse wave is
50%
(a) Astable Multivibrator
(b) Mono-stable Multivibrator
(c) Bistable Multivibrator
(d) Schmitt trigger
UPPCL AE-16.11.2013
A type of multivibrator whose output consists of 2
Ans. (a) : Astable multivibrators generally have an even
stable states is known as Bistable multivibrator. The
50% duty cycle, that is the 60% of the cycle time the
circuit switches from one stable state to the other when
output is high and remaining 50% of the cycle time of
an appropriate trigger pulse is applied.
output is off. In other words, the duty cycle of an
15. ……………multivibrator is a square wave astable timing pulse is 1 : 1.
oscillator
19. The duration of the ON time of any pulse of
(a) Monostable (b) Astable
mono-stable multivibrator depends on
(c) Bistable (d) None of the above
(a) External R connected to the circuit only
Nagaland PSC (CTSE) Diploma-2017, Paper II (b) R and C both
Ans. (b) : An astable multivibrator is a square wave (c) External C connected to the circuit only
oscillator because it produces a continuous square wave (d) External R but not external C
from its output which can be used to flash lights or UPPCL AE-16.11.2013
produce a sound in a loudspeaker. It is a free running Ans. (b) : In monostable multivibrator, there is only one
and frequency of square wave generator independent of stable state. The duration of the output pulse is
output voltage. determined by the RC network connected externally to
Analog Electronics 488 YCT
the 555 timer. The stable state output is approximately 23. The output frequency of an astable
zero at logic low level. multivibrator using NE555 timer is given by,
1.44 1
(a) (b)
(R a + 2R b )C (R a + 2R b )C
1 1.44
(c) (d)
1.44(R a + 2R b )C (R a + R b )C
TNPSC AE-2013
Ans. (a) : The frequency of oscillation being the
reciprocal of over all time period.
T = 0.693 (Ra+2Rb) C sec.
1.44
F= Hz
20. A bleeder resistor is used in a D.C power (R a + 2R b )C
supply because it 24. What will be the period and frequency of
(a) Keeps the supply OFF oscillation for an astable multivibrator, given
(b) Keeps the supply ON the following specifications?
(c) Improves filtering action R1 = 1kΩ R2 = 5.6 kΩ C1 = 0.01 µF C2 = 0.03 µF
(d) Improves voltage regulation (a) 12.5 ms, 80 Hz (b) 1.25 µs, 800 kHz
KVS TGT (WE)- 2016 (c) 1.25 ms, 800 Hz (d) 0.125 ms, 8 kHz
TNPSC AE-2014 TNPSC AE-2013
Ans. (d) : Bleeder resistor is used in a DC power supply 1
because- Ans. (d) : f =
0.69(R 1C1 + R 2 C 2 )
• It improves voltage regulation of the supply.
• It provides safety to the technician handling the 1
f=
equipment. 0.693 (1 × 103 × 0.01× 10−6 + 5.6 × 103 × 0.03 × 10−6 )
• By maintaining a minimum current through the
1000
choke, it improves its filtering action. f= = 8196 Hz
0.69(.01 + 5.6 × 0.03)
f 8kHz
1 1
and, T = = × 10−3
F 8
= T = 0.125ms
25. Important applications of Schmitt trigger
circuit are as below :
21. A monostable multivibrator has R = 10 kΩ and (a) As an amplitude comparator
C = 1pF? What is the width of the pulse? (b) As a squaring circuit
(a) 6.3 ps (b) 6.3 ns (c) As a Flip Flop circuit
(c) 6.3 µs (d) 6.3 ms (d) All the above
TNPSC AE-2014 TNPSC AE-2013
Ans. (b) : Phase width of the pulse of monostable Ans. (d) : A Schmitt trigger circuit produce square
multivibrator, wave for sine wave input and it also used as an
T = 0.69 RC amplitude comparator and flip-flop also.
= 0.69 × 10 × 103 × 1 × 10–12 = 6.9 ns 26. What is the maximum load current that one
≅ 6.3 ns can draw from a 15 volt 3-pin regulator of the
22. Which of the following is also called as Eccles type 781.15?
Jordan Circuit? (a) 1 A (b) 0.5 A
(a) Astable Multivibrator (c) 100 mA (d) 3 A
(b) Monostable Multivibrator TNPSC AE-2013
(c) Bistable Multivibrator Ans. (c) : For 3 pin regulator the maximum current that
(d) Schmitt Trigger can flow through it is 80 mA to 100 mA - for 15 V
TNPSC AE-2014 rating.
Ans. (c) : Bistable Multivibrator– 27. What is a Schmitt trigger?
It has two absolutely stable states. It can stay in one of (a) A trigger circuit
its two states indefinitely changing to the other state (b) A comparator with Hysteresis
only when it receives as trigger pulse from outside. (c) A comparator without Hysteresis
Bistable multivibrator is also called as Eccles Jordan (d) Amplifier
circuit. RPSC LECTURER-10.01.2016
Analog Electronics 489 YCT
Ans. (b) : A Schmitt trigger is a comparator circuit with Ans. (c) : Frequency of oscillation
hysteresis implemented by applying positive feedback 1
to the non-inverting input of a comparator or differential f=
amplifiers. T
1.44
f=
( A + 2R B ) C
R
1.44
=
(10 + 2 × 10 ) × 0.1× 103 × 10−6
1.44
It is an active circuit which converts an analog input =
30 × 0.1× 10−3
signal to a digital output signal.
f = 480Hz
28. In a digital frequency meter, the Schmitt
trigger is used for f 476 Hz
(a) Converting sinusoidal waveforms into t
rectangular pulses. Duty cycle D = c × 100
T
(b) Scaling of the sinusoidal waveforms 0.693(R A + R B )C
(c) Providing time base = × 100
(d) Triggering a start pulse 0.693(R A + 2R B )C
Nagaland PSC CTSE (Degree)-2017, Paper-I
=
( R A + R B ) × 100
Ans. (a) ( R + 2R ) A B

20
= × 100
30
D = 66.66%
30. The basic important blocks of IC 555 timer
(a) Voltage source (b) Flip-flop
(c) Resistors (d) Switch
RPCS Lect.-2011
Ans. (b) : The important blocks of IC 555 timer has two
comparators, which are basically 2 operational
• A digital frequency meter is an electronic instrument amplifiers an R-S flip flop, two transistors and a
that can measure even the smaller value of frequency resistive network.
up to 3 decimals of a sinusoidal wave and displays it 31. A d.c. voltage supply provides 60 V when the
on the counter display. output is unloaded. When connected to a load,
• The main purpose of the Schmitt trigger is to convert the output drops to 56 V. the value of the
the sinusoidal wave signal into a square wave or voltage regulation is
rectangular pulse train.
(a) 3.7% (b) 5.7%
• Digital frequency meter has High sensitivity and
good frequency response. (c) 7.1% (d) 9.1%
• It does not measure the exact value. IES-2019
29. In astable multivibrator as shown in figure, if Ans. (c) : Given, No Load Voltage, VNL = 60 V
RA = RB = 10 kΩ and C = 0.1 µF, then duty Full Load Voltage, VFL = 56 V
cycle and frequency of oscillation is (select V – VFL
nearest values) : Voltage Regulation = NL × 100%
VFL
60 – 56
= ×100%
56
4
= × 100%
56
= 7.14%
32. For 555 astable multivibrator, if C = 0.01 µF,
RA=10kΩ, RB = 50kΩ, the frequency and the
(a) (50% and 300 Hz) respectively duty cycle will be nearly.
(b) (66.66% and 350 Hz) respectively (a) 1.6 kHz and 54.5% (b) 1.3 kHz and 54.5%
(c) (66.66% and 476 Hz) respectively (c) 1.6 kHz and 46.5% (d) 1.3 kHz and 46.5%
(d) (40% and 200 Hz) respectively IES-2019
MPSC HOD Govt. Poly. -2013 TNTRB AE– 2017

Analog Electronics 490 YCT

Ans. (b) : Given, RA = 10 kΩ, RB = 50 kΩ, C = 0.01 µF Ans. (b) : Voltage Regulator :-
• Voltage Regulator has a Zener Diode connected in
parallel with filter output.
• The Zener Diode is biased with reverse connection
for voltage regulation.
• Voltage Regulator is a circuit that creates and
maintains a fixed output voltage.
35. A 1 µs pulse can be converted into a 1 ms pulse
by using
(a) A monostable multivibrator
(b) An astable multivibrator
(c) A bistable multivibrator
(d) A J-K flip-flop
APGENCO AE-23.04.2017
IES-2014, 2007, 2000,1999, 1995
Frequency of A stable multivibrator Ans. (a) : Monostable multivibrator-
1.44 • It has only one stable state.
f= • It is also known as single shot or one shot
( R A + 2R B ) C multivibrator.
1.44 • It is used as delay and timing circuits.
=
(10 + 2 × 50 ) ×103 × 0.01×10 –6 • It converts 1 µs pulse into a 1 ms pulse so it is called
f = 1.3 kHz a pulse stretcher circuit.
Duty cycle of A stable multivibrator • It is also used for temporary memories.
RA + RB 36. A monostable multivibrator is frequently used :
D= × 100% (a) In memory and timing circuit
R A + 2R B
(b) For regeneration of distorted waves
10 + 50 (c) In counting circuits
= ×100%
10 + 2 × 50 (d)For producing triangular waves
60 KVS TGT (WE)- 2016, IES-2013
= × 100% Ans. (b) : Used of monostable multivibrator :-
110
D = 54.54%. • Monostable multivibrator is used in analog systems
to control an output signal frequency.
33. Consider the following statements regarding
linear power supply : • It can consider as triggered pulse generators.
1. It requires low frequency transformer. • It used for the generation of clock pulse and the
regeneration of distorted waves.
2. It requires high frequency transformer.
• It is called a pulse stretcher circuit because it
3. The transistor works in active region.
increases the width of a pulse.
Which of the above statements is/are
correct? 37. The frequency of oscillation of astable
multivibrator with component values R1 = 2kΩ,
(a) 1 only (b) 2 and 3 only
R2 = 20kΩ, C1 = 0.01 µF and C2 = 0.05 µF is:
(c) 1 and 3 only (d) 3 only (a) 1428.5 Hz (b) 142.85 Hz
IES-2016 (c) 14.285 Hz (d) 1.4285 Hz
Ans. (c) : Features of Linear Power Supply :- IES-2013
• Required a step-down low-frequency transformer and Ans. (a) : Given, R1 = 2 kΩ, C1 = 0.01 µF, C2 = 0.05 µF
high the input voltage and frequency both. Frequency of oscillation of a stable multivibrator
• Required the voltage across the load does not vary. 1
• Transistor should operate in the active region so that f=
0.69 ( R 1C1 + R 2 C 2 )
the desired amplification is achieved.
34. In a voltage regulator, zener diode is 1
=
1. Connected in series with filter output (
0.69 2 × 10 × 0.01 × 10 + 20 × 103 × 0.05 ×10 –6
3 –6
)
2. Forward biased 1
=
3. Connected in parallel with filter output
4. Reverse biased
(
0.69 20 × 10 –6 + 1000 × 10 –6 )
Which of the above are correct? 106
=
(a) 1 and 2 (b) 3 and 4 703.8
(c) 1 and 4 (d) 2 and 3 f = 1420.85 Hz
IES-2015 f 1428.5Hz

Analog Electronics 491 YCT

38. In order to obtain repetitive pulses of unequal Ans. (b) : The circuit shown above is a mono-stable
mark space one can use : multivibrator.
1. A voltage comparator fed with a triangular • IC 555 mono-stable multivibrator works as a
wave signal and DC-voltage. frequency divider circuit.
2. An astable Multivibrator • Monostable multivibrator used in pulse width
3. A mono-astable Multivibrator fed with square modulation.
wave input. • It acts as a Linear Ramp Generator.
Which of these statements are correct? • It can be used to drive a relay.
(a) 1 and 3 only (b) 1 and 2 only 41. Consider the following statements about a good
(c) 2 and 3 only (d) 1, 2 and 3 power supply :
IES-2011 1. The a.c. ripple should be high.
Ans. (d) : To obtain repetitive pulses of unequal mark 2. SV' (Voltage stability factor) should be low.
space, we can use – 3. ST' (Temperature stability factor) should be
• An astable multivibrator without any trigger input. low
• A monostable multivibrator fed with a square wave Which of the above statements are correct?
input. It can produce one stable output by triggered (a) 1, 2 and 3 (b) 2 only
input. (c) 3 only (d) 2 and 3 only
• Voltage comparator having triangular wave signal IES-2009
and DC voltage. Ans. (d) : Specifications of a good power supply-
39. Consider the following statements : • In a good power supply AC ripple should be low.
1. A Schmitt trigger circuit can be emitter • Voltage stability factor (SV) and Temperature
coupled bistable circuit. stability factor (ST) both should be low in a good
2. Schmitt trigger circuit exhibits hysteresis power supply.
phenomenon. • The power supply must always be voltage regulated
3. The output of Schmitt trigger will be and be able to hold a fixed voltage output over a
triangular if the input is square wave. range of loads.
Which of these statements are correct? 42. Which one of the following is a regulated power
(a) 1, 2 and 3 (b) 1 and 2 only supply?
(c) 2 and 3 only (d) 1 and 3 only (a) IC 555 (b) IC 844
IES-2011 (c) IC 3080 (d) IC 723
IES-2009
Ans. (b) : Schmitt Trigger :-
Ans. (d) :
• Schmitt trigger is a comparator circuit with
hysteresis implemented by positive feedback which
gives a Bi-stable output.
• Schmitt trigger shows different characteristics for
increasing and decreasing value of the input. This
property is known as the hysteresis phenomenon.
• The output of Schmitt trigger will be a square wave
for any input.
• From the emitter-coupled Bi-stable circuit. We can
get the property of a Schmitt trigger circuit.
40. The circuit shown above is :

IC 723 :-
• IC 723 voltage regulator is used for series voltage
regulator applications.
• It can be used as both positive and negative voltage
regulator.
• IC 723 can also be used as a temperature controller,
current regulator or shunt regulator.
• It is available in both Dual – In – Line and metal
cane packages.
43. Narrow pulses with adjustable mark to space
(a) Bi-stable multi-vibrator ratio can be obtained from square wave input
(b) Mono-stable multi-vibrator signal by using which of the following?
(c) Free running multi-vibrator 1. Schmitt trigger.
(d) Ramp generator 2. Monostable multivibrator
IES-2010 3. Clippers
Analog Electronics 492 YCT
 Select the correct answer using the code Ans. (d) : Series Transistor Feedback Voltage
given below : Regulator :-
(a) only 1 (b) only 2 • It is also called the series pass regulator and used in
(c) 1 and 2 (d) 2 and 3 linear regulated power supply.
IES-2006 • In this type of Regulator, the regulation factor can be
Ans. (b) : Monostable multivibrator is a circuit used as improved by increasing the low of the shunt transistor
pulse Generator. It is able to changes pulse width of and by increasing the resistance between the collector
signals. of the shunt transistor and the collector of the series
So, Narrow pulses with adjustable mark to space ratio transistor.
can be obtained from square wave input signal by using
monostable multivibrator.
44. Match List-I (Application of the circuit) with
List-II (Circuit Name) and select the correct
answer using the code given below the lists :
List-I List-II
A. Divider 1. Astable
multivibrator
B. Clips input voltage at 2. Schmitt trigger
two predetermined
Levels
C. Square wave generator 3. Bistable • Transistor, In transistor series voltage regulator
multivibrator behaves like a variable resistor.
D. Narrow current 4. Blocking • The output resistance can be reduced by using a
pulse generator oscillator Darlington pair in place of the series transistor.
A B C D • Output resistance cannot be reduced by reducing the
(a) 4 2 1 3 hfe of the shunt transistor.
(b) 3 2 1 4 46. Consider the following circuit :
(c) 4 1 2 3
(d) 3 1 2 4
IES-2009, 2004
Ans. (d) : Astable multivibrator :- It is an electronic
circuit that has not stable states. It clips input voltage of
two predetermined levels.
Schmitt Trigger :- It is regenerative comparator that Which one of the following expressions for V0 is
employs positive feedback and converts sinusoidal input correct?
into a square wave output.  R1 + R 2 
Bistable multivibrator :- It is also known as Flip-Flop (a) V0 = Vz  
multivibrator. It is widely used in latches and counters.  R + R1 + R 2 
It is also used in frequency divider circuits and in (b) V0 = AVz
storage devices.
 R 
Blocking Oscillator :- It is a waveform generator that (c) V0 = AVz  1 + 1 
is used to produce narrow current pulses or trigger  R2 
pulses. It blocks the feedback, after a cycle, for certain
predetermined time while it having the feedback from  R1 + R 2 
(d) V0 = AVz  
the output signal.  R + R1 + R 2 
45. Which one of the following statements is not IES-2003
correct in respect of a series transistor Ans. (c) :
feedback voltage regulator?
(a) The regulation factor can be improved by
increasing the hfe of the shunt transistor
(b) The regulation factor can be improved by
increasing the resistance between the
collector of the shunt transistor and the
collector of the series transistor. Apply voltage divider rule,
(c) Output resistance can be reduced by using a
Darlington pair in place of the series  R2 
AVz = V0  
transistor.  R1 + R 2 
(d) Output resistance can be reduced by reducing
 R 
the hfe of the shunt transistor. V0 = AVz  1 + 1 
IES-2004  R 2 

Analog Electronics 493 YCT

47. Match List-I (Circuit Name) with List-II Ans. (c) T = RC ln(3)
(Characteristics) and select the correct answer T = 1.1 RC
using the code given below the lists :
List-I List-II
A. Schmitt trigger 1. It need a pulse
transformer
B. Monostable 2. It is used to
Multivibrator generate gating
pulse whose
width can be
controlled
C. Astable 3. It is a bistable
multivibrator circuit 50. Which one of the following sets of circuits can
D. Blocking oscillator 4. It has no stable be obtained by using a 555 timer ?
state (a) Pulse modulator and amplitude demodulator
Codes : (b) Pulse modulator and astable multivibrator
A B C D (c) Amplitude demodulator and AC to DC
(a) 3 2 4 1 converter
(b) 2 3 1 4 (d) AC to DC converter and astable multivibrator
RPSC Vice Principal ITI-2016
(c) 3 2 1 4
IES-2000
(d) 2 3 4 1
Ans. (b) : Pulse Width Modulator (PWM) using 555
IES-2003
Timer :-
Ans. (a) :
• Schmitt Trigger behaves as a Bi-stable circuit.
• Monostable multivibrator is a pulse generator circuit.
• A stable multivibrator has no stable states. It has two
quasi-stable states.
• A blocking oscillator is a wave-form generator that is
used to produce narrow pulses. It needs a pulse
transformer.
48. The function of the diode D in the timer circuit
shown below is to

Astable multivibrator using 555 Timer :-

(a) Increase the charging time of C.

(b) Decrease the charging time of C.
(c) Increase the discharging time of C.
(d) Decrease the discharging time of C.
IES-2003
Ans. (d) : In the above given timer circuit, Diode ‘D’ is
connected in forward bias. The capacitor ‘C’ will
charge through the resistance (RA+RB). Due to forward
biasing of Diode ‘D’, the capacitor will discharge by
diode ‘D’ instead of resistance RB and discharging time Hence, pulse modulator and Astable multivibrator
of capacitor ‘C’ will decrease. circuit can be obtained by using a 555 timer.
49. What is the time period of a monostable 555 51. For the high-pass circuit to act as a
multivibrator? differentiator, the time constant must be
(a) T = 3RC (b) T = RC (a) Small
(c) T = 1.1RC (d) T = 0.33RC (b) Very small in comparison to the time period
RRB JE- 31.08.2019, 10 AM-12 PM of the input signal

Analog Electronics 494 YCT

 (c) Very high in comparison to the time period of Ans. (c) : Use of commutating capacitors in a bi-
the input signal (that is low pass circuit) stable multivibrator –
(d) Moderate value
TNPSC AE-2013
IES-1999
Ans. (b) : High-Pass Filter Circuit as Differentiator–

The output of a HPF circuit at low frequency will be

zero but at high frequency the value of output will be
infinite. This property is same as a differentiator circuit.
(τ = RC)
When the time constant of the HPF is smaller than the
Bi-stable multivibrator has two stable states. It is known
time period of the input signal then the circuit acts as a
as flip-flop. R1 and R2 are feedback resistors and are
differentiator. RC << T connected in parallel with C1 and C2 respectively.
A differentiator circuit produces a constant output Capacitor C1 and C2 are commutating capacitors. These
voltage when the input applied tends to change steadily. are also known as speed-up commutating capacitors.
52. A second-order band-pass active filter can be They reduce the transition time (time taken for the
obtained by cascading a low-pass second-order transfer).
section having cut-off frequency fOH with a Hence, commutating capacitors (C1 & C2) are used in a
high-pass second-order section having cut-off Bi-stable multivibrator to increase the speed of
frequency fOL, provided response.
(a) fOH > fOL (b) fOH < fOL 54. Higher order active filters are use for variable
(a) Bandwidth
(c) fOH = fOL (d) f OH ≤ 1 f OL (b) Gain in the pass-band
2
IES-1999 (c) Impedance
(d) Roll-off rate
Ans. (a) : Band-Pass Active Filter – A second order
band-pass active filter allows frequencies within a IES-1998
specific frequency range and attenuates the other Ans. (d) : Higher Order Active Filters : Higher order
frequencies. active filters can be obtain by cascading a proper
Low –pass filter isolates the frequencies higher than the number of first and second order filters. Higher order
cut-off frequency but High-pass filter isolates the active filters are used for variable Roll-Off rate.
frequencies lower than the cut-off frequency. The rate at which gain changes is called roll-off rate. It
By cascading a High pass second-order filter and Low- is expressed in dB/octave or dB/decade.
Pass second-order filter, we can make a second order 55. Consider the following statements :
band-pass active filter. The 555 timer can be employed in
The condition for getting a Band-Pass the cut-off 1. A monostable multivibrator
frequency (fOH) of low-pass second-order filter must be 2. A bistable multivibrator
greater than the cut-off frequency (fOL) of High-pass 3. An astable multivibrator
second-order filter. Of these statements
fOH > fOL (a) 1 and 2 are correct
53. In a bistable multivibrator, commutating (b) 1 and 3 are correct
capacitors are used to (c) 2 and 3 are correct
(a) Increase the base storage charge (d) 1, 2 and 3 are correct
(b) Provide a.c. coupling IES-1996
(c) Increase the speed of response Ans. (d) : The 555 timer can be employed An astable
(d) Alter the frequency of the output multivibrator monostable multivibrator and bi-stable
IES-1998 multivibrator –

Analog Electronics 495 YCT

Astable multivibrator – • Monolithic regulator allows to create a stabilized
power supply.
• 78XX series of monolithic linear regulators (for
positive voltage) and 79XX (for negative voltage).
• It is used to introduce flexibility in setting output
voltage level.
• To maintain a constant output voltage. It can adjust
the device resistance.
57. Consider the following statements:
In a series transistor regulator, the regulation
factor and output resistance can be improved
by
1. Increasing hfe of the series transistor
2. Increasing hfe of the shunt transistor
Monostable multivibrator :- 3. Increasing the external resistance R connected
between the collector and base of the series
transistor.
Of these statements
(a) 1 and 2 are correct
(b) 2 and 3 are correct
(c) 1 and 3 are correct
(d) 1, 2 and 3 are correct
IES-1996
Ans. (a) : Series transistor regulator :-

Bi-Stable Multivibrator :-

• In this regulator transistor acts as control element

and it is connected in series with the load (RL).
Therefore it is called series voltage regulator.
• The regulation factor and output resistance can be
improved by increasing hfe of the series transistor
and hfe of the shunt transistor respectively.
Limitation :-
• Output voltage can not maintain absolutely because
VBE and VZ decrease with increase room
temperature.
• Output voltage cannot be changed as there is no
provisional it in the circuit.
56. Consider the following statements:
Monolithic regulators can be used to • It can not provide good regulation at high current.
1. Realize a constant voltage regulator • It has poor ripple factor with respect to input
2. Realize a constant current regulator. variation.
3. Introduce flexibility in setting output voltage 58. The given figure shows the application of 555
level. timer circuit as an astable multivibrator. The
charging and discharging, time constants are
Of these statements
respectively
(a) 1 and 2 are correct
(b) 1 and 3 are correct
(c) 2 and 3 are correct
(d) 1, 2 and 3 are correct
IES-1996
Ans. (b) : Monolithic Regulator :-
• Monolithic Regulator is also known as integrated
Regulator. It is a linear voltage regulator.

Analog Electronics 496 YCT

 (a) R1 C and R2 C
(b) R1 C and (R1 + R2) C
(c) (R1 + R2) C and R1 C
(d) R2 C and R1 C
IES-1995
Ans. (c) : Of these statements :
(a) 1, 2 and 3 are correct (b) 1 and 2 are correct
(c) 2 and 3 are correct (d) 1 and 3 are correct
IES-1994
Ans. (b) : The given circuit is a High-Pass filter.
Time constant of High-Pass RC filter τ = RC
• When the time constant of a high-pass RC circuit is
very small as compare to the time period, the circuit
will act as a differential circuit. RC << T
At this condition the output V0 will consist of a positive
and negative spike.
From the given 555 time circuit diagram. The
Resistance (R1+R2) will charge the capacitor (C). The • When the time constant is very large as compare to
capacitor (C) will discharge through resistance R1. So, the time period, the impedance (XC) of the circuit
will be very small. RC >> T
the charging time of the capacitor (C)
At this condition the output V0 will equal to the input Vi
Tc = ( R 1 + R 2 ) C , (V0 = Vi).
and the discharging time, 61. Match List-I with List-II and select the correct
Td = R 1C answer using the code given below the lists :
List-I List-II
59. The circuit shown in the given figure is : (Type of filter) (Property
associated with
it)
A. Low pass filter 1. Tuned circuit
B. High pass filter 2. Compensated
attenuator
C. Band pass filter 3. Differentiator
D. RLC – Circuit 4. Ringing
(a) Pulse amplifier A B C D
(b) Monostable multivibrator (a) 3 2 4 1
(c) Astable multivibrator (b) 2 3 1 4
(d) Bistable multivibrator (c) 2 3 4 1
(d) 2 1 3 4
IES-1995
IES-1994
Ans. (b) : The circuit shown in the given figure is a
monostable multivibrator. Ans. (b) : Low-Pass Filter :- It passes signals with a
frequency lower than a selected cut-off frequency and
Monostable multivibrator has one stable state and one
attenuates signals with frequencies higher than the cut-
quasi stable state. When we applied an external trigger
off frequency.
pulse to the circuit, the multivibrator will jump to quasi
High-Pass Filter :- It acts as a differentiator circuit
stable from stable state. After the few time period it will when time constant is very small as compare to the time
automatically set back to the stable without any external period.
trigger. It is mainly used as timer. RC << T
60. For the circuit given in the figure, consider the Band Pass Filter :- It acts like a tuned circuit that
following statements : passes all frequencies between lower and Higher
frequency Range. It passes all frequencies above its cut-
1. The output VO will consist of a positive and off frequencies.
a negative spike if RC << T. RLC Circuit:- A Circuit with a value of resistor that
2. The output VO will be similar to Vi if RC >> causes it to be just on the edge triggering is called
T critically damped.
3. The output will have a higher rise time if RC Under damped-ringing happens
is made progressively smaller than T. Over damped-ringing is suppressed

Analog Electronics 497 YCT

62. Which of the following pairs is/are correctly Ans. (c) : Astable multivibrators are self triggered.
matched?
Waveform
1. Triangular wave
2. Impulse wave
3. Saw-tooth wave
Circuitry and input signal
1. Integrating circuit and square wave
2. Differentiating circuit and Step signal
3. Differentiating circuit and triangular wave
Select the correct answer using the codes
given below :
(a) 2 and 3 (b) 1 and 2 Advantage of Astable Multivibrator:-
(c) 1 alone (d) 1 and 3 • They are very simple in design
IES-1993 • They are very reliable.
Ans. (b) : • They are very easy to construct with a very nominal
cost
• They do not need any external triggering or input
clock pulse.
• They can run continuously for a very large amount of
time without any problem.
65. Consider the following two statements:
Statement 1: Astable multivibrator can be used
for generating square wave.
Statement 2: Bistable multivibrator can be used
for storing binary information.
63. An astable multivibrator can be used as
(a) Only statement 1 is correct
(a) Squaring circuit
(b) Only statement 2 is correct
(b) Comparator
(c) Both the statements 1 and 2 are correct
(c) Frequency to voltage converter (d) Both the statements 1 and 2 are incorrect
(d) Voltage to frequency converter GPSC Asstt. Prof. 11.04.2017
Nagaland PSC CTSE (Diploma) 2018, Paper-I GATE-2001
Nagaland PSC CTSE (Degree) 2018, Paper-II
Ans. (c) : Astable multivibrator :- It has two unstable
Nagaland PSC CTSE (Degree) 2017, Paper-II states.
Ans. (d) : Voltage to frequency converter:- • It can be used for generating square wave.
• Astable multivibrator are used in the application • It is also called a free running multivibrator.
like pulse position modulation, frequency Bistable Multivibrator:-
modulation.
• It can be switched over from one stable state to the
• Astable multivibrator circuit mainly used as a other by the external trigger pulse.
continuous wave generation circuit. • It is also known as latches and Flip-Flops for use in
• It is used in voltage to frequency converter circuits. sequential type circuits.
• Astable multivibrator circuit can generate also • It can be used for storing binary information.
square wave for this reason, they are used in digital 66. An ideal sawtooth voltage waveform of
transmission, receiver, television broadcast etc. frequency 500Hz and amplitude 3V is
64. Which one of the following multivibrators does generated by charging a capacitor of 2 µF in
not required input clock pulse or trigger? every cycle. The charging requires
(a) Monostable (a) Constant voltage source of 3V for 1 ms
(b) Bistable (b) Constant voltage source of 3V for 2 ms
(c) Astable (c) Constant current source of 3 mA for 1 ms
(d) Schmitt trigger circuit (d) Constant current source of 3 mA for 2 ms
Nagaland PSC (Degree) 2018, Paper-II GATE-2003
Analog Electronics 498 YCT
 1 1 1
Ans. (d) : Given, f = 500 Hz, T = = 2 ms V C, VCC = × 9 = 3V
f 3 3
2 2
VCC = × 9 = 6 V
3 3
VC = 3 V to 6 V
68. In the following astable multivibrator circuit,
which properties of V0 (t) depend on R2?

1 t
C ∫0
Vc(t) = i C .dt

I
Vc(t) = × t = slope × f
C
Vc(t) = 3V at t = 2 ms
−3
I 2 ×10

2 ×10 –6 ∫0
3= 1dt
(a) Only the frequency
I ( 2 ×10−3 − 0 ) = 6 × 10−6 (b) Only the amplitude
I = 3 mA (c) Both the amplitude and the frequency
(d) Neither the amplitude nor the frequency
t = 2 ms
GATE-2009
67. An astable multi-vibrator circuit using IC 555
Ans. (a) :
timer is shown below. Assume that the circuit is
oscillating steadily.

The voltage VC across the capacitor varies

between
(a) 3 V to 5 V (b) 3 V to 6 V If V+ > V– then, V0 = + Vsat
(c) 3.6 V to 6 V (d) 3.6 V to 5 V V+ > V– then, V0 = + Vsat
GATE-2008 Hence, amplitude of astable multivibrator does’nt
depend on R2.
Ans. (b) : Given VCC = 9V For charging and discharging of capacitor ‘C’ time
period.
T = (R1 + R2)C
TON = TOFF = 0.69 (R1 + R2)C
So, T = TON + TOFF = 1.38 (R1 + R2)C
1 1
frequency f = =
T 1.38 ( R1 + R 2 ) C
Hence, In astable multivibrator circuit, only the
frequency depends on R2.
69. If a pulse train with a frequency of 10 kHz is
applied to the trigger input of a bistable
In given astable multivibrator circuit, the capacitor
multivibrator, the frequency of the output
1 2 pulse train would be
voltage VC, varies between VCC and VCC
3 3 (a) 5 kHz (b) 20 kHz
Given that the VCC = 9 Volt (c) 10 kHz (d) None of these
Hence the variation Range of capacitor voltage. Kerala PSC Lecturer (NCA) 04.07.2017

Analog Electronics 499 YCT

Ans. (a) : For Bi-stable multivibrator– 20 − 5 15
F R L(min) = =
Fout = in 15 15
2 RL(min) = 1kΩ.
10 kHz 74. Which component's size is affected by the
Fout =
2 frequency of operation of a switched mode
Fout = 5 kHz power supply?
70. Asymmetrical astable multivibrator has R = (a) Transformer
100Ω and C = 0.1 mF. The periodic time T is (b) Transistor and Transformer
equal to (c) Transformer and Capacitor
(a) 138 mS (b) 69 mS (d) Capacitor
(c) 6.9 mS (d) 13.8 mS
Kerala PSC Lecturer (NCA) 04.07.2017 Nagaland PSC- 2018, Diploma Paper-II
Ans. (d) : For astable multivibrator– Ans. (c) : A switch mode power supply (SMPS) is a
Time period T = 1.38 RC modern power supply converter that works on switching
T = 1.38 × 100 × 0.1 mF technique. In SMPS regulation a large component such
T = 138 × 0.1 msec as transformer, capacitor and inductor are affected by
T = 13.8 ms the frequency of operation.
71. In transistor series voltage regulator the 75. DC output drops from 50 V with no load to 48
transistor behaves like a variable V with full load. Load regulation is
(a) resistor (b) capacitor (a) 2% (b) 4%
(c) inductor (d) resistor and capacitor (c) 1% (d) 8%
TSPSC Manager (Engg.) - 2015
Nagaland PSC- 2018, Diploma Paper-II
Ans. (a) : Transistor series voltage regulator has a
transistor in series to the zener regulator and both in Ans. (b) : VNL = 50 V VFL = 48 V
parallel to load. The transistor works as a variable VNL − VFL
resistor regulating its collector emitter voltage in order %VR = ×100
VNL
to maintain the output voltage constant.
72. In a typical 555 astable multivibrator circuit, if 50 − 48
= ×100
RA = RB = 2.2kΩ and C = 0.1µF then the free- 50
running frequency is : %VR = 4%
(a) 3.123 kHz (b) 2.186 kHz
(c) 4.128 kHz (d) 6.226 kHz 76. By the use of which of the following the PPM
APPSC POLY. LECT. 14.03.2020 can be converted to PWM?
Ans. (b) : RA = RB = 2.2 kΩ (a) Astable multivibrator
C = 0.1 µF (b) Integrator
(c) Monostable multivibrator
1
f= (d) Bistable multivibrator
0.693 ( R A + 2R B ) × C
Nagaland PSC CTSE- 2015, Paper-II
1
f= Ans. (d) : With the help of bistable multivibrator pulse
0.693 ( 2.2 × 10 + 2 × 2.2 × 103 ) × 0.1× 10−6
3
position modulation can be converted into pulse width
modulation.
1000
f= 77. In a free running multivibrator, each stage is
0.693 × 0.66
cut off for 1µs. What is the oscillation
f = 2.186 kHz frequency
73. A zener regulator has an input voltage from 20 (a) 10 MHz (b) 5 MHz
V to 30 V. The load current varies from 10 mA (c) 1 MHz (d) 0.5 MHz
to 15 mA. If the Zener voltage is 5 V, the value Nagaland PSC (Degree) 2018, Paper-II
of series resistor will be Nagaland PSC CTSE- 2015, Paper-II
(a) 1 kΩ (b) 1.5 kΩ Ans. (c) : In electronic circuits, astable multivibrators
(c) 1.66 kΩ (d) 2.5 kΩ are also known as free–running multivibrator as they
Mizoram PSC IOLM -2018, Paper I do not require any additional inputs or external
Ans. (a) : Given , V = 20 volt, Vz = 5 V , assistances to oscillation.
IL(max) = 15 mA 1 1
f= = = 1× 106 Hz
VL V − Vz T 1× µs
I L(max) = =
R L(min) R L(min) = 1 MHz

Analog Electronics 500 YCT

78. (c) A bistable multivibrator
(d) An oscillator
Nagaland PSC CTSE (Degree)-2017, Paper-II
Ans. (c) :

The figure given above shows the circuit of

which one of the following?
(a) Bi-stable multi-vibrator
(b) Schmitt trigger
(c) Mono-stable multi-vibrator
(d) Astable multi-vibrator
IES - 2008
Ans. (c) :
• Any AC input signal is converted into square wave
so the Schmitt trigger is also called as square wave
converter.
• It is also called amplitude comparator
• A comparator circuit with positive feedback is called
Schmitt trigger circuit. It exhibit Hysteresis
The given above circuit, phenomenon.
This is the monostable multi-vibrator monostable -a • It is a basically used Bistable multivibrator
one-shot as once externally triggered it returns back to 82. Pick the odd one out (One of the following type
it's first stable state. numbers is a negative output regulator)
Application of monostable multivibrator (a) LM 7912 (b) LM 7812
The monostable multivibrator is used as delay and
timing circuit. It is also used for temporary memories. It (c) LM 317 (d) LM 7805
is often used to trigger another pulse generator. It is Nagaland PSC CTSE (Diploma)-2018, Paper-I
used for regenerating old and workout pulses. KVS TGT (WE)- 2014
79. What is another name for one-shot Ans. (c) : LM 7912, 7805, 7812, 7905 are voltage
multivibrator? regulator ICs while LM 317 is a positive linear voltage
(a) Monostable regulator and LM 7912 is a negative output regulator.
(b) Astable 83. Pick the odd one out (one of the following is an
(c) Bistable adjustable output regulator)
(d) None of the above options (a) LM 337 (b) LM 7815
NIELIT Scientists- 2017 (c) LM 7918 (d) MC 7812C
Ans. (a) : Mono stable mltivibrator – Nagaland PSC CTSE (Diploma)-2018, Paper-I
• It is also called a single-shot or single swing or a one- Ans. (d) : LM 337, LM 7815 and LM 7918 are
shot multvibrator.
regulator while LM 7812C is a datasheet.
• Other names are; delay multivibrator and univibrator.
• It has one absolutely stable (stand-by) state and one 84. Which of the following circuits converts any
quasi-stable state. arbitrary waveform into square waveform?
80. The output time period of a transistorized (a) Hartley oscillator
monostable multivibrator using base resistance (b) Schmitt trigger
Rb and coupling capacitor Cb for the output (c) Differentiator
transistor is given by (d) RC phase shift oscillator
(a) Rb Cb (b) 0.69 Rb Cb RPSC LECTURER-10.01.2016
(c) 2 Rb Cb (d) 1.38 Rb Cb Ans. (b) :
Nagaland PSC CTSE (Degree)-2017, Paper-II
TSGENCO AE - 2015
Ans. (b) : The width of monostable multivibrator output
pulse depends upon the RC time constant.
Hence it depends on the values of Rb Cb. The duration
of pulse is given by
T = 0.693 R b C b
81. Schmitt trigger is basically
(a) An astable multivibrator
(b) A mono stable multivibrator
Analog Electronics 501 YCT