Kibur College

Department of Computer Science

Course Title: Computer Organization and Architecture
Prepared by: Yordanos
PART I Write “True” if the statement is correct and “False” if it is incorrect.
1. Registers are responsible for generating control signals.
2. In a binary adder subtractor the mode input M is responsible to determine whether the
circuit is adder or subtractor.
3. Higher access time in memory indicates lower the speed.
4. Information transfer from one register to another is described by replacement operator.
5. An associative mapping allows any block of the main memory to be mapped into any cache
line.
6. The numbers (1011)2 and (1011)16 are equal.
7. Effective address represents the actual location of an operand.
8. As memory gets further from the processor, the processor uses shorter access time.
9. In a register stack organization, the stack pointer is incremented when an element is pushed onto
the stack.
10. Immediate addressing mode uses a constant value with in the instruction.

11. The value of sign magnitude, one’s complement and two’s complement is identical
for positive numbers.
12. The output variable of a half-adder is called the augends.
13. In combinational circuit the outputs are determined only by the current states of
the inputs.
14. Selection input determines the input that should be connected to the output.
15. A floating-point number is said to be normalized if the first bit of the mantissa is nonzero.
16. Computer architecture is concerned with ways in which the hardware
components operate and the way they are interconnected together to form a
computer system.
17. All flip flops have 2 outputs.
18. Both half and full adders use large Scale Integration.

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 19. In registers, load input 0 means transfer of data from input lines in to the flip flops
can occur.
20. Bias can be calculated using the formula 2n-1.
PART II Choose the correct answer from the given alternatives.
21. Which of the following memories has the highest access time among all the others?
A. Cache C. Random access memory
B. Hard disk D. Registers
22. Which of the following I/O techniques requires the CPU to continuously check the status of
a device?
A. Interrupt driven I/O C. Memory mapped I/O
B. DMA I/O D. Polling
23. Suppose you are given the binary number 0100 along with the selected bit. After selective
set operation, which pair of operand and resulting binary number is valid?
A. 1011 & 0111 C. 0110 & 0111
B. 0111 & 0111 D. 0101 & 0111
24. Based on the above question, after selective complement operation, which pair of operand
and resulting binary number is valid?
A. 0011 & 0111 C. 0011 & 0101
B. 0011 & 0110 D. 0001 & 0111
25. Which of the following values is equivalent to 69?
A. (1000110)2 C. (55)16
B. (105)8 D. (115)8
26. In indirect addressing mode, the address field of an instruction contains:
A. The actual operand C. The instruction opcode
B. The address of the operand D. The operation to be performed
27. Which one of the following represents a set of common lines through which binary
information is transferred one at a time?
A. Communication cables C. Registers
B. Common bus D. Network cables
28. Which of the following memory has the characteristics “high cost per bit and lower access
time”?
A. Register C. Random access memory
B. Cache D. Secondary storage device

29. Which of the following registers stores the address of the memory location to be accessed?
A. Address Register C. Instruction Register
B. Program Counter D. Data Register
30. If you have a 128 word stack, how many bits are required to represent the stack pointer?
A. 128 C. 10
B. 6 D. 7
31. Which one of the following terminologies represents a set of operations executed on data
stored in one or more registers?
A. Arithmetic operation C. Micro operations
B. Catch hit D. Register transfer
32. Which of the following function corresponds to control unit of a CPU?

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 A. Perform arithmetic and logical operations
B. Sequencing of instructions
C. Allocation and De-allocation of memory
D. Manages external devices
33. Which of the following registers calculates the address of the next instruction to be executed
by the Central Processing Unit?
A. Accumulator C. Data register
B. Instruction registers D. Program counter
34. Which of the following is not a characteristic of Reduced Instruction Set Computer
architecture?
A. One instruction per cycle
B. Large instruction set
C. Operations done within the registers
D. It uses hardwired control units
35. The postfix expression abc+de /*- is equivalent to which of the following infix expression?
A. a-(b+c)*(d/e) C. abc+-de*/
B. abc+*(d/e) D. (a+b)-d/e*c
36. ________ is the percentage of time data is found at a given memory level.
A. Hit ratio C. Miss rate
B. Miss penalty D. Hit time
37. Which of the following is not a secondary storage device?
A. DVD-R C. Hard Disk Drive
B. Solid State Drive D. Random Access Memory
38. Which one of the following statement is NOT true about the Cache replacement Policy?
A. LRU (Least Recently Used) algorithm keeps history of accesses for every cache block in
a system in order to make the operation of the cache fast.
B. In FIFO, the block that has been in cache for the longest time would be selected as the
victim to be removed from cache memory.
C. Random replacement policy picks a block at random and replaces it with a new block.
D. Optimal algorithm keeps values in cache that will be needed again soon, and throw out
blocks that won’t be needed again.
39. Which of the following statements is correct?
A. Peripherals and CPU can communicate in the absence of an input/output interface.
B. The manner of operation in CPU and peripherals is similar.
C. Data transfer rate of peripherals is slower than CPU.
D. Different peripherals have similar operating modes.
40. Which arithmetic expression is suitable for stack manipulation?
A. postfix notation
B. Prefix notation
C. Infix notation
D. Polish notation

41. Suppose we have 15 words in a memory, how many address bits are necessary to
select a specific word?
A. 4 C. 3
B. 5 D. 2

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42. A memory word contains 23 words and 4 bits in each word, the internal structure of
that memory will be .
A. 3 C. 4
B. 8 D. 32
43. A combinational circuit that receives input from n data lines and directs them to 2n
output lines is:
A. Multiplex C. Counter
er D. Flip flop
B. Decoder
44. Suppose the value that is currently stored in a flip flop is 0. If both the inputs S and
R are set to 0, then the output of the flip flop will be
A. 1 C. empty
B. 1 and D. 0
0
45. Which one of the following numbers is the correct value for one’s complement
of the number -15 in 6 bit representation?
A. 101111 C. 110000
B. 001111 D. 110001

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 46. Which of the following numbers is different?
A. 73
B. (1001001)2 C. (111)8
D. (59)16
47. Which of the following logic expressions represents the logic diagram shown?

A. X=AB’+A’B C. X=(AB)’+A’B’
B. X=(AB)’*AB D. X=A’B’+AB
48. A flip-flop is a binary cell capable of storing information of
A. One bit B. Two bit C.8-bit D. 16-bit
49. Which one of the following is valid representation in a signed magnitude format and 1’s
complement format.
A. 100110 & 011001 C. 011111 & 100001
B. 100110 & 111001 D. 100010 & 011001
50. Which one of the following gates requires both inputs to be 0 at a time to produce an
output of 1?
A. AND C. NOR D. XOR
B. OR

PART III Fill the blank spaces with appropriate words.

51. _______________ refers to the symbolic notation used to describe the micro operation transfers
among register.
52. _______________is a program that starts a computer and manages the flow of data between the
operating system and other devices.
53. _______________is the time required to position the read write head to a specific location.
54. _______________ are input or output devices that are connected to a computer.
55. _______________is a collection of storage cells together with associated circuits needed to
transfer information in and out of storage.
56. _______________is a register that holds the address of the top item in the stack.

57. The process of transferring new information in to a register is called .

58. A group of bits that can move in and out of a memory as a single unit is
called .
59. A digital device that goes through a predetermined sequence of steps up on the
application of an input pulse is called .
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 60. A number that is approximately mid way in the range of values expressed by the
exponent is called .
61. Any scientific notation of numbers contains the components ,
, .
PART IV Answer the following questions accordingly.

62. When can we say loading is done in parallel in registers?

63. Describe the steps to be followed on how read and write operations are performed in
RAM memory.
64. Represent the number 10010.001x10-2 using 32 bit floating point representation format.
65. Convert the number (F2B.A3)16 to decimal, binary and octal. The conversion to binary
and octal should be direct.
66. What are the disadvantages of SR flip flop?
67. What is pipelining?
68. Compare and contrast between serial and parallel interface?
69. Compare and contrast between static and dynamic RAM?
70. Explain how the push and pop operation can be performed in a stack.
71. Suppose at a given time CPU seeks 40 words and was able to get 13 of them from the catch
memory and the rest were located at Random Access Memory. What will be the hit ratio?
72. In an 8 bit register what does the micro operation R2<---R1(L) specify? (2pts)
73. Suppose a control unit generates a word “10100000001010”.
Given information:
Operations R2=1101
00000 =Transfers A R3=0101
01000 =AND R4=0111
00101 =Subtract R5=1011
01010 =OR R6=1111
Values in registers R7=1110
R1=1110 External input= 1010
Decode the instruction accordingly and answer the following questions.
A. Which registers are selected to provide input?
B. Which operation is selected in this case?
C. Which register is selected to receive output?
D. What is the value to be stored after the operation is performed?
74. A computer using direct mapping scheme, if a system has a 4096 bytes cache with a block size
of 64 bytes and a main memory having 65536 bytes.
A. How many blocks of main memory are there?
B. How many blocks of cache memory are there?
C. If a CPU generates an address “B631”, to which Cache block will the memory address
mapped?