Microprocessor

8085 Operation
MOHD SYAHRIL NOOR SHAH
Todays topic will cover…
◦ 8085 internal architecture
◦ Registers
◦ ALU group
◦ Instruction decoder and machine cycle encoder, Timing and control circuitry
◦ Interrupt control group
◦ Serial I/O control group
◦ 8085 operation
◦ Instruction fetch
◦ Instruction execution
◦ Stack operation
◦ 8085 IC
◦ Bus multiplexing

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8085 Internal Architecture

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8085 Internal Architecture

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8085 Internal Architecture

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8085 Internal Architecture

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8085 Internal Architecture

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 8085 Internal Architecture

Remember, in 8085 system:

i. Data bus: 8-bits
ii. Address bus: 16-bits

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8085 Internal Architecture

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Registers

• Register array: 14 registers

◦ 12 registers are 8-bit capacity
◦ 2 registers are 16-bit capacity
• Classified into 4 types
1. General purpose register
2. Special purpose register
3. Temporary register
4. Pointer register

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Registers-General purpose

1. General purpose register (user accessible)

◦ B,C,D,E,H,L are 8-bits register
◦ Can also be used for 16-bit pairs. BC, DE & HL
◦ Used to store intermediate data & results
◦ HL register pairs can be used as data pointer that holds memory
address.

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Registers-Special purpose

2. Special purpose register

a) Accumulator (A register) : b) Instruction register (IR):
(user accessible) (not-user accessible)
• 8-bit register • Store the instruction fetch
• All ALU perform with reference from memory before being
to A register contents. transfer for instruction
decoding.
• Results of an operation stored
in A register. • Not programable and cannot
be access by user.
• Store data for I/O transfer.

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 Registers-Special purpose
D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

is set if the arithmetic operation caused

Carry
a carry overflow (from addition) or a
(CY)
borrow (from subtraction)
Parity is set if the accumulator has an even
2. Special purpose register (P) number of ‘1’s
c) Flag register (F): is set if the arithmetic operation caused
(user accessible) Auxilary
a carry out from the bit-3 to the bit-4
carry
◦ Indicates the status of position. (The auxiliary carry flag is used
ALU operation using 5 (AC)
in BCD arithmetic)
flip-flops which are set
or reset according to the Zero is set if the accumulator contains all ‘0’s
data condition of the (Z)
results in the Sign reflects the contents of bit-7 of the
accumulator.
(S) accumulator

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Example-Flag register
ADD B instruction (add register B with register A)
if register A contains 88 H, register B contains 99 H
Binary Decimal
register A 10001000 136
register B +10011001 + 153
register A 100100001 289
(result) D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

◦ S =0 Bit D7 = 0 after addition

◦ Z =0 The accumulator contains other than zero after addition
◦ AC = 1 There is a carry out of bit D3 to bit D4 during addition
◦ P=1 The accumulator contains an even number of ‘1’s after addition
◦ CY = 1 There is an overflow as a result of the addition

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Registers-Temporary

3. Temporary register
a) Temporary data register b) W and Z register
(not-user accessible) • 8-bit register
• 8-bit register • Use to hold temporary
• Use to hold temporary data for address during execution of
ALU operation some instruction.

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Registers-Pointer

4. Pointer register
a) Program counter (PC) b) Stack pointer (SP)
• 16-bit address register • 16-bit address register
• Contains the address of the • Holds the address of the data
next instruction to be executed. present at the top of stack.
• Is initialized to 0000H after • A reserve area of the memory
processor reset or power-up. in RAM to store and retrieve
temporary data.

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Buffer and latches
➢ Incrementer/decrementer
▪ 16-bit register
▪ To increase or decrease the content of
program counter (PC) and stack pointer (SP)
➢ Address buffer
▪ 8-bit unidirectional buffer
▪ Drive higher order address bus (A8 to A15)
➢ Data/Address buffer
▪ 8-bit bidirectional buffer
▪ Drive lower address bus (A0 to A7) and data bus (D0 to D7)

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ALU

ALU group
▪ Perform 8-bits arithmetic and logical operation (add, sub, and, or, xor, etc)
▪ The accumulator (Reg A) holds the first operand of an ALU operation.
▪ The second operand is hold in the temporary register.
▪ The result of the ALU operation is returned to the accumulator and the
necessary flip-flop flags are set/clear.

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Interrupt & serial I/O control

➢ Interrupt control
▪ Interrupt = Occurrence of external disturbance.
▪ 5 interrupt – TRAP, RST7.5, RST 6.5, RST 5.5, INTR
➢ Serial I/O control
▪ SID = Serial data input (received)
▪ SOD = Serial data ouput (send)

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8085 Operation

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 Sequential Machine
➢A digital computer = sequential machine.
➢The CPU (microprocessor) executes instructions in a
sequence as specified by the program.
➢In general terms the instructions are executed in the
sequence they are written.
➢However a certain class of instruction can vary the
instruction execution sequence.

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Function of Memory System
The function of the memory system of a digital computer is to
provide:

1. storage facility for the program ( the instructions ) the

microprocessor is required to execute.

2. storage facility for the data that is to be manipulated

by those instructions.

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 The Instruction Cycle
There are two stages to the complete execution of an
instruction :

Stage 1 : Stage 2 :
CPU fetches the CPU executes the
instruction from instruction
memory

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The Instruction Cycle cont..

Stage 1- Fetching cycle

➢The fetch cycle takes the instruction required from memory then stores it in the
instruction register.
➢Moves the program counter by one so that it points to the next instruction.

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The Instruction Cycle cont..

Stage 2- Execute cycle

➢The actual actions which occur during the execute cycle of an instruction.
➢Depends on both the instruction itself and the addressing mode specified to be
used to access the data that may be required.

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 Instruction Fetch
1. Processor places address of
where the instruction is stored
onto address bus 1

2. Processor asserts the read

control line
4
3. The memory device places the
data at the addressed location
onto the data bus
4. The processor reads the 3
instruction byte.

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Instruction Fetch cont..

The program counter always contains the address of the

memory location from where the CPU is to fetch the next
instruction byte.
The program counter is AUTOMATICALLY INCREMENTED every
time the CPU fetches an instruction byte. Instructions are thus
executed in the sequence they are loaded into program memory.
The contents of the program counter (PC) can be overwritten by
execution of certain instructions e.g. jmp, call, ret etc.

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 Instruction Format cont..
➢Instructions are stored in program memory in 8-bit
binary coded form.
➢The 8085 has 74 basic instruction and 246 total
instructions
➢Since an instruction must represent a complete and
unambiguous statement of the operation required of
the processor then 8-bits (the number of bits of a
single memory location) is often insufficient to
specify the complete instruction.
➢Depending on the particular instruction, 8085A
instructions occupy one, two or three successive
memory locations.
➢Once read from memory, the opcode of the
instruction is stored in the instruction register.

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Instruction Format cont..
What is an Opcode?
➢Opcode = Operation Code
➢The first byte of an instruction = Opcode
➢It describes :
◦ The operation to be carried out e.g move data, arithmetic operation, logical
operation etc. Where the source data is located in the computer. The destination
for the result of the operation. How many bytes constitute the complete
instruction.
Single byte Two byte Three byte
instruction instruction instruction address

n
n+1

n+2

Ex: ADD B Ex: ADI 77H Ex: STA 3002H 29

 Example-Fetching Instruction
Main Memory
Addr. Data
PC 2003 2002 41H
2003 32H
2004 02H
Address Bus
2005 30H

IR 41H Data Bus

Previous
instruction
Step 1: Program counter (PC)
points to the address of the next
instruction to be fetch.

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 Example-Fetching Instruction cont..
Main Memory
Addr. Data
PC 2003 2002 41H
2003 32H
2004 02H
Address Bus
2005 30H

IR 41H Data Bus

Step 2: Contents of the PC is

passed across the address bus

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 Example-Fetching Instruction cont..
Main Memory
Addr. Data
PC 2004 2002 41H
2003 32H
2004 02H
Address Bus
2005 30H

IR 41H Data Bus

Step 3: PC is increased. Memory

location of next instruction is
located.

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 Example-Fetching Instruction cont..
Main Memory
Addr. Data
PC 2004 2002 41H
2003 32H
2004 02H
Address Bus
2005 30H

IR 41H Data Bus

Step 4: The data in the memory

at the given location is moved
accross the data bus.

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 Example-Fetching Instruction cont..
Main Memory
Addr. Data
PC 2004 2002 41H
2003 32H
2004 02H
Address Bus
2005 30H

IR 32H Data Bus

Step 5: Moved into instruction

register (IR) so the new
instruction can be decoded.

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Instruction Format

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 Instruction Decoder and Control Logic

➢The contents of the instruction register is

read by the instruction decoder.
➢The instruction decoder configures the
control logic so that the particular sequence
of CPU operations are carried out to
complete execution of the instruction.
➢This will include fetching the remaining
bytes of an instruction, if the instruction is a
multi byte instruction.
➢The second ( and third ) bytes of a multi
byte instruction are accessed by the CPU in
exactly the same way as the opcode is
fetched from memory. The second ( and
third ) bytes of an instruction are stored in
temporary registers in the CPU.

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Example Execute Instruction
➢Consider the instruction: STA 3002H
➢Opcode in assembly language form: STA
➢Opcode in machine language form : 00110010 (32H)
➢Address location: 3002H
➢The opcode specifies :
1. Data is to be moved (store reg A in memory) 32H
2. The source of the data << CPU register A 02H
3. The destination for the data >> external memory
4. The complete instruction is three bytes long 30H

➢Bytes 2 & 3 of the instruction specify the address of the

memory location where the data is to be written.

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 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0002
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 3001

Data
Reg.W 3002
Reg.Z 3003

Step 1: PC points to the next instruction to be fetch.

 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0003
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 3001

Data
Reg.W 3002
Reg.Z 3003

Step 2: Memory location of next instruction is located. PC is

incremented. Fetching the instruction first byte (Opcode)
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0003
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 32H 3001

Data
Reg.W 3002
Reg.Z 3003

Step 3: The memory content in the memory at the given location

is moved to the IR (Opcode) for instruction decoding.
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0004
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 32H 3001

Data
Reg.W 3002
Reg.Z 3003

Step 4: After decoding, determine it’s a three-byte instruction.

Proceed to fetch the second byte. PC incremented.
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0004
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 32H 3001

Data
Reg.W 02H 3002
Reg.Z 3003

Step 5: The second instruction byte is stored in temporary

register W. (This is the lower order address)
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0005
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 32H 3001

Data
Reg.W 02H 3002
Reg.Z 3003

Step 6: Proceed to fetch the third instruction byte. PC

incremented.
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0005
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 32H 3001

Data
Reg.W 02H 3002
Reg.Z 30H 3003

Step 7: The third instruction byte is stored in temporary

register Z. (This is the upper order address)
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0005
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 32H 3001

Data
Reg.W 02H 3002
Reg.Z 30H 3003

Step 8: Register Z and W are used to point to an address in main

memory (3002H)
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0005
0002 32H
0003 02H
0004 30H
Acc. 89H

IR 32H 3001

Data
Reg.W 02H 3002 89H
Reg.Z 30H 3003

Step 9: The accumulator (reg A) content is stored in memory at

the specified address.
 Example Execute Instruction
STA 3002H Main Memory
Addr. Contents
0001

Program
PC 0006
0002 32H
0003 02H
0004 30H
Acc. 89H
0005 Next Opcode
IR 32H

Reg.W 02H 3001

Data
Reg.Z 30H 3002 89H
3003

Step 10: Execution completed. Fetching the next instruction. PC

incremented.
Example Execute Instruction
STA 3002H

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 Example Execute Instruction
STA 3002H
• Place program counter onto address bus ; opcode address
• Assert 𝑅𝐷control signal
• Read opcode and load into instruction register ; PC incremented
• Decode the opcode
• Place program counter onto address bus ; address of byte 2
• Assert 𝑅𝐷 control signal
• Read byte 2 and save in temp register W ; PC incremented
• Place program counter onto address bus ; address of byte 3
• Assert 𝑅𝐷 control signal
• Read byte 3 and save in temp register Z ; PC incremented
• The whole of the instruction has been fetched at this stage. The 8-bit temporary registers W &
Z contain the 16-bit address of the memory location at which the contents of CPU register A is to
be stored.
• The execution phase of the instruction can now take place.
• Place the contents of W & X onto the address bus ; specify memory address
• Place the contents of register A onto data bus ; data to be written
• Assert 𝑊𝑅 control signal ; write data to memory

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 Stack Pointer
➢The stack is a reserved area of memory. It operates as a last-in first-
out (LIFO) bank of registers.

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 Stack Pointer
➢The memory locations, which
constitute the stack, are used to store
binary information temporarily during
program execution.
➢The stack can be located anywhere in
read/write memory, but is usually
defined such that it neither interferes
with the program memory space or the
data memory space.

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 Stack Pointer cont..
➢The start address of the stack is specified at the initialisation stage of the
program by loading the 16-bit CPU register, called the stack pointer, with
the desired address of the start of the stack.
▪ e.g LXI SP <address>
➢Data from CPU register pairs are stored in the stack area of memory when
the processor executes a (PUSH rp) instruction.
➢Data stored in the stack area of memory are returned to processor
register pairs when the processor executes a (POP rp) instruction.
➢The contents of the PC is automatically stored in the stack area of
memory whenever the processor executes a call or restart (RST n)
instruction.
➢Data is automatically transferred from the stack area of memory to the PC
whenever the processor executes a return (RET) instruction.

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 Example-Writing on Stack
Acc. F
B 00H 3AH C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP
3002 89H
3003
LXI SP, 3004H
3004

1: Initialising the stack using the LXI SP, 3004H. The Opcode LXI is
define as “Load Register Pair Immediate”. So the instruction
dictates the SP register is to be loaded with value 3004H.

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 Example-Writing on Stack
Acc. F
B 00H 3AH C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3004H
3002 89H
3003
LXI SP, 3004H
SP 3004

2: Stack pointer (SP) is initialised and pointing to the specified

address.

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 Example-Writing on Stack
Acc. F
B 00H 3AH C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3004H
3002 89H
3003
PUSH HL
SP 3004

3: Data from the register pair HL are stored in the stack area of
memory when the processor execute PUSH rp instruction. SP
decrement by ‘1’ before moving register H content to stack.

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 Example-Writing on Stack
Acc. F
B 00H 3AH C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3003H
3002 89H
SP 3003 56H
PUSH HL
3004

3: Data from the register pair HL are stored in the stack area of
memory when the processor execute PUSH rp instruction. SP
decrement by ‘1’ before moving register H content to stack.

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 Example-Writing on Stack
Acc. F
B 00H 3AH C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3002H
SP 3002 92H
3003 56H
PUSH HL
3004

4: SP decrement by ‘1’ before moving register L content to stack.

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Reading from Stack
Lets say you wanted to read the data from stack
memory and store it in register pair BC……

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 Example-Reading from Stack
Acc. F
B 00H 3AH C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3002H
SP 3002 92H
3003 56H
POP BC
3004

1: Data stored in the stack area of memory are returned to the

processor register pairs when the processor execute a POP rp
instruction.

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 Example-Reading from Stack
Acc. F
B 00H 92H C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3002H
SP 3002 92H
3003 56H
POP BC
3004

2: Moving stack memory location content to register C. After

moving, increment SP.

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 Example-Reading from Stack
Acc. F
B 00H 92H C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3003H
3002 92H
SP 3003 56H
POP BC
3004

2: Moving stack memory location content to register C. After

moving, increment SP.

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 Example-Reading from Stack
Acc. F
B 56H 92H C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3003H
3002 92H
SP 3003 56H
POP BC
3004

3: Moving stack memory location content to register B. After

moving, increment SP.

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 Example-Reading from Stack
Acc. F
B 56H 92H C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3004H
3002 92H
3003 56H
POP BC
SP 3004

3: Moving stack memory location content to register B. After

moving, increment SP.

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 Example-Reading from Stack
Acc. F
B 56H 92H C Main Memory
Addr. Contents
D E
H 56H 92H L
3001
SP 3004H
3002 92H
3003 56H
POP BC
SP 3004

4: Completed POP instruction.

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 Timing and control

➢ Crystal oscillator
The control logic subsystem of a microprocessor is a configurable sequential state machine.
It is configured by the instruction decoding circuitry to enable execution of a particular
instruction.
It has associated with it a number of inputs and outputs, both from other subsystems of the
CPU and from external devices.
It operates with respect to a stable clock reference signal provided by a crystal source.
Typical clock frequencies for an 8085A microprocessor are in the order of 5-MHz.
The internal clock for the control logic is half the frequency of the external crystal source (i.e
internally the crystal source clock is divided by 2)

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 Control logic

➢ Control logic functions

𝑹𝑫 - A logic ‘0’ specifies the processor will read the data on
the data bus.
𝑾𝑹 - A logic ‘0’specifies that the processor has placed data
(write) onto the data bus for an external device to read.
Reset(out) - A logic ‘1’ on the reset in input to the processor
causes the program counter to be reset to 0000H. To indicate
the processor has been reset a logic `1’, synchronized to the
processor clock, is placed on this output.

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 Control logic

➢ Control logic functions cont..

𝑺𝟎 𝑺𝟏 𝑰𝑶/𝑴ഥ - A 3-bit status code that specifies the operation the processor
is performing. (e.g. 110 specifies the processor is fetching an opcode from
program Memory).

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 Control logic cont..

➢ Control logic functions cont…

CLK out - Is a buffered version of the internal master clock of the 8085A. It is half
the crystal frequency.
HOLD (1) HLDA (0) - An external device can request use of the system busses by
driving the HOLD input to logic ‘1’. The 8085A acknowledges the request by
asserting the HLDA output to logic ‘1’. It only does after it has relinquished control
of the bus structure.
ALE (0) -When this signal is logic ‘1’ the processor specifies that it has valid address
information on the CPU pins D0-7
RDY(1) -When this signal is logic ‘0’ the processor suspends execution of an
instruction. It permits slow peripheral devices more time to access or load data.

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Control logic cont..

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8085 Pin diagram

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8085 Bus interface
➢ The 8085A microprocessor uses only 16 connections to interface the
8-bit data bus and 16-bit address bus.

➢ Address bus lines 𝑨𝟎−𝟕 are time multiplexed with data bus lines 𝑫𝟎−𝟕

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 8085 Bus interface cont..

➢ Multiplexing the lower address bus

and data bus using Latch.

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8085 Bus interface cont..

➢ Peripheral devices ( memory and IO ) require stable address

data throughout a read or write operation.
➢ The processor only provides A0 - A7 during the period
ALE=logic ‘1’ state after which the multiplexed lines AD0 - AD7
assume the role of the data bus. ( D0 - D7 )
➢ To provide external devices with stable address data
throughout a read or write operation it is necessary to latch
the low byte of the address using the ALE control signal.
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End Lecture
WEEK 2
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