ANSWER KEY

QP Code :
THAMIRABHARANI ENGINEERING COLLEGE
(An Autonomous Institution)
B. E. DEGREE END SEMESTER THEORY EXAMINATIONS, NOV. / DEC. 2025
Fourth Semester
Electrical And Electronics Engineering
EE3404 –MICROPROCESSOR AND MICROCONTROLLER
(Common To if applicable)
(Name of the Tables/Charts) Can be Permitted (if applicable)
Regulations - 2021
Duration : 3 Hrs Maximum : 100 Marks

PART – A (ANSWER ALL QUESTIONS) (Marks 10*2=20)

[Link]. Questions BLT CO Marks

The IO/M̅ (Input-Output/Memory) signal in 8085 differentiates whether the current

operation is related to memory (IO/M̅ = 0) or I/O device (IO/M̅ = 1) during read/write
1. 1 2
machine cycles.

 Accumulator (A)

 Flag Register

 Stack Pointer (SP)

2.  Program Counter (PC) 1 2

 Instruction Register (IR)

 Temporary Register

 Interrupt Control Register

The stack stores return addresses and temporary data during subroutine calls,
3. interrupts, PUSH/POP instructions. It helps preserve program execution sequence. 2 2

A look-up table (LUT) is a memory table that stores pre-computed values used to
4. 2 2
speed up calculations such as ASCII conversion, sine wave generation, code
translation, etc.

The 8255 PPI (Programmable Peripheral Interface) is used to interface keyboard,

displays, DAC/ADC, relay drivers etc. It provides three 8-bit programmable I/O ports
5. 3 2
(Port A, Port B, Port C).

6. 3 2
  Address lines

 Chip Select (CS)

 Start of Conversion (SOC)

 End of Conversion (EOC)

 Output data lines (D0–D7)

 Read signal (RD)

IDE (Integrated Development Environment) is software that provides programming

tools such as editor, compiler, assembler, debugger and simulator in a single
7. environment. 4 2

 External Interrupt 0 (INT0)

 Timer 0 Interrupt (T0)

8.  External Interrupt 1 (INT1) 4 2

 Timer 1 Interrupt (T1)

 Serial Interrupt (RI/TI

 Timer0 (8/16 bit)

 Timer1 (16-bit)
9. 5 2
 Timer2 (8-bit with prescaler/postscaler)

 Timer3 (16-bit)

10.  Port A 5 2

 Port B

 Port C

 Port D

 Port E
 PART – B (ANSWER ALL QUESTIONS) (Marks 5*13 = 65)
[Link]. Questions BLT CO Marks
Block diagram explanation points:

 ALU
 Register array (A, B, C, D, E, H, L)

 Instruction register & decoder

 Program counter, Stack pointer

 Address/Data bus

 Timing & control unit

 Interrupt control

 Serial I/O control

Write functions of each block.

11. a i 1

Or
b i Explain control signals: 1

 ALE
 RD̅

 WR̅

 IO/M̅

 Address valid time

Draw timing waveforms and explain T-states.
12. a i List & explain: 2

1. Immediate → MVI A,55H

2. Register → MOV A,B

3. Direct → LDA 2050H

4. Register Indirect → LDAX B

5. Implicit → CMA

6. Immediate register indirect

8085 supports five standard addressing modes:

✅ 1. Immediate Addressing Mode

 In this mode, data (operand) is given immediately in the
instruction itself.
 The constant is stored in the next byte of the instruction.

Example
MVI A, 55H

Meaning: Move immediate data 55H into accumulator A.

Operation

 PC fetches opcode (MVI A)

 Next byte (55H) is placed into register A

✔ Fastest mode since data is available immediately.

✅ 2. Register Addressing Mode

 Operand is available inside one of the general purpose registers.
 Data moves between registers.

Example
MOV A, B
Meaning: Copy the contents of register B into register A.

Operation

No memory access required (uses internal bus) → Faster execution.

✅ 3. Direct Addressing Mode

 Operand (data) is stored at a specific 16-bit memory address
given directly in the instruction.

Example
LDA 2050H

Meaning: Load accumulator from memory location 2050H.

Operation

 The processor takes the address 2050H from instruction

 It places this address on the address bus
 Reads data from memory

Used when:

 Data stored in RAM

 Lookup tables
 Constant tables

✅ 4. Register Indirect Addressing Mode

 The instruction does not hold the actual memory address.
 A register pair (H-L or B-C) contains the address indirectly.

Example
LDAX B

Meaning: Load accumulator with the contents of the memory location

whose address is held by BC pair.

Operation

 BC pair holds memory address

 Processor reads memory data and loads into accumulator

Used for:

 Array access
 String operations
 Pointer operations
Another example:

MOV A, M

Here, HL pair points to the memory location addressed through symbolic

name M.

✅ 5. Implicit (Implied) Addressing Mode

 Operand is not specified in the instruction.
 It is implicitly understood by the microprocessor.

Example
CMA

Meaning: Complement accumulator.

Internal Operation

ACC = NOT(ACC)

 No operand required
 Accumulator is implied

Other examples:

STC → set carry flag

CMC → complement carry flag
DAA → decimal adjust accumulator

✅ (Optional) 6. Immediate Register-Indirect

Addressing Mode (Rare/Hybrid)
Sometimes mentioned separately in universities.

Here:

 Data is immediately given,

 But destination location is pointed by register pair

Example
MVI M, 25H

Meaning: Move 25H to memory location pointed by HL register pair.

Internal operation:

 HL has address = e.g., 3000H

 Store 25H into memory[HL]
 🎯 Summary Table

Addressing Mode Data Location Example Notes

Immediate Inside instruction MVI A,55H Fast
Register Inside register MOV A,B No memory access
Direct In memory location LDA 2050H 16-bit address
Register Indirect Memory via pointer LDAX B, MOV A,M Used for arrays
Implicit Predefined operand CMA, STC Operand understood
Or
b i 1. Read the input byte (call it val). 2

2. Preserve val (we use register B as backup).

3. Extract the high nibble (bits 7–4), move it to low nibble position
(bits 3–0). Convert that 4-bit value (0–15) into ASCII:

o If value ≤ 9 → ASCII = value + 30H (characters '0'..'9')

o If value ≥ 10 → ASCII = value + 37H (characters

'A'..'F')
Note: 37H = 30H + 07H so when value=10 (0AH): 0AH
+ 37H = 41H = 'A'.

4. Extract the low nibble (bits 3–0) directly from val and convert
similarly.

5. Store the two ASCII bytes in memory or output port.

Assumptions:
 Input byte is stored at memory location 3000H.
 Resulting ASCII bytes will be stored at 3001H (high digit) and
3002H (low digit).

 Uses registers: A, B, D, E, and HL (for storing results).

 NIB2ASCII is a callable subroutine that converts a nibble (0–15)

in A to its ASCII code (in A) and returns.

Program
ORG 0000H

START: LXI H, 3000H ; HL -> 3000H (point to input

location)
MOV A, M ; A <- [3000H] ; input byte
MOV B, A ; B <- backup of input

; -------- Convert HIGH nibble ----------

MOV A, B ; A = original input
ANI F0H ; keep only high nibble (bits
7-4), others = 0
RRC ; rotate right 1 (repeat 4
times to move high nibble to low)
RRC
RRC
 RRC ; now bits 3-0 contain original
bits 7-4
ANI 0FH ; mask to be safe: A = 0x0(high
nibble)
CALL NIB2ASCII ; convert nibble in A to ASCII
char
MOV D, A ; save high-digit ASCII in D

; -------- Convert LOW nibble -----------

MOV A, B ; A = original input again
ANI 0FH ; isolate low nibble (bits 3-0)
CALL NIB2ASCII ; convert nibble in A to ASCII
char
MOV E, A ; save low-digit ASCII in E

; -------- Store results (two ASCII chars) -

LXI H, 3001H ; HL -> 3001H (store high
digit)
MOV M, D ; [3001H] <- high ASCII
INX H
MOV M, E ; [3002H] <- low ASCII

HLT

; -------- Subroutine: Convert nibble -> ASCII in A

----------
; Input : A contains 0x00..0x0F
; Output: A contains ASCII for hex digit
('0'..'9','A'..'F')
NIB2ASCII: CPI 0AH ; Compare A with 10 (0AH)
JC NIB_DIGIT ; If A < 10, jump to produce
'0'..'9'
ADI 37H ; If A >= 10, A = A + 37H -->
maps 0AH..0FH to 'A'..'F'
RET

NIB_DIGIT: ADI 30H ; A = A + 30H --> maps 0..9 to

'0'..'9'
RET

13. a i 3
8255 – Programmable Peripheral
Interface
The Intel 8255 PPI is a General-Purpose Programmable I/O device.
It provides 24 I/O lines arranged as three 8-bit ports:

 Port A (PA0–PA7)
 Port B (PB0–PB7)

 Port C (PC0–PC7) (split into two 4-bit ports PC Upper / PC

Lower)

It is used for interfacing:

 Keyboards
 Displays

 ADC/DAC

 Stepper motors

 Printers
  Relays

Block Diagram of 8255 (Neatly

Drawn)
Use this diagram in your answer sheet:

┌───────────────────────────┐
│ 8255 PPI │
│ │
│ ┌───────────────┐ │
PA7–PA0 ────►│ PORT A (8) │◄───── │
│ └───────────────┘ │
│ │
│ ┌───────────────┐ │
PB7–PB0 ────►│ PORT B (8) │◄───── │
│ └───────────────┘ │
│ │
│ ┌───────────────┐ │
PC7–PC0 ────►│ PORT C (8) │◄───── │
│ └───────────────┘ │
│ │
│ ┌────────────────────┐ │
DATA BUS ◄──►│ DATA BUS BUFFER │──│── CPU
│ └────────────────────┘ │
│ │
│ ┌────────────────────┐ │
A1,A0 ────►│ READ/WRITE LOGIC │ │
RD, WR, │ Chip Select, Reset │ │
CS, RESET │ │ │
│ └────────────────────┘ │
│ │
│ ┌────────────────────┐ │
│ │ CONTROL LOGIC │◄─┤─ CONTROL
WORD
│ └────────────────────┘ │
│ │
└───────────────────────────┘

Internal Architecture Explanation

✅ 1. Data Bus Buffer

 Bi-directional tri-state buffer

 Interfaces 8255 to CPU data bus (D0–D7)

 Transfers data:

o Input data from ports → CPU

o Output data from CPU → ports

✅ 2. Read/Write Control Logic

Controls internal operations using signals:

Signal Function
RD̅ Read data from selected port
WR̅ Write data into selected port
CS̅ Chip select (enable device)
A1–A0 Select port/register

✅ 3. Group Selection

8255 has two groups:

 Group A controls:
o Port A (PA0–PA7)

o Upper 4 bits of Port C (PC4–PC7)

 Group B controls:

o Port B (PB0–PB7)

o Lower 4 bits of Port C (PC0–PC3)

✅ 4. Control Register

Stores control word from CPU to configure:

 Mode of operation
 Direction (input/output)

 Handshaking pins

Port Addressing (Using A1, A0)

A1 A0 Selected Register
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Register

🧾 Control Word Format (Mode

Definition)
D7 D6 D5 D4 D3 D2 D1 D0
│ │ │ │ │ │ │ └── Port C lower (In/Out)
│ │ │ │ │ │ └──── Port B (In/Out)
│ │ │ │ │ └────── Mode for Group B
│ │ │ │ └────────── Port C upper (In/Out)
│ │ │ └───────────── Port A (In/Out)
 │ │ └─────────────── Mode for Group A
│ └────────────────── Group A mode select
└───────────────────── 1 = I/O mode, 0 = Bit Set/Reset

🚀 Operating Modes of 8255

8255 has three main I/O modes:

MODE 0 → Simple Input/Output

MODE 1 → Handshaking I/O
MODE 2 → Bi-directional Handshaking

✅ MODE 0 (Simple / Basic I/O Mode)

 No handshake
 Independent ports

 Simple input/output only

 Port C can act as individual port bits

Used for: LED, switches, display

CPU
│
Port A → Output
Port B → Input
Port C → Individual bits

Characteristics
✔ No control signals
✔ Fastest mode
✔ Can configure each port separately

✅ MODE 1 (Strobed / Handshake I/O)

Provides handshaking signals using Port C lines.

Used for:

 Keyboard input
 Printers

 ADC/DAC

Handshake pins (from Port C)

 STB (Strobe Input)

 IBF (Input Buffer Full)

 OBF (Output Buffer Full)

 ACK (Acknowledge)
✅ MODE 2 (Bi-directional Data Transfer)
 Only for Port A
 True bidirectional communication

 Uses Port C upper lines for handshake

Used for:

 Data buses
 Multiprocessor communication

 DMA-type transfers

Bit Set / Reset (BSR) Mode

 Only affects Port C single bits
 Independent of other ports

 Used to control:

o Individual relays

o LEDs

o Control lines

Control Word Format (BSR):

D7 = 0 → BSR mode active

D3–D1 = PC bit selected (0 to 7)
D0 = 1 → Set bit
D0 = 0 → Reset bit

Group Summary
Group Ports Mode Supported
Group A Port A + PC upper Mode 0,1,2
Group B Port B + PC lower Mode 0,1

Applications of 8255
 Interface keyboards
 Control stepper motors

 Drive LEDs

 ADC & DAC

 Sensor interfacing
  Industrial automation

Final Summary
The 8255 PPI:

 Provides 24 programmable I/O lines

 Configurable via control word

 Supports simple, handshake, and bidirectional modes

 Essential for peripheral interfacing in 8085/8086 systems

Or
b i 3
8279 – Keyboard/Display Controller
(Detailed Explanation)
The Intel 8279 is a programmable controller used to interface:

 Matrix keyboards (up to 64 keys)

 Seven-segment / multi-digit displays

 Scanned or encoded displays

It offloads the CPU by:

 Handling key debouncing

 Generating keyboard interrupts

 Refreshing displays automatically

Internal Block Diagram of 8279

Draw the following diagram on your answer sheet:

┌───────────────────────────┐
│ 8279 IC │
│ │
CLK ───────►│ Clock & Timing │
│ │
SL0–SL3 ───────► │ Scan Generator │
│ │
RL0–RL7 ◄─────── │ Return Lines │
│ │
│ ┌───────────────────┐ │
│ │ Keyboard Debounce │ │
│ │ & FIFO Buffer │ │
│ └───────────────────┘ │
 │ │ │
│ IRQ◄──────────────│ CPU
│ │
DISP0–DISP3 ◄────── │ Display Addressing │
│ │
OUTA–OUTD ────────►│ Display Driver │
│ │
│ ┌───────────────────┐ │
│ │ Control Logic │ │
DB0–DB7 ◄────────► │ │ Data/Status │ │
│ └───────────────────┘ │
│ │
RD, WR, CS, A0 ──────►│ CPU Interface │
└───────────────────────────┘

Pin Diagram Overview

Pin Function
SL0–SL3 Scan lines (row/column scan)
RL0–RL7 Return lines (sense keys)
OUTA–OUTD Display segment drivers
A0 Command/Data select
RD̅ Read signal from CPU
WR̅ Write signal from CPU
CS̅ Chip select
DB0–DB7 Bidirectional data bus
IRQ Interrupt request
CLK Frequency input

Functional Blocks Explanation

🔷 1. Keyboard Interface

 Operates in scanned OR encoded mode.

 Detects key closures, debounces automatically.

 Stores key codes in an 8-byte FIFO buffer.

🔷 2. Debounce & FIFO

 Eliminates key bounce.

 Allows multiple key presses.

 Generates interrupt to CPU when buffer is full.

🔷 3. Display Interface

 Drives 6 or 8 displays.
 Displays automatically refreshed — no CPU burden.

🔷 4. Scan Generator

 Generates scan pulses to:

o Keyboard rows

o Display digits
Frequency is programmable.

Keyboard Operating Modes

✅ 1. Scanned Keyboard Mode

Supports:

 2-key lockout OR N-key rollover

 Up to 64 keys arranged in 8×8 matrix

Scan lines SL0–SL3 select row/column.

Return lines RL sense key press.

Modes:

 2-Key Lockout: Accept only 1 key at a time

 N-Key Rollover: Accept multiple keys (gaming/industrial)

✅ 2. Sensor Matrix Mode

Used for:

 Switches
 Contact closures

 Mechanical sensors

Continuously monitors inputs.

Display Operating Modes

The 8279 supports:

✅ 1. Left Entry Mode

Characters are entered from left side of display.

Example: abc → shown as abc____

✅ 2. Right Entry Mode

Characters scroll from right side (calculator-style).

Example: typing 123 shows as ....123

Display Formats

✅ Decoded Scan
  7-segment decoding internal to 8279
 Saves CPU work

✅ Encoded Scan

 CPU provides encoded 4-bit BCD

 External decoder (7447/7448)

Scan Modes (Overview)

Mode Function
Encoded Use 4 scan lines + external decoder
Decoded Directly drive up to 8 digits

8279 Command/Control Word Format

Command register selected when A0=1

Sample format:
D7 D6 D5 D4 D3 D2 D1 D0
│ │ │ │ │ │ │ └── Operation bit
│ │ │ │ │ │ └──── Keyboard mode
│ │ │ │ │ └────── Display mode
│ │ │ │ └────────── Entry mode
│ │ │ └───────────── Scan mode
│ │ └─────────────── Clock divisor
│ └────────────────── Reset FIFO
└──────────────────── Global enable

Status Word

Read when A0 = 0 in read mode.

Includes:

 FIFO full flag

 FIFO empty flag

 Key available flag

 Time-out

FIFO Buffer Operation

FIFO = First In First Out

 8 bytes deep
 Keypress stored in sequence

 CPU reads later

 Interrupt generated when:

o Key available

o FIFO full
Key Debounce Logic
Mechanical keys produce noise like:

On press → bounce → settle

8279 filters it and stores only one stable event.

Interrupt (IRQ) Operation

8279 issues IRQ when:

 New keypressed
 FIFO overflow

 Sensor change

CPU clears IRQ by reading.

Interfacing Concept (Keyboard +

Display)
You can draw this:

┌───────┐
│ 8279 │
SL0–SL3 ───►│ │◄── RL0–RL7
│ │
OUTA–OUTD──►│ │──► Display segments
└───────┘
│
CPU Bus

Applications
8279 widely used in:

 Digital calculators
 Control panels

 Data entry terminals

 Microwave oven keyboards

 Industrial meters

 ATMs
  CNC machines

Conclusion
The Intel 8279 reduces CPU load by:
✔ handling key debouncing
✔ performing display refresh
✔ generating scanning patterns
✔ buffering keys

making it ideal for real-time embedded systems.

Interrupt Structure of 8051

Microcontroller
An interrupt is a mechanism by which the microcontroller temporarily
suspends the main program to execute an ISR (Interrupt Service Routine)
when an important event occurs.

The 8051 supports 5 vectored interrupts, each with programmable

priority.

Types of Interrupts in 8051

Interrupt Source Vector Address Type
External Interrupt 0 (INT0) 0003H Edge/Level triggered
Timer 0 Interrupt 000BH Internal
External Interrupt 1 (INT1) 0013H Edge/Level triggered
Timer 1 Interrupt 001BH Internal
14. a i Serial Port Interrupt 0023H Internal (RI/TI flags) 4

Interrupt Vector Table

At reset, the processor starts at 0000H.

For interrupts, execution jumps to:

0003H : External 0 ISR

000BH : Timer0 ISR
0013H : External 1 ISR
001BH : Timer1 ISR
0023H : Serial ISR

These addresses contain jump instructions to the actual ISR code.

8051 Interrupt Enable Register (IE)

Location: A8H

┌─────────────────────────────────────────────┐
| EA | — | ET2 | ES | ET1 | EX1 | ET0 | EX0 |
└─────────────────────────────────────────────┘
MSB LSB
Bit Meaning
EA Global Enable (1 = interrupts allowed)
ET0 Enable Timer0 interrupt
EX0 Enable External0 interrupt
ET1 Enable Timer1 interrupt
EX1 Enable External1 interrupt
ES Enable Serial interrupt

Example (Enable all):

MOV IE, #10010111B

Interrupt Priority Register (IP)

Location: B8H

┌─────────────────────────────────────────────┐
| — | — | PT2 | PS | PT1 | PX1 | PT0 | PX0 |
└─────────────────────────────────────────────┘

Bit = 1 → high priority

Bit = 0 → low priority

Two-Level Priority

8051 supports:

 Low priority interrupts

 High priority interrupts

High priority interrupts can interrupt low priority ISRs.

Interrupt Response Latency

8051 takes 3 machine cycles to respond:

1. Finish instruction
2. Push PC on stack

3. Jump to ISR

Interrupt Service Routine (ISR)

Structure:

ORG 0003H ; external 0 vector

CALL MYISR
RETI ; return from interrupt

RETI (not RET) needed to:

 restore priority flags

 resume main program
External Interrupt Triggering

External interrupts INT0 and INT1 can be triggered:

✅ Level triggered

Active LOW (default)

✅ Edge triggered

Selected through TCON register

TCON Register (Timer/Interrupt Control)

Address: 88H

┌─────────────────────────────────────────────┐
| TF1 | TR1 | TF0 | TR0 | IE1 | IT1 | IE0 | IT0 |
└─────────────────────────────────────────────┘

Bits:

Bit Meaning
IT1 External 1 edge/level mode
IE1 External 1 interrupt flag
IT0 External 0 edge/level mode
IE0 External 0 interrupt flag

 ITx = 1 → Edge triggered

 ITx = 0 → Level triggered

Interrupt Control Flow

(Interrupt occurs)
↓
Check EA (global enable)
↓
Check enabling bit in IE register
↓
Check priority (IP register)
↓
Finish current instruction
↓
Push PC on stack
↓
Jump to vector address
↓
Execute ISR until RETI
↓
Pop PC from stack
↓
Resume main program

Interrupt Nesting

 High priority interrupts can interrupt low priority ISR

 Low priority cannot interrupt high priority ISR

 Equal priority → handled by vector order

Serial Interrupt

Triggered by:

 TI (Transmit interrupt flag)

 RI (Receive interrupt flag)

ISR must check which flag caused interrupt.

Block Diagram of Interrupt Structure (Draw in answer sheet)

┌──────────────────────────────┐
External0 → │ Interrupt Control Logic │
Timer0 → │ │
External1 → │ Priority Resolver Unit │────┐
Timer1 → │ │ │
Serial → │ Vector Address Generator │ │
└───────────┬──────────────────┘ │
│ │
▼ ▼
PC Stack Interrupt
↓ |
└──────► CPU Executes ISR

Key Features Summary

✔ 5 vectored interrupts
✔ Simultaneous enabling/disabling
✔ Priority levels
✔ Edge/Level triggering
✔ Automatic PC save/restore
✔ Supports nesting

Typical ISR Example

ORG 0003H ; INT0 vector
INT0_ISR:
CLR P1.0
RETI

Advantages of Interrupts

 Reduces CPU polling time

 Real-time event handling

 Higher system efficiency

Conclusion

The 8051 interrupt structure:

 Provides fast response to external/internal events,

 Offers priority control,

 Supports vectored jump addresses,

 Efficiently resumes main program using RETI.

This makes 8051 suitable for embedded real-time control applications.

 Or
b i 4
Interfacing a Unipolar Stepper
Motor with 8051 Microcontroller
A stepper motor rotates in fixed angular steps (commonly 1.8° or 7.5°
per step).
It is widely used in CNC machines, servo drives, robotics, printers, disk
drives, etc.

The motor consists of multiple windings which are energized in sequence

to rotate the shaft.

For a unipolar stepper motor, the coil center tap is connected to +V,
and the ends are driven by the microcontroller through a driver.

Why Driver Circuit is Required?

Because:

 8051 I/O pin can source only 15–20 mA at 5V

 Stepper motor coils need 300–500 mA at 12V

So we use:

✅ ULN2003 (Darlington transistor array)

OR
✅ Four power transistors with flyback diodes

This protects the microcontroller and gives required current.

Functional Block Diagram

Draw this in your answer sheet:

┌─────────┐
│ 8051 │
│ │
P2.0 ─────│ │
P2.1 ─────│ I/O │
P2.2 ─────│ Port │───► Driver ───► Stepper
P2.3 ─────│ │ (ULN2003)
│ │ ↑
└─────────┘ │
│ +12V

Circuit Diagram

Neatly draw this diagram:

+12V
│
 .│.
.│. Center Tap
│
┌────────┴────────┐
│ │
Coil A Coil B
| |
Q1 Q2
| |
P2.0 ────────► ULN2003 |
(driver)
| |
Coil C Coil D
│ │
Q3 Q4
│ │
P2.2 P2.3

All transistor grounds connect to GND

Back EMF diodes provided internally in ULN2003

Or simply label:

 P2.0 → coil A
 P2.1 → coil B

 P2.2 → coil C

 P2.3 → coil D

4-Step Sequential (Waveform)

Also called full step sequence

Step A B C D
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1

Waveform to draw:

A: ─█───┬──────┬───────
B: ────█───┬────┬──────
C: ───────█───┬──┬─────
D: ─────────█──┬──┬────

After step 4 → back to step 1 = continuous rotation.

Bi-phase (Two coil ON) Mode

More torque. Table:

Step A B C D
1 1 1 0 0
2 0 1 1 0
3 0 0 1 1
4 1 0 0 1

Operation Principle
  Energizing coil A attracts rotor tooth → moves one step
 Energizing coil B moves again, etc.

 Sequence determines direction

o Forward: A→B→C→D

o Reverse: D→C→B→A

Stepper Motor Advantage

 Precise positioning
 No feedback required

 Excellent repeatability

Assembly Language Program (4-Step Sequence)

; Stepper motor interface using Port 2
ORG 0000H
MAIN: MOV P2, #0A0H ; Initialize port as output

STEP1: MOV P2, #01H ; 0001

ACALL DELAY
STEP2: MOV P2, #02H ; 0010
ACALL DELAY
STEP3: MOV P2, #04H ; 0100
ACALL DELAY
STEP4: MOV P2, #08H ; 1000
ACALL DELAY
SJMP STEP1 ; continuous rotation

;-----------------------
DELAY: MOV R2, #20H
D1: MOV R1, #FFH
D2: DJNZ R1, D2
DJNZ R2, D1
RET
END

👉 Rotation Speed = controlled by delay routine.

Reverse Rotation Program

Just reverse the sequence:

STEP1: MOV P2, #08H

ACALL DELAY
STEP2: MOV P2, #04H
ACALL DELAY
STEP3: MOV P2, #02H
ACALL DELAY
STEP4: MOV P2, #01H
ACALL DELAY
SJMP STEP1

Step Angle Calculation (Optional Theory)

Step Angle = 360° / (number of rotor teeth × number of
phases)

Typical values:
  1.8°
 7.5°

 15°

Why ULN2003 is preferred?

 Each channel supports 500 mA

 Darlington amplification

 Inbuilt flyback diodes

 Direct TTL/CMOS control

Applications of Stepper Interfacing

 Robotics
 CNC machines

 Disk Drives

 Antenna positioning

 XY Plotters

 Textile machines

ii 4

15. a i 5
PIC18 Series Microcontroller –
Functional Block Diagram
The PIC18 family (e.g., PIC18F452/4550) is an advanced 8-bit RISC
microcontroller designed by Microchip Technology.
It supports high-performance, low-power, and rich on-chip peripherals.

Draw this diagram in your answer sheet:

┌───────────────────────┐
│ CPU (ALU) │
│ Accumulator | WREG │
└─────────┬─────────────┘
│
┌─────────▼───────────┐
│ Instruction │
│ Decoder │
└─────────┬───────────┘
│
┌───────────────┐ │
┌─────────────────┐
│ Program Memory│◄───────┘ │ Data Memory
│
│ (Flash ROM) │ │ (RAM + SFR)
│
└──────┬────────┘
└─────────────────┘
 │
┌─────────▼───────────┐
│ Stack (31 Levels) │
│ Return Address │
└─────────┬────────────┘
│
┌──────────────▼───────────────┐
│ Timers (T0,T1,T2) │
└──────────────┬───────────────┘
│
┌──────────────▼───────────────┐
│ Capture/Compare/PWM (CCP) │
└──────────────┬───────────────┘
│
┌──────────────▼───────────────┐
│ A/D Converter (ADC) │
└──────────────┬───────────────┘
│
┌──────────────▼──────────────┐
│ USART (Serial UART) │
└──────────────┬──────────────┘
│
┌──────────────▼──────────────┐
│ I2C / SPI (MSSP Module) │
└──────────────┬──────────────┘
│
┌──────────────▼──────────────┐
│ Interrupt Controller │
└──────────────┬──────────────┘
│
┌──────▼───────┐
│ I/O Ports │
│ (PORTA–PORTE) │
└──────┬────────┘
│
External Pins

Main Internal Components

✅ 1. CPU (Central Processing Unit)

 Executes instructions
 Performs arithmetic & logic using the ALU

 Uses WREG (Working Register)

Consists of:

 ALU
 Instruction register

 Status flags (Z, C, DC, OV)

✅ 2. Program Memory (Flash ROM)

 Stores user program
 Non-volatile

 Typically 8 KB – 128 KB
✅ 3. Data Memory (RAM)
Includes:

 GPR (General Purpose Registers)

 SFR (Special Function Registers)

✅ 4. Stack (31-level)
Used for:

 Storing return addresses

 Interrupt nesting

Hardware controlled.

✅ 5. Oscillator Module
Provides system clock.

Supports:

 Internal RC oscillator
 External crystal

 PLL frequency multiplier

✅ 6. Timer Modules
PIC18 usually has:

 Timer0: 8/16-bit
 Timer1: 16-bit

 Timer2: 8-bit (PWM support)

Used for:
✅ Time delays
✅ Event counting
✅ Frequency measurement

✅ 7. Capture/Compare/PWM (CCP)
Capture mode
  Captures timer value on external event

Compare mode

 Generates timed output events

PWM mode

 Motor/LED brightness control

✅ 8. ADC (Analog-to-Digital Converter)

Features:

 10-bit resolution

 Multiple analog channels

Converts sensor readings → digital values.

✅ 9. USART (Serial Communication)

Supports:

 Full-duplex

 Baud rate generator

Used for:

 PC communication

 GSM/GPS modules

✅ 10. MSSP (Master Synchronous Serial

Port)
Provides:

 I2C

 SPI

Used for interfacing:

 EEPROMs
 RTC

 Displays
  Sensors

✅ 11. Interrupt Controller

Features:

 Multiple vectors
 Priority levels (High/Low)

 Interrupt enable/disable bits

Sources:

 External interrupts
 UART interrupt

 Timer interrupt

 ADC interrupt

✅ 12. I/O Ports

Ports available:

 PORTA (Analog/Digital pins)

 PORTB (External interrupts)

 PORTC (Serial pins)

 PORTD (Parallel slave port)

 PORTE (Control pins)

Pins are:

 Bidirectional

 TTL level

✅ 13. Watchdog Timer (WDT)

Prevents system lock-up by reset on timeout.

✅ 14. Brown-Out Reset (BOR)

Resets MCU automatically if supply voltage drops.
✅ 15. Power-On Reset (POR)
Resets MCU on power startup.

Pin Diagram Overview (General)

PIC18 pins carry:

 I/O ports
 Interrupt pins

 ADC inputs

 Serial TX/RX

 MCLR reset input

 Oscillator pins OSC1/OSC2

Power Features

PIC18 supports:

 Idle mode
 Sleep mode

 Low-power oscillator

Used for battery applications.

Memory Organization Summary

Memory Type Size Function
Program (Flash) Up to 128 KB Stores code
EEPROM 256–1024 bytes Permanent data
RAM Up to 3936 bytes Runtime variables

Special Function Registers (SFRs)

Examples:

SFR Purpose
TRISx Port direction
PORTx I/O data
INTCON Interrupt control
TMRx Timer registers
ADCON ADC control

Advantages of PIC18

 High speed (Instruction per cycle)

 Rich peripherals

 Low standby current

  Built-in flash rewritability

Applications

PIC18 is used in:

 Automotive control units

 Industrial machines

 Medical devices

 Smart meters

 Robotics

 Communication devices

Or
b i 5
I/O Port Structure of PIC18
Microcontroller
PIC18 microcontrollers support up to 5 bidirectional I/O ports:

 PORTA
 PORTB

 PORTC

 PORTD

 PORTE

Each pin can function as:

✅ Digital input
✅ Digital output
✅ Peripheral function (ADC, UART, PWM, I2C…)

The direction (input/output) is controlled by TRIS registers.

I/O Port Block Diagram (Draw This in Exam)

Draw this clearly:

CPU Data Bus

│
▼
┌─────────────┐
│ TRIS Reg │◄─── Controls Direction Bit
└─────┬───────┘
│ (1 = Input, 0 = Output)
▼
┌─────────────┐
│ Data Latch │◄─── From PORTx write
└─────┬───────┘
│
┌──────▼────────┐
 │ Output Buffer │──► Pin (Output Mode)
└──────┬────────┘
│
▼
┌──────────────┐
│ Tri-State │
│ Buffer │
└──────┬────────┘
│
▼
PIC18 Pin
▲
│
┌───────┴────────┐
│ Schmitt Trigger│
└───────┬────────┘
│
▼
PORTx Read

Important points:

 Write → latch → pin

 Read → pin value (input)

 TRIS bit controls output buffer enable

How Direction Works

TRIS bit Pin Mode Operation
0 Output Data latch drives pin
1 Input Tri-state enabled

Registers used

PORTx Register

 Reads pin level

 Writes to output latch

LATx Register

 Eliminates read-modify-write problems

 Preferred for writing

TRISx Register

 Direction control

TRIS Register Example

Pin TRIS bit (1=input,0=output)
TRISB0 Direction of RB0

Read-Modify-Write Issue

If you write to PORTx directly:

PORTB = PORTB | 0x04;

The read operation reads pin state, not latch,

causing unpredictable output if the pin is loaded.

Solution ✅ Use LAT register:

LATB = LATB | 0x04;

Port MUXing (Alternate Functions)

Example:

PORTC pins may support:

 UART TX/RX
 CCP1/CCP2 PWM output

 SPI SCK/SDI/SDO

PIC pins are multi-functional and configured using Peripheral Pin

Select blocks.

PORTA Features

Supports:

 ADC input channels

 Comparator input pins

 Vref pins

May require disabling analog mode:

ADCON1 = 0x0F; // Make all PORTA pins digital

Typical PORT Registers Table

Port Functionality
PORTA Digital / Analog
PORTB External interrupts
PORTC UART, PWM, SPI
PORTD Parallel Slave Port
PORTE Control functions

Note on Analog Pins

Analog pins are controlled by:

 ADCON0
 ADCON1

 ADCON2

 CMCON (Comparator)

Analog pins must be disabled for digital I/O.

I/O Port Programming Examples

✅ 1. Make PORTB Pins Output
TRISB = 0x00; // All PORTB pins output
PORTB = 0xFF; // Turn all pins ON

✅ 2. Make PORTA Input, PORTC Output

TRISA = 0xFF; // Input
TRISC = 0x00; // Output

✅ 3. Toggle an LED on RB0

TRISBbits.TRISB0 = 0; // Configure RB0 output

while(1)
{
LATBbits.LATB0 = 1; // LED ON
__delay_ms(500);
LATBbits.LATB0 = 0; // LED OFF
__delay_ms(500);
}

✅ 4. Read Switch on RA0 and Light LED on

RB0
TRISA = 0xFF; // RA0 as input
TRISB = 0x00; // RB0 as output

while(1)
{
if(PORTAbits.RA0 == 1)
LATBbits.LATB0 = 1;
else
LATBbits.LATB0 = 0;
}

✅ 5. Binary Counter Display on PORTD

TRISD = 0x00;

for(int i=0; i<256; i++)

{
LATD = i;
__delay_ms(200);
}

Input Buffer Types

PIC input buffers are:

 TTL compatible

 Schmitt trigger

Ensures:

 Noise immunity
  Stable logic levels

Weak Pull-ups

Some ports (PORTB) support internal pull-ups:

[Link] = 0; // Enable pull-ups

Output Driver Characteristics

Output pins can drive:

 ~25 mA each

 200 mA per port max

Suitable for LED driving (with resistor).

Interrupt On Change (IOC)

PORTB pins RB4–RB7 can generate interrupts on edge change:

 Used for keypads

 Sensor triggers

Applications of PIC I/O Ports

 Keypad interfaces
 LED/7-segment displays

 ADC sensor input

PART – C (Marks 1*15 = 15)
[Link]. Questions BLT CO Marks
16. a i
LED-Based Binary Counter using
Timer in 8085
The goal is to increment a binary count (0000 → 1111) and display it on
LEDs connected to the output port.
A delay between each increment is generated using Timer-0
(implemented by software delay loops because 8085 has no hardware
timer block).

System Concept

 8085 generates binary values (0–15).

 Values are transferred to output port.

 LEDs show the binary count.

 Timer-0 (software delay) controls the rate.

Block Diagram (Draw this in exam)

┌──────────┐
│ 8085 CPU │
 └────┬─────┘
│ Data Bus
┌───▼────────┐
│ 8255 PPI │
│ Port-B │
└───┬────────┘
│ Output lines PB0-PB3
│
┌────▼───────┐
│ LED Array │
│ (4 LEDs) │
└────────────┘

Circuit Diagram (Logic)

8255 PORT-B
┌─┬─┬─┬─┬──────┐
PB0 ─────>│●│ LED1 (LSB)
PB1 ─────>│●│ LED2
PB2 ─────>│●│ LED3
PB3 ─────>│●│ LED4 (MSB)
└─┴─┴─┴─────────┘
|
GND

Each LED uses a resistor (~330Ω) to limit current.

Port Initialization

The 8255 is programmed in Mode-0 (Simple Output):

 PORT-B → Output (for LEDs)

 PORT-A, PORT-C → Don’t care

Control Word: 10000000B = 80H

Working Principle

1. Initialize 8255 for output.

2. Load register with count 00H.

3. Send value to output port → LEDs glow accordingly.

4. Call delay routine (Timer-0 concept).

5. Increment count.

6. Repeat.

LED patterns represent binary values:

Count LED4 LED3 LED2 LED1

0000 OFF OFF OFF OFF
0101 OFF ON OFF ON
1111 ON ON ON ON

Timer-0 Software Delay

Because 8085 doesn’t have a built-in timer hardware (like modern

MCUs), delays are created using:

✅ Register decrement loops

✅ CALL/RET cycles

Thus called software timer.

Instruction Timing (Reference)

 8085 frequency normally = 3.072 MHz

 1 machine cycle = 325 ns

 Delay loop consumes machine cycles → produces timing.

8085 Assembly Program

MVI A, 00H ; Initialize count
OUT 02H ; Send to LEDs
MVI C, 10H ; Loop 16 times

LOOP: OUT 02H ; Output pattern

CALL DELAY ; Timer delay
INR A ; Increment counter
DCR C ; Decrement loop
JNZ LOOP ; Repeat until 16 counts
JMP LOOP ; Continuous operation

;----------------------------------
DELAY: MVI D, FFH
D1: MVI E, FFH
D2: DCR E
JNZ D2
DCR D
JNZ D1
RET
;----------------------------------
Explanation of Code

✅ MVI A,00H

Load accumulator with starting binary value.

✅ OUT 02H

Send accumulator contents to port-02 where LEDs are connected.

✅ MVI C,10H

Initialize loop counter (16 counts from 00–0F hex).

Delay Routine

The nested loops produce a time delay:

 Outer loop (D register)

 Inner loop (E register)

Each loop consumes several T-states → LED glow becomes visible to

human eye.
LED Output Example

When A = 05H → 0101B

LED output:

PB3 PB2 PB1 PB0

0 1 0 1

So LEDs turn ON/OFF accordingly.

Port Address Mapping Example

Typical 8255 port mapping:

Port Address
Port-A 00H
Port-B 01H
Port-C 02H
Control 03H

In this example, we used Port-B.

Why Binary Counter?

It demonstrates:

 Data output transfer

 Port interfacing

 Timing control

 Visual binary representation

Applications

✅ Digital clock circuits

✅ Timing experiments
✅ Learning machine cycles
✅ Display multiplexing basics

Advantages

✔ Easy to verify binary counting visually

✔ Good for lab experiments
✔ Demonstrates Timer Delays

Precautions

 LEDs must have current limiting resistors.

 Delay value must be slow (human eye ~20–30ms minimum).
  Output pins must sink/source limited current.

Conclusion

The LED-based binary counter using 8085:

✅ Uses 8255 programmable peripheral interface

✅ Generates binary patterns 0000 to 1111
✅ Displays via LEDs
✅ Delay is produced by software timer loops

This experiment demonstrates I/O interfacing, binary counting, and

software timing, making it an essential part of 8085 microprocessor
laboratory experimentations.

Or
b i
Interfacing of DAC with 8051 /
8085 to Generate Analog Waveform
Digital-to-Analog Converter (DAC) is an important peripheral that
converts digital (binary) data from the microprocessor / microcontroller
into corresponding analog voltage or current.

DACs are used for generating:

✅ analog audio
✅ ramp wave
✅ sine / triangular wave
✅ motor control
✅ instrumentation systems

Commonly used IC: DAC0808 or MC1408

Need for DAC

Microprocessors and microcontrollers are purely digital devices.

Real-world signals (sound, temperature, speed) are analog.

Hence DAC is needed to:

 Convert digital output into analog voltage/current

 Interface digital electronics with analog world

Basic Principle

DAC converts binary input into proportional analog output:

Vo=D2n−1×VrefV_o = \frac{D}{2^n - 1} \times V_{ref}Vo=2n−1D

×Vref

Where:

 D → digital value
  n → number of bits (DAC0808 → 8-bit)

Block Diagram (Draw this for full marks)

┌──────────────┐
│ 8085/8051 │
│ µP/µC Unit │
└──────┬───────┘
│ 8-bit data bus
┌──────▼───────┐
│ Latch │ (74LS373)
└──────┬───────┘
│ 8-bit output
┌──────▼───────┐
│ DAC0808 │
└──────┬───────┘
│ Analog output
┌──────▼───────┐
│ Op-Amp LM741 │ (current→voltage converter)
└──────┬───────┘
│
Analog Output

Why Latch?

Microprocessor changes data during execution.

Latch holds data stable at DAC input.

Output Stage

DAC0808 provides current output.

We must convert it into voltage using op-amp:

Vout = - Iout × Rf

Rf typically = 10 kΩ

Pin Description (DAC0808)

Pin Function
D0–D7 Digital inputs
Vref Reference voltage
Iout Current output
Vcc +15V supply
GND Ground

Interfacing with 8085 – Port Address Mapping

Example 8255 ports:

Port Address
Port-A 00H
Control 03H

Port-A used to send digital values to DAC.

8085 Assembly Program to Generate Ramp Waveform

MVI A,00H ; Start value
LOOP: OUT 00H ; Send to DAC
INR A ; Increment digital value
 CALL DELAY ; Visible increase
JMP LOOP ; Repeat forever

DELAY: MVI B,FFH

D1: MVI C,FFH
D2: DCR C
JNZ D2
DCR B
JNZ D1
RET

This produces ramp (saw-tooth) waveform.

8051 Program (Same task)

ORG 0000H
MOV A, #00H

LOOP: MOV P1, A ; P1 connected to DAC

INC A
ACALL DELAY
SJMP LOOP

DELAY: MOV R1, #0FFH

L2: MOV R2, #0FFH
L3: DJNZ R2, L3
DJNZ R1, L2
RET
END

Waveform Generation

✅ Ramp Waveform

Digital count goes 00,01,02,…,FF

Produces increasing analog ramp.

/ / / /
/ / / /
/ / / /

✅ Triangular Wave

Count up → Count down (reverse increment)

✅ Staircase Wave

Small delay increments produce steps.

Working Explanation

1. Microprocessor outputs 8-bit data

2. Latch holds value

3. DAC converts binary → proportional analog

4. Op-amp converts current → voltage

5. Output visible on oscilloscope

 Internal Architecture of DAC0808 (Draw this also)
Binary Weighted Resistor Network
│
▼
Summing Amp ---> Current Output

Resistors are weighted:

 Least significant bit → largest resistance

 Most significant bit → smallest resistance

Advantages of DAC Interfacing

 Smooth analog output

 Fast conversion

 Simple digital control

Precautions

 Proper reference voltage

 Stable power supply

 Op-amp offset must be adjusted

Applications

✅ Function generators
✅ Speech synthesis
✅ Motor speed control
✅ Robotics
✅ Signal conditioning

Conclusion

Interfacing DAC with 8051/8085 enables generation of real-world

analog waveforms from digital values. Using latch and op-amp,
DAC0808 can produce clean ramp/triangle/staircase waveforms. This is
fundamental for digital-to-analog signal processing and laboratory
experiments.

Interfacing of DAC with 8051 / 8085 to Generate Analog

Waveform
Digital-to-Analog Converter (DAC) is an important peripheral that converts digital (binary) data from the
microprocessor / microcontroller into corresponding analog voltage or current.

DACs are used for generating:

✅ analog audio
✅ ramp wave
✅ sine / triangular wave
✅ motor control
✅ instrumentation systems

Commonly used IC: DAC0808 or MC1408

📌 Need for DAC

Microprocessors and microcontrollers are purely digital devices.
Real-world signals (sound, temperature, speed) are analog.

Hence DAC is needed to:

 Convert digital output into analog voltage/current

 Interface digital electronics with analog world

🧩 Basic Principle
DAC converts binary input into proportional analog output:

Vo=D2n−1×VrefV_o = \frac{D}{2^n - 1} \times V_{ref}Vo=2n−1D×Vref

Where:

 D → digital value

 n → number of bits (DAC0808 → 8-bit)

🧱 Block Diagram (Draw this for full mark