Computer Organisation and 22EC363 3rd semester AY 2025-26

Architecture

MODULE – 3
Basic Processing Unit

- Prepared by,
Prof. Aishwarya N
ECE Dept., DSCE 1
 MODULE - 3 SYLLABUS (8 hours)
1. Fundamental Concepts of a processor
- Single bus organization
- Register Transfers Pre-requisites :- DEDV Concepts
2:1 MUX, Encoder and decoder,
- Performing an Arithmetic or Logic Operation
D-F/F and Counters (T- F/F)
- Fetching and storing a word from memory
2. Execution of a complete Instruction, Branch
Instructions - Operations of a control unit
3. Multiple Bus Organization
- Operations of a control unit
4. Hardwired control unit
5. A Complete Processor
6. Micro-programmed control unit

Text Book: Carl Hamacher, Zvonko Vranesic, SafwatZaky, “Computer Organization”, 5th Edition, McGraw Hill, India, 2002
Chapter – 5 2
1. Fundamental Concepts of a processor Operations of a control unit on Multiple Bus Organization
- Single bus organization [Link]
3. Multiple Bus Organization
[Link] 5. Hardwired control unit
7. Micro-programmed control unit
- Register Transfers [Link]
- Performing an Arithmetic or Logic Operation
- Fetching and storing a word from memory 6. Complete Processor ----

[Link]

3. Execution of a complete Instruction, Branch

Instructions - Operations of a control unit
[Link]
vBb6l

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 Data path

Figure: The Computer:Top-Level Structure

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In addition to the ALU & the control circuitry, the processor contains a number of registers
used for several different purposes.

Instruction register (IR)

• Holds the instructions that is currently being executed.
• Its output is available for the control circuits which generates the timing signals that
control the various processing elements in one execution of instruction.

Program Counter (PC)

• This is another specialized register that keeps track of execution of a program.
• It contains the memory address of the next instruction to be fetched and executed.
• It’s like a bookmarker

Besides IR and PC, there are N-general purpose registers R0 through R(N-1)

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The components on
the CPU (internal to
the CPU) are connected
by an internal bus (not
shown explicitly
CPU and memory are
in diagram)
connected via external
(system) bus – Address ,
Data and Control bus, as
shown in diagram

Memory Address Register (MAR)

▪ A register that holds the address of the data to be fetched from memory or stored in RAM.

Memory Data Register (MDR)

▪ A register that stores the data being transferred to and from the immediate access storage.
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[Link]

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1. Fundamental Concepts
Standards
• Instructions are stored in main memory.
• Program Counter (PC) points to the next instruction.
• Typically, the instructions are of 4 bytes, hence the instruction
memory is addressed in terms of 4 bytes (word length = 32
bits).
• When an instruction is executed, PC is incremented by 4 to
point to the next instruction.
• PC is incremented by 4 to point to the next instruction.
• In that case, all instructions starts from an address that is
multiple of 4 (last 2 bits 00).

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MAR  [PC]
MDR  Mem[MAR]
IR  [MDR]

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( Z, Y, TEMP) 11
MOV LOCA, R1

MOV R0, LOCX

MOV R0, T1

ADD R0, LOCA

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 Fundamental Concepts

• Processor fetches one instruction at a time and

perform the operation specified.

• Instructions are fetched from successive memory

locations until a branch or a jump instruction is
encountered.

• Processor keeps track of the address of the memory

location containing the next instruction to be fetched
using Program Counter (PC).

• Instruction Register (IR) holds the current instruction being executed.

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 Executing an Instruction
• Fetch the contents of the memory location pointed to by
the PC. The contents of this location are loaded into the IR
(fetch phase).
MAR  [PC]
IR ← [[PC]] (OR) IR ← Mem[PC] (OR) MDR  Mem[MAR]
IR  [MDR]

• Assuming that the memory is byte addressable, increment

the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the IR
(execution phase).

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 Executing an Instruction
• Transfera word of data from one processor register to
another or to the ALU.
• Perform an arithmetic or a logic operation and store the
result in a processor register.
• Fetchthe contents of a given memory location and load
them into a processor register.
• Store a word of data from a processor register into a given
memory location.

To know how these operations are implemented, we need to know the

internal structure of the processor.
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 Processor Organization – Single Bus Structure
Explain the single bus organisation of the processor with a neat diagram

System bus
(Control bus)
Eg:/ Read memory,
Write to memory
System bus
( Address and
Data bus)
Note:
• n → no. of bits that the register can hold, also,
width of the bus (no. of wires in the bus => the
number of parallel wires in the bus that carry data
parallelly between registers and the ALU.)
Thus, n = word length of the processor = register
width = bus width (in bits)
❑ For example, if the processor is 32-bit,
→ each register is 32 bits wide,
→ and the internal processor bus also has 32
parallel lines.

• N → no. of GPRs

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• The various functional blocks of the CPU can be organized and interconnected in a variety of ways.

• Fig. 7.1 shows a simple organization in which the arithmetic and logic unit (ALU) and all the registers are connected using a
single common bus. This bus is internal to the processor.

• The data and address lines of the external memory bus are connected to the processor bus via Memory Data Register
(MDR) and the Memory Address Register (MAR). This is also shown in Fig. 7.1.

• Data may be loaded into MDR either from the memory bus or from internal processor bus. Data stored in MDR may be
placed on either bus.

• The input of the MAR is connected to the internal bus and its output is connected to the external bus.

• The control lines of the memory bus are connected to the instruction decoder and control logic block. This unit is
responsible for issuing the signals that control the operation of all the units inside the processor and for interacting with the
memory bus.

• The functional elements like PC, MAR, MDR, R0, R1 etc., are connected to the internal bus. MAR and MDR are also
connected to the external bus. The bus connections are shown as arrow with slash notation.

• The number(N) and function of processor registers R0 through R(N–1) vary from processor to processor. 18
• Some may be general purpose; others may be special purpose registers like stack pointer or index registers.

• Three registers Y, Z, TEMP are transparent to the programmer, i.e., they are never referred directly by an
instruction. They are used by the processor for temporary storage during execution of some instructions.

• The multiplexer MUX selects either the output of register Y or a constant value 4. This is provided as input A
of the ALU.
o The constant value is used to increment the contents of the PC.

• The B input of the ALU is obtained directly from the processor bus.
• Thus, the 'select' line S of MUX can be either select4 or selectY.
• ALU performs the operations on operands A and B, and produces a result which is stored in Z initially. The type of
operation to be performed is indicated by Control Unit(CU) after decoding the instruction (using CU’s instruction
decoder circuit) and is, based on opcode in the instruction.
• The registers, the ALU and the internal bus are collectively referred to as ‘datapath’ of the processor.

Where is stack pointer,

Accumulator, overflow flag, carry
flag in Fig 7.1 ? 19
Register Transfers
Control switches

Ri out , Ri in
Are also called as gating signals

When Ri out or Ri in =0 ,
no data transfer between
processor bus and register
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 • Ri out , Ri in
What is the size of gating signals w.r.t Register Ri
PC,MAR, R0,Y, MDR, Z , • Yin is gating signal for
processor bus in Fig 7.1, register Y
if word-length of the • Zin and Zout are gating
computer is 8 bits ? signals for register Z

Similarly, we have, gating

signals for all registers on
Why Yin, MARin only? the CPU

If the processor bus is 8

bits, what is the size of
MDR and data bus?

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Example 1

MOV R2, R1

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 In the figure,
Register Ri → n=1 bit →
1 no. of D F/Fs

• Ri out -> enable signal of

tri-state buffer
• Ri in -> select signal of 2:1
MUX

• Thus Riout , Ri in
are called as control /gating signals

Register Ri → D Flip-Flop at the hardware

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NOTE:
Which circuit to use to
generate clock?

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• All operations and data transfers within the processor take place within time periods defined by processor clock.
• The control signals that govern particular transfers are asserted at the start of clock cycle. The registers consist of edge-
triggered flip-flops.
• A ‘clocking methodology’ defines the timing of read and write.
➢ If a signal is written at the same time it is read, the final value is ambiguous.
➢ Hence, edge-triggered clocking methodology is used in all the processors.
• When edge-triggered flip-flops are not used, two or more clock signals may be required for proper transfer of data. This is
known as multiphase clocking.

Carry flag → 1 bit → 1 D- FF

Register Ri , Z etc. → n bits → n no. of D F/Fs

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 Performing an Arithmetic or Logic operation
• The ALU is a combinational circuit which performs arithmetic and logic operations on two operands applied at its A and B
inputs.
• One of the operands is the output of the MUX and the other operand is obtained directly from the processor bus, as shown
in Fig. 7.1.
• The result is stored temporarily in register Z.
Example 1

ADD R2, R1

The signals are activated for the duration of the clock cycle corresponding to that step. Once operation is completed, control
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signals are set back to 0. All the other signals are inactive.
10. Memory Operations

Load / Fetch / Read Store / Write

• In the load operation, the contents of the specified • In the store operation, the data from the processor is
memory location are read by the processor. stored in the specified memory location.
• For load operation, processor sends the address of the • For store operation processor, sends the address of the
memory location whose contents are to be read and memory location where the data is to be written is on
generates the appropriate read signal to indicate that it is the address lines, the data to be written on the data
a read operation. lines and generates the appropriate write signal to
• The memory identifies the addressed memory location indicate the store operation.
and sends the contents of that memory location to the • The memory identifies the addressed memory location
processor and writes the data sent by the processor at that
• The memory content doesn’t change after reading. location
• Destroys / overwrites the former contents of that
location.

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Fetching (Reading / loading ) a word from memory and
Storing (writing) a word to memory

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29
 Databus
(Memory) Data bus

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MFC is from
memory to CPU,
sent via control
bus

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 Example 1 MOV (R2), R1

Example 1 MOV R2, (R1)

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2. Execution of complete instruction and branch instruction
•We select a set of 14 instructions.
• Discuss the control signals required to execute these instructions on the single-bus processor architecture.
1) ADD R2, R1 // R1 = R1+R2
2) ADD LOCA,R1 // R1 = R1 + Mem[LOCA]
3) LOAD LOCA, R1 // R1 = Mem[LOCA]
4) STORE R1, LOCA // Mem[LOCA] = R1 Refer to Faculty’s handwritten
5) MOVE R2, R1 // R1 = R2 notes shared on GCR’s classwork
section for answers with
6) MOVE #10, R1 // R1 = 10
comments
7) BR LOCA // PC = LOCA
8) BZ LOCA // PC = LOCA if Zero flag is set
9) INC R1 // R1 = R1 + 4
10)DEC R1 // R1 = R1 – 4
11)HALT //Machine Halt
12) ADD R1, R2, R3 // R3 = R1 + R2
13)ADD (R3), R1 // R1 = R1 + data at address pointerd by R3
14) ADD (R3)+, R1 // R1 = R1 + data at address pointerd by R3 and after fetching R3, increment R3 i.e. R3 = R3 +4

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ADD R2, R1

ADD R2, R1

Control Actions ( Control sequence)

Fetch
phase
Decode
phase
Execution
phase
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ADD LOCA, R1

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LOAD LOCA, R1

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 STORE R1, LOCA

• Address field
• Immediate field Different fields of IR
• Offset field 37
MOV R2, R1

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MOV #10, R1

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40
Unconditional branch

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 Move N,R1

Branching LOOP :
Clear R0

Determine address of
"Next" number and add
"Next" number to R0
Program and store result in R0
loop Decrement R1

Branch target Branch_if_R1>0 LOOP BGT R1,0,LOOP

Move R0,SUM
Conditional branch

•
•
•
SUM
N n
NUM1
NUM2

•
Figure 2.10. Using a loop to add n numbers.
•
•
NUM n
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Conditional branch

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ADD (R3),R1

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48
ADD (R3)+,R1

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MOV (Rsrc),Rdst

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Exercise 1,2,3:
Write the control sequence for the instruction below, on a single processor bus architecture
i) MOV (R2), R1
ii) MOV R2, (R1)
iii) SUB R1, R2, R3
iv) MUL R0, R5

Write the instruction based on the information given. Mention the addressing mode . Also write the control actions.

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ADD R1,R2, R3 (SINGLE PROCESSOR BUS ARCHITECTURE)
R3  [R1] + [R2]

R1 and R2 cannot be placed on

the bus at the same time, because
there is only one processor bus.
Hence 2 separate steps (additional
step) are needed

i.e., only register output can be

enabled during a clock cycle, in a
single bus architecture.
(Disadvantage)

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3. Multiple Bus Organization

Explain the multi-bus organisation of the processor with a neat diagram

• Most processors today, provide multiple datapath inside CPU

so that several transfers can take simultaneously

How data transferred

from MDR to IR? 53
• Fig. 7.10 shows three-bus organization of the CPU.
• All general-purpose registers are combined into a single block called register file.
• The register file has three parts:
o Two outputs allowing the contents of two different registers to be simultaneously placed on the buses A and B.
o The third part allows the data on bus C to be loaded into a third register during the same clock cycle.
• Buses A and B can transfer two source operands to A and B inputs of the ALU.
• The result is transferred to the destination over C bus during the same cycle.
Therefore, a three-address (3–operand) instruction of the form OP Rsrc1, Rsrc2, Rdst can be executed in one clock cycle after
the fetch phase.
• Therefore, there is no need for temporary registers Y and Z (as in Fig. 7.1).
• Another feature is the provision for Incrementer unit to update the value of PC, which eliminates the need to add a value 4
to program counter using the ALU.
• MDR and MAR are connected to system bus

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 OP SRC1, SRC2. DESTN

Here, OP is –
DESTN  SRC1 – SRC2

Control sequence SUB R2,R3, R1

Example 1

Fetch
phase Decode
phase
Execution phase 56
Control sequence
Example 2

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Exercise 4:
For each of the control sequence given, identify - the instruction, it’s addressing mode and the processor bus organization.
Draw the processor bus organisation diagram.
i)
Steps Control Sequence
1 PCout, MARin, Read, Select4, Add, Zin
2 Zout, PCin, Yin, MDRinE, WMFC
3 MDRout, Irin
4 R5out, Yin
5 R3out, SelectY, Add, Zin
6 Zout, R5in, End
ii)
Steps Control Actions
T1 PCout, R = B, MARin , READ, IncPC
T2 MDRinE, WMFC
T3 MDRoutB , R = B, Irin
T4 R4outA , R5outB , SelectA, MUL, R3in , End

Exercise 5:
Write the control sequence for the instruction MUL R4, R5, R4 a single processor bus architecture.
Repeat for 3-level processor bus architecture
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5. Hardwired control unit
Standards

ADD R2, R1

Execution
phase

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Opcodes
Fig 7.14

Examples of control
signals ?

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 If maximum steps is 8, then
what is the configuration of
the step -decoder ?

If maximum instructions in
ISA for a processor is 30,
then what is the
configuration of the
instruction decoder ?

RISC 63
Consider (only)
3 instructions as an
example ADD R2, R1 ADD LOCA, R1

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 Part of
HARDWIRED CU

• PC out -> enable signal of

tri-state buffer
• PC in -> select signal of 2:1
MUX
(Represented as control switches/
gating switches in Fig 7.2)
PC out
PCin
Diagram when
Register PC → D Flip-Flop at the hardware ( 1 bit)
PC size > 1 bit
(say 2 bits) ? 67
 • The design objective for any processor is to reduce the number of clock cycles
6. A Complete Processor
required to execute an instruction. Standards
• Ideally, we expect an operation to be completed in one cycle.
• Towards this goal, instead of a single bus structure, we designed a multi bus
structure.
• However, single-cycle processor design is inefficient and difficult to implement since
every instruction execution has to be completed in one clock cycle.
• Performance improvement can also be achieved if fetch and execute phases can be
overlapped. This technique called pipelining is a feature of all modern processors.
• Latest processors include an instruction unit, which fetches many instructions in
advance and places them in a ready queue.
• Other enhancement includes having multiple functional units such as Integer Unit
and Floating-point unit which operate on respective type of data in parallel.
• A powerful processor can be designed using the structure shown in Fig. 7.12.
• As shown, the processors may have separate instruction cache and data cache for
storing instructions and operands.
• Only if information is not available in cache, processor has to access the main
memory. This reduces the memory access time and improves the performance.
• The processor is connected to the system bus and to the memory by means of a bus
interface.
• Using multiple units and pipelining, it is possible to design very powerful processors.
• Processors that execute instructions at a rate exceeding one instruction per clock
cycle are called superscalar processors.

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7. Micro-programmed control unit
Standards

Opcodes

Fig 7.18

Sequence of Operations
I. Instruction fetched → loaded into IR
II. Starting Address Generator reads opcode → gives starting
address
III. Address loaded into μPC
IV.μPC fetches microinstructions sequentially from Control Store
V. Each microinstruction generates control signals (CW) to
execute the instruction

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• A microprogrammed control unit generates control signals by reading microinstructions (Control Words – CWs) stored in a memory called the
Control Store (CS).
• Each machine instruction (like ADD, LOAD, etc.) has a corresponding microprogram — a sequence of microinstructions stored in CS.
• IR (Instruction Register):
Opcodes
• Holds the current instruction fetched from memory.
• The opcode part of this instruction determines which microprogram needs to be executed.
• Starting Address Generator:
• Takes the opcode from the IR.
• Generates the starting address of the corresponding microprogram in the Control Store.
• This starting address is then loaded into the microprogram counter (μPC).
• μPC (Microprogram Counter):
• Works like a program counter but for microinstructions.
• Points to the current microinstruction(control word) in the control memory.
• After each microinstruction is executed, it is incremented automatically by the clock to fetch the next microinstruction.
• Sometimes, it can be loaded with a new address (for example, for branching in microprogram: Fig 7.20)
• Control Store (CS):
• A ROM that stores all the micro-routines (Acts as a Loop up table- LUT).
• The address given by μPC is used to read the current microinstruction (CW).
• The CW is decoded to generate actual control signals for processor operations.
Note: The Fig. 7.18 shown cannot handle branch instructions !
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 Opcodes

Why Starting Address Generator is Required ?

• Each machine instruction (like ADD, SUB, LOAD) corresponds to a different sequence of microinstructions stored at different
locations in the control store.
• When a new instruction is loaded into the IR, the control unit must know where in the control memory its microprogram
begins.
• The Starting Address Generator performs this mapping:
• It uses the opcode of the instruction.
• Outputs the starting address (entry point) of that microprogram.
• Without this unit, the control unit wouldn’t know where to begin fetching microinstructions for each new instruction 71
ADD R2, R1 ADD R2, R1
Addr-
Control Actions ( Control sequence) ess
0x00
0x04
0x08
0x0C
0x10

Opcodes
Example 1

Control Store also known as Control

Memory (CM)
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 Opcodes

Example 2

Addr-
ess
0x00
0x04
0x08
0x0C
0x10

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 ADD R2, R1
Micro-program / micro-routine
is a sequence of control
Addr- steps/control actions for a
ess given machine instruction

0x00
Micro-program /
0x04
0x08
0x0C
0x10

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 Select signal S of MUX

Select4 => Select S=1

SelectY => Select S = 0

Deeper Practical Understanding

1. How can a single 1-bit constant “4” and an n-bit register Y
both be valid inputs to the same MUX? (size difference ?)
2. How can we design a mux which takes n -bits as inputs I0 and
I1? We usually take I0, I1 as inputs for 2:1 mux where I0 and I1
is only 1 bit, isn’t it ?
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76
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 ⌈log₂(100)⌉ is read as ceiling of log₂(100)
7:128 Decoder

Analogy
uPC v/s PC ? PC: Like a page number in a book — tells you which chapter instruction to read next.
μPC: Like a line number inside that page — tells you which micro-step of that instruction is being executed.

Analogy
•Machine Instruction → Brushing your teeth
• This is the overall task given to the “processor” (you).
•Microinstructions → The small steps needed to perform that task:
• Take the toothbrush
• Open the toothpaste
• Squeeze the paste
• Brush teeth
• Rinse mouth
Each microinstruction activates certain “control signals” (actions by muscles or hands), just like the control unit activates control
signals in hardware.
i.e. Each Micro-instruction performs one or more micro-operations. 79
 Aspect Hardwired Control Unit Microprogrammed Control Unit
Speed Faster (direct hardware paths) Slower (memory fetch overhead)
Flexibility Low (hardware redesign needed) High (software-like microprogram edits)
Complexity High for complex logic for complex instructions Easier to design for complex instructions
• Higher hardware cost • Lower, but adds memory cost
Cost • Generally, more costly to redesign (hardware • Cheaper to update (software-level
changes) changes)
Power Consumption Lower (no memory access) Higher (due to control memory)
Error Handling Difficult to debug/fix Easier (microprogram can be patched)
Scalability Good for simple/fixed ISCs Better for evolving/complex ISCs
Control signals are generated by executing
Control signals are generated by logic circuits (using
Definition microinstructions stored in a control
gates, flip-flops, decoders, etc.)
memory
Implemented with a microprogram stored
Implementation Implemented with hardware circuits
in ROM or control memory
Common in CISC processors (where
Common in RISC processors (where speed and
Use Cases complex instructions need
simplicity are critical)
microprogramming)
Example Intel 8085, ARM processors Intel 8086, VAX-11 series

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 Control Unit Type Advantages Disadvantages
➢ Faster execution speed (direct
▪ Low flexibility; requires hardware
hardware paths, minimal delays)
redesign for changes
➢ Lower power consumption (no
▪ High design complexity and cost for
memory access)
Hardwired complex instruction sets
➢ Simpler implementation for fixed,
▪ Difficult to debug or modify post-
simple instruction sets
fabrication
➢ More reliable in terms of timing
▪ Larger chip area for intricate logic
predictability
➢ High flexibility; easy to modify
instruction set via microprogram
▪ Slower execution (overhead from
updates
fetching micro-instructions)
➢ Simpler design process for
▪ Higher power consumption due to
complex CISC architectures
control memory access
Microprogrammed ➢ Easier debugging and error
▪ Requires additional hardware
correction (software-like
(control store memory, μPC)
patching)
▪ Potential for microprogram bugs
➢ Supports emulation of new
affecting reliability
instructions without hardware
changes

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 Aspect Program Counter (PC) Microprogram Counter (μPC)
Holds the address of the next instruction to be fetched Holds the address of the microinstruction to be fetched from
Meaning
from main memory. control memory (control store).
Used in Main processor datapath. Microprogrammed control unit.
Level of operation Machine level (instruction level). Microinstruction level (control level).

Points to Next program instruction in main memory. Current microinstruction in the control store.
Type of memory
Main memory (RAM) or instruction cache. Control memory (ROM used to store microprograms).
accessed
Increment Incremented by instruction length (e.g., +1 or +4 bytes). Incremented by 1 after each microinstruction execution.
Ensures sequential execution of microinstructions for one
Purpose Ensures sequential execution of program instructions.
machine instruction.
Loaded with the start address of the microprogram
Reset / Load Loaded with the start address of the program or branch
corresponding to the current instruction (from opcode). or
condition target.
branch target.
Depends on number of microinstructions (usually smaller, e.g.,
Typical width Depends on address bus width (e.g., 16, 32, or 64 bits).
8–12 bits).

Incremented by ALU or Incrementer circuit Clock

PC = 1004 → next instruction fetched from memory μPC = 010 → microinstruction fetched from control store
Example
address 1004. address 010.

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Exercise 6 :
Write the control sequence for MOV R4, R5 a single processor bus architecture.
Repeat for 3-level processor bus architecture
Outline how the microprogrammed control unit generates control signals for this.
Also, show how hardwired control unit generates R4in control signal

Exercise 7:
a) Explain the concept of a hardwired control unit with a neat block diagram.
b) Describe how control signals are generated in a hardwired control unit.
c) Differentiate between hardwired control and microprogrammed control.
d) What are the advantages and limitations of a hardwired control unit?
e) Explain the organization of a microprogrammed control unit with a neat diagram.
f) Differentiate between horizontal and vertical microinstructions/ CWs.
g) Construct a microprogram (Micro-routine) for the instruction “ADD R1, R2” assuming a simple processor.
h) Compare the flexibility and design trade-offs of microprogrammed vs. hardwired control.
i) Explain how branching is handled within a microprogrammed control unit.
j) Analyze why a single-cycle processor design is inefficient and discuss how superscalar processors overcome this limitation
using multiple functional units and caches. What other features can be introduced to improve the processor’s
performance.
k) Justify the names hardwired and micro-programmed Control unit.

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Pre-
requisites
ENCODER
DECODER
MUX
Pre-requisites

Clock edges

88
Pre-requisites

APPLICATION

• Shift registers
Pre-requisites
Counter is a sequential circuit consisting of a set of flip-flops which can go
through sequence of states. It is used to count the number of clock cycles.

Counters internally consist of flip-flop ( JK / T )

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Questions to ponder and self-explore!
( Not for SEE and CIE )

1. “ALU is a combinational circuit”. But, for implementing shift and rotate instructions, don’t we need sequential circuits ?
(Also, in module2, we saw sequential multiplier → shift operation => shift registers built using D – F/Fs at the hardware)

2. “In Fig. 7.1, when we label the internal processor bus as n bits, it refers to data width (register/ALU width => MDR, R0 to
R(N-1), Z , TEMP, Y, MDR, operand A and operand B). But — the PC width, MAR width is determined by the address bus width,
which may be different from n.”
a) Assume address bus is 16 bits and process bus is 8 bits. How it handles 16-bit address in PC ? Can processor handle all
16-bits at once ?
b) What is the length of IR register ? Relate to RISC and CISC ISA architecture.

3. If maximum address of a memory is 0x200 (i.e., 200H), what is the length (width) of address bus ?
4. Why tri-state gate is also called tri-state buffer ?
5. To increment PC , we use ALU. But, to increment uPC , we use clock , why ?

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NOTE:
1. Students are recommended to study from PPT mainly
2. If the content in ppt is to small, refer textbook notes shared for detailed explanation, to write
in exam.
3. Solutions to problems /exercise – solved in class, refer to students who have taken class notes.
4. Write Working Column wherever applicable

Resources used in preparing this PPT

a. Text book –L Krishnananda‘s “Computer organization”
b. NPTEL course
• [Link]
c. VTU notes
d. Google, Gen AI etc.

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